Index: lib/Transforms/InstCombine/InstCombineCompares.cpp =================================================================== --- lib/Transforms/InstCombine/InstCombineCompares.cpp +++ lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -115,6 +115,15 @@ IsSigned); } +/// isBranchOnSignBitCheck - Given an exploded icmp instruction, return true if +/// any use of this comparison is a branch on sign bit comparison. +static bool isBranchOnSignBitCheck(ICmpInst &I, bool isSignBit) { + for (auto *U : I.users()) + if (isa(U)) + return isSignBit; + return false; +} + /// isSignBitCheck - Given an exploded icmp instruction, return true if the /// comparison only checks the sign bit. If it only checks the sign bit, set /// TrueIfSigned if the result of the comparison is true when the input value is @@ -3271,6 +3280,40 @@ // bits, if it is a sign bit comparison, it only demands the sign bit. bool UnusedBit; isSignBit = isSignBitCheck(I.getPredicate(), CI, UnusedBit); + + // Canonicalize icmp instructions based on dominating conditions. + BasicBlock *Parent = I.getParent(); + BasicBlock *Dom = Parent->getSinglePredecessor(); + auto *BI = + Dom ? dyn_cast_or_null(Dom->getTerminator()) : nullptr; + ICmpInst::Predicate Pred; + BasicBlock *TrueBB, *FalseBB; + ConstantInt *CI2; + if (BI && match(BI, m_Br(m_ICmp(Pred, m_Specific(Op0), m_ConstantInt(CI2)), + TrueBB, FalseBB))) { + assert(TrueBB != FalseBB && "TrueBB must not be equal to FalseBB"); + ConstantRange CR = ConstantRange::makeAllowedICmpRegion(I.getPredicate(), + CI->getValue()); + ConstantRange DominatingCR = + (Parent == TrueBB) + ? ConstantRange::makeAllowedICmpRegion(Pred, CI2->getValue()) + : ConstantRange::makeAllowedICmpRegion( + CmpInst::getInversePredicate(Pred), CI2->getValue()); + ConstantRange Intersection = DominatingCR.intersectWith(CR); + if (Intersection.isEmptySet()) + return replaceInstUsesWith(I, Builder->getFalse()); + if (!isZBranchCheck(I, isSignBit) && !I.isEquality()) { + if (Intersection.isSingleElement()) { + const APInt *API = Intersection.getSingleElement(); + return new ICmpInst(ICmpInst::ICMP_EQ, Op0, Builder->getInt(*API)); + } + ConstantRange Difference = DominatingCR.difference(CR); + if (Difference.isSingleElement()) { + const APInt *APD = Difference.getSingleElement(); + return new ICmpInst(ICmpInst::ICMP_NE, Op0, Builder->getInt(*APD)); + } + } + } } // See if we can fold the comparison based on range information we can get Index: test/Transforms/InstCombine/icmp.ll =================================================================== --- test/Transforms/InstCombine/icmp.ll +++ test/Transforms/InstCombine/icmp.ll @@ -1979,3 +1979,121 @@ ret i1 %cmp } +; CHECK-LABEL: @idom_sign_bit_check_edge_dominates +define void @idom_sign_bit_check_edge_dominates(i64 %a) { +entry: + %cmp = icmp slt i64 %a, 0 + br i1 %cmp, label %land.lhs.true, label %lor.rhs + +land.lhs.true: ; preds = %entry + br label %lor.end + +; CHECK-LABEL: lor.rhs: +; CHECK-NOT: icmp sgt i64 %a, 0 +; CHECK: icmp eq i64 %a, 0 +lor.rhs: ; preds = %entry + %cmp2 = icmp sgt i64 %a, 0 + br i1 %cmp2, label %land.rhs, label %lor.end + +land.rhs: ; preds = %lor.rhs + br label %lor.end + +lor.end: ; preds = %land.rhs, %lor.rhs, %land.lhs.true + ret void +} + +; CHECK-LABEL: @idom_sign_bit_check_edge_not_dominates +define void @idom_sign_bit_check_edge_not_dominates(i64 %a) { +entry: + %cmp = icmp slt i64 %a, 0 + br i1 %cmp, label %land.lhs.true, label %lor.rhs + +land.lhs.true: ; preds = %entry + br i1 undef, label %lor.end, label %lor.rhs + +; CHECK-LABEL: lor.rhs: +; CHECK: icmp sgt i64 %a, 0 +; CHECK-NOT: icmp eq i64 %a, 0 +lor.rhs: ; preds = %land.lhs.true, %entry + %cmp2 = icmp sgt i64 %a, 0 + br i1 %cmp2, label %land.rhs, label %lor.end + +land.rhs: ; preds = %lor.rhs + br label %lor.end + +lor.end: ; preds = %land.rhs, %lor.rhs, %land.lhs.true + ret void +} + +; CHECK-LABEL: @idom_sign_bit_check_edge_dominates_select +define void @idom_sign_bit_check_edge_dominates_select(i64 %a, i64 %b) { +entry: + %cmp = icmp slt i64 %a, 5 + br i1 %cmp, label %land.lhs.true, label %lor.rhs + +land.lhs.true: ; preds = %entry + br label %lor.end + +; CHECK-LABEL: lor.rhs: +; CHECK-NOT: [[B:%.*]] = icmp sgt i64 %a, 5 +; CHECK: [[C:%.*]] = icmp eq i64 %a, %b +; CHECK-NOT: [[D:%.*]] = select i1 [[B]], i64 %a, i64 5 +; CHECK-NOT: icmp ne i64 [[D]], %b +; CHECK-NEXT: br i1 [[C]], label %lor.end, label %land.rhs +lor.rhs: ; preds = %entry + %cmp2 = icmp sgt i64 %a, 5 + %select = select i1 %cmp2, i64 %a, i64 5 + %cmp3 = icmp ne i64 %select, %b + br i1 %cmp3, label %land.rhs, label %lor.end + +land.rhs: ; preds = %lor.rhs + br label %lor.end + +lor.end: ; preds = %land.rhs, %lor.rhs, %land.lhs.true + ret void +} + +; CHECK-LABEL: @idom_zbranch +define void @idom_zbranch(i64 %a) { +entry: + %cmp = icmp sgt i64 %a, 0 + br i1 %cmp, label %lor.end, label %lor.rhs + +; CHECK-LABEL: lor.rhs: +; CHECK: icmp slt i64 %a, 0 +; CHECK-NOT: icmp eq i64 %a, 0 +lor.rhs: ; preds = %entry + %cmp2 = icmp slt i64 %a, 0 + br i1 %cmp2, label %land.rhs, label %lor.end + +land.rhs: ; preds = %lor.rhs + br label %lor.end + +lor.end: ; preds = %land.rhs, %lor.rhs + ret void +} + +; CHECK-LABEL: @idom_not_zbranch +define void @idom_not_zbranch(i32 %a, i32 %b) { +entry: + %cmp = icmp sgt i32 %a, 0 + br i1 %cmp, label %return, label %if.end + +; CHECK-LABEL: if.end: +; CHECK-NOT: [[B:%.*]] = icmp slt i32 %a, 0 +; CHECK: [[C:%.*]] = icmp eq i32 %a, %b +; CHECK-NOT: [[D:%.*]] = select i1 [[B]], i32 %a, i32 0 +; CHECK-NOT: icmp ne i32 [[D]], %b +; CHECK-NEXT: br i1 [[C]], label %return, label %if.then3 +if.end: ; preds = %entry + %cmp1 = icmp slt i32 %a, 0 + %a. = select i1 %cmp1, i32 %a, i32 0 + %cmp2 = icmp ne i32 %a., %b + br i1 %cmp2, label %if.then3, label %return + +if.then3: ; preds = %if.end + br label %return + +return: ; preds = %if.end, %entry, %if.then3 + ret void +}