Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp =================================================================== --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -341,6 +341,10 @@ uint64_t Address, const void *Decoder); +static DecodeStatus DecodeFMemMMR6(MCInst &Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); @@ -353,6 +357,10 @@ uint64_t Address, const void *Decoder); +static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -1588,6 +1596,22 @@ return MCDisassembler::Success; } +static DecodeStatus DecodeFMemMMR6(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + int Offset = SignExtend32<16>(Insn & 0xffff); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::createReg(Reg)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -1641,6 +1665,23 @@ return MCDisassembler::Success; } + +static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + int Offset = SignExtend32<11>(Insn & 0x07ff); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::createReg(Reg)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h @@ -183,6 +183,9 @@ unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + unsigned getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -756,6 +756,19 @@ } unsigned MipsMCCodeEmitter:: +getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + // Base register is encoded in bits 20-16, offset is encoded in bits 10-0. + assert(MI.getOperand(OpNo).isReg()); + unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, + STI) << 16; + unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); + + return (OffBits & 0x07FF) | RegBits; +} + +unsigned MipsMCCodeEmitter:: getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { Index: lib/Target/Mips/MicroMips32r6InstrFormats.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrFormats.td +++ lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -916,3 +916,35 @@ let Inst{15-6} = funct; let Inst{5-0} = 0b111100; } + +class LDWC1_SDWC1_FM_MMR6 funct> + : MMR6Arch { + bits<5> ft; + bits<21> addr; + bits<5> base = addr{20-16}; + bits<16> offset = addr{15-0}; + + bits<32> Inst; + + let Inst{31-26} = funct; + let Inst{25-21} = ft; + let Inst{20-16} = base; + let Inst{15-0} = offset; +} + +class POOL32B_LDWC2_SDWC2_FM_MMR6 funct> + : MMR6Arch, MipsR6Inst { + bits<5> rt; + bits<21> addr; + bits<5> base = addr{20-16}; + bits<11> offset = addr{10-0}; + + bits<32> Inst; + + let Inst{31-26} = 0b001000; + let Inst{25-21} = rt; + let Inst{20-16} = base; + let Inst{15-12} = funct; + let Inst{11} = 0; + let Inst{10-0} = offset; +} Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrInfo.td +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -63,6 +63,7 @@ class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>; class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>; class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>; +class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>; class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>; class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>; class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>; @@ -88,6 +89,8 @@ class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>; class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>; class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>; +class SDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"sdc1", 0b101110>; +class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>; class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>; class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>; class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>; @@ -97,6 +100,7 @@ class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>; class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>; class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>; +class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>; class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>; class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>; class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>; @@ -647,6 +651,53 @@ II_MFHC1>, HARDFLOAT, FGR_64; class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd>; +class COP2LD_MMR6_DESC_BASE< + string opstr, RegisterOperand COPOpnd, InstrItinClass Itin, + SDPatternOperator OpNode = null_frag> { + dag OutOperandList = (outs COPOpnd:$rt); + dag InOperandList = (ins mem_mm_11:$addr); + string AsmString = !strconcat(opstr, "\t$rt, $addr"); + list Pattern = [(set COPOpnd:$rt, (OpNode addrDefault:$addr))]; + Format f = FrmFI; + InstrItinClass Itinerary = Itin; + string BaseOpcode = opstr; + bit mayLoad = 1; + string DecoderMethod = "DecodeFMemCop2MMR6"; +} +class LWC2_MMR6_DESC : COP2LD_MMR6_DESC_BASE<"lwc2", COP2Opnd, NoItinerary, + load>; + +class SDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 { + dag InOperandList = (ins FGR64Opnd:$ft, mem_mm_16:$addr); + dag OutOperandList = (outs); + string AsmString = !strconcat("sdc1", "\t$ft, $addr"); + list Pattern = [(store FGR64Opnd:$ft, addrDefault:$addr)]; + Format f = FrmFI; + InstrItinClass Itinerary = II_SWC1; + string BaseOpcode = "sdc1"; + bit mayStore = 1; + let DecoderMethod = "DecodeFMemMMR6"; +} + +class COP2ST_MMR6_DESC_BASE< + string opstr, RegisterOperand COPOpnd, InstrItinClass Itin, + SDPatternOperator OpNode = null_frag> { + dag OutOperandList = (outs); + dag InOperandList = (ins COPOpnd:$rt, mem_mm_11:$addr); + string AsmString = !strconcat(opstr, "\t$rt, $addr"); + list Pattern = [(OpNode COPOpnd:$rt, addrDefault:$addr)]; + Format f = FrmFI; + InstrItinClass Itinerary = Itin; + string BaseOpcode = opstr; + bit mayStore = 1; + string DecoderMethod = "DecodeFMemCop2MMR6"; +} + +class SDC2_MMR6_DESC : COP2ST_MMR6_DESC_BASE<"sdc2", COP2Opnd, NoItinerary, + store>; +class SWC2_MMR6_DESC : COP2ST_MMR6_DESC_BASE<"swc2", COP2Opnd, NoItinerary, + store>; + /// Floating Point Instructions class FARITH_MMR6_DESC_BASE, ADDS_FM_MM<1, 0x70>; -def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM_MM<0x27>; -def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, - LW_FM_MM<0x26>; def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM_MM<0x2f>; -def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, - LW_FM_MM<0x2e>; def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM_MM<0x48>, INSN_MIPS4_32R2_NOT_32R6_64R6; def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, @@ -147,4 +142,12 @@ MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32; def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32; + let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR6" in { + def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, + LW_FM_MM<0x27>; + def SDC1_MM : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, + LW_FM_MM<0x2e>, FGR_32; + def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, + LW_FM_MM<0x26>; + } } Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -96,6 +96,14 @@ let OperandType = "OPERAND_MEMORY"; } +def mem_mm_11 : Operand { + let PrintMethod = "printMemOperand"; + let MIOperandInfo = (ops GPR32, simm11); + let EncoderMethod = "getMemEncodingMMImm11"; + let ParserMatchClass = MipsMemSimm11AsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + def mem_mm_12 : Operand { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPR32, simm12); Index: lib/Target/Mips/Mips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/Mips32r6InstrInfo.td +++ lib/Target/Mips/Mips32r6InstrInfo.td @@ -756,7 +756,9 @@ def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6; def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6; def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6; -def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6; +let AdditionalPredicates = [NotInMicroMips] in { + def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6; +} def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6; let AdditionalPredicates = [NotInMicroMips] in { @@ -789,9 +791,9 @@ } def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; let AdditionalPredicates = [NotInMicroMips] in { -def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; + def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; + def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; } -def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; let AdditionalPredicates = [NotInMicroMips] in { def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, HARDFLOAT; @@ -803,8 +805,8 @@ def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6, HARDFLOAT; def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT; def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT; + def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6; } -def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6; //===----------------------------------------------------------------------===// // Index: lib/Target/Mips/MipsInstrFPU.td =================================================================== --- lib/Target/Mips/MipsInstrFPU.td +++ lib/Target/Mips/MipsInstrFPU.td @@ -400,20 +400,26 @@ } /// Floating Point Memory Instructions -def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>; -def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>; +let AdditionalPredicates = [NotInMicroMips] in { + def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>; + def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>; +} let DecoderNamespace = "Mips64" in { def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2, FGR_64; +} +let DecoderNamespace = "Mips64", AdditionalPredicates = [NotInMicroMips] in { def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2, FGR_64; } def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2, FGR_32; -def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, - ISA_MIPS2, FGR_32; +let AdditionalPredicates = [NotInMicroMips] in { + def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, + ISA_MIPS2, FGR_32; +} // Indexed loads and stores. // Base register + offset register addressing mode (indicated by "x" in the Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1745,13 +1745,13 @@ let AdditionalPredicates = [NotInMicroMips] in { // COP2 Memory Instructions -def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>, +def LWC2 : StdMMR6Rel, LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>, ISA_MIPS1_NOT_32R6_64R6; def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>, ISA_MIPS1_NOT_32R6_64R6; def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>, ISA_MIPS2_NOT_32R6_64R6; -def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>, +def SDC2 : StdMMR6Rel, SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>, ISA_MIPS2_NOT_32R6_64R6; // COP3 Memory Instructions Index: test/MC/Disassembler/Mips/micromips32r3/valid-el.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r3/valid-el.txt +++ test/MC/Disassembler/Mips/micromips32r3/valid-el.txt @@ -189,3 +189,6 @@ 0x04 0x63 0x02 0x64 # CHECK: lwle $24, 2($4) 0x44 0x60 0x08 0x6c # CHECK: lle $2, 8($4) 0x44 0x60 0x08 0xac # CHECK: sce $2, 8($4) +0x46 0x9c 0x04 0x00 # CHECK: lwc1 $f2, 4($6) +0x46 0xb8 0x04 0x00 # CHECK: sdc1 $f2, 4($6) +0x46 0x98 0x04 0x00 # CHECK: swc1 $f2, 4($6) Index: test/MC/Disassembler/Mips/micromips32r3/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r3/valid.txt +++ test/MC/Disassembler/Mips/micromips32r3/valid.txt @@ -189,3 +189,6 @@ 0x63 0x04 0x64 0x02 # CHECK: lwle $24, 2($4) 0x60 0x44 0x6c 0x08 # CHECK: lle $2, 8($4) 0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4) +0x9c 0x46 0x00 0x04 # CHECK: lwc1 $f2, 4($6) +0xb8 0x46 0x00 0x04 # CHECK: sdc1 $f2, 4($6) +0x98 0x46 0x00 0x04 # CHECK: swc1 $f2, 4($6) Index: test/MC/Disassembler/Mips/micromips32r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -276,3 +276,10 @@ 0x00 0x22 0x08 0xf4 # CHECK: mfhc0 $1, $2, 1 0x54 0x06 0x30 0x3b # CHECK: mfhc1 $zero, $f6 0x02 0xf0 0x8d 0x3c # CHECK: mfhc2 $23, $16 +0x9c 0x45 0x00 0x20 # CHECK: lwc1 $f2, 32($5) +0x20 0x24 0x00 0x10 # CHECK: lwc2 $1, 16($4) +0xb8 0xea 0x00 0x40 # CHECK: sdc1 $f7, 64($10) +0xb9 0x0a 0x00 0x40 # CHECK: sdc1 $f8, 64($10) +0x20 0x50 0xa0 0x08 # CHECK: sdc2 $2, 8($16) +0x98 0xcd 0x01 0x71 # CHECK: swc1 $f6, 369($13) +0x20 0xf1 0x83 0x09 # CHECK: swc2 $7, 777($17) Index: test/MC/Disassembler/Mips/micromips64r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -193,3 +193,10 @@ 0x59 0x21 0x08 0xfc # CHECK: dmfc0 $9, $1, 1 0x55 0x24 0x24 0x3b # CHECK: dmfc1 $9, $f4 0x01 0xd2 0x6d 0x3c # CHECK: dmfc2 $14, $18 +0x9c 0x45 0x00 0x20 # CHECK: lwc1 $f2, 32($5) +0x20 0x24 0x00 0x10 # CHECK: lwc2 $1, 16($4) +0xb8 0xea 0x00 0x40 # CHECK: sdc1 $f7, 64($10) +0xb9 0x0a 0x00 0x40 # CHECK: sdc1 $f8, 64($10) +0x20 0x50 0xa0 0x08 # CHECK: sdc2 $2, 8($16) +0x98 0xcd 0x01 0x71 # CHECK: swc1 $f6, 369($13) +0x20 0xf1 0x83 0x09 # CHECK: swc2 $7, 777($17) Index: test/MC/Mips/micromips32r6/valid.s =================================================================== --- test/MC/Mips/micromips32r6/valid.s +++ test/MC/Mips/micromips32r6/valid.s @@ -275,3 +275,10 @@ mfhc0 $1, $2, 1 # CHECK: mfhc0 $1, $2, 1 # encoding: [0x00,0x22,0x08,0xf4] mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b] mfhc2 $23, $16 # CHECK: mfhc2 $23, $16 # encoding: [0x02,0xf0,0x8d,0x3c] + lwc1 $f2, 32($5) # CHECK: lwc1 $f2, 32($5) # encoding: [0x9c,0x45,0x00,0x20] + lwc2 $1, 16($4) # CHECK: lwc2 $1, 16($4) # encoding: [0x20,0x24,0x00,0x10] + sdc1 $f7, 64($10) # CHECK: sdc1 $f7, 64($10) # encoding: [0xb8,0xea,0x00,0x40] + sdc1 $f8, 64($10) # CHECK: sdc1 $f8, 64($10) # encoding: [0xb9,0x0a,0x00,0x40] + sdc2 $2, 8($16) # CHECK: sdc2 $2, 8($16) # encoding: [0x20,0x50,0xa0,0x08] + swc1 $f6, 369($13) # CHECK: swc1 $f6, 369($13) # encoding: [0x98,0xcd,0x01,0x71] + swc2 $7, 777($17) # CHECK: swc2 $7, 777($17) # encoding: [0x20,0xf1,0x83,0x09]