Index: lib/Target/Mips/MicroMips32r6InstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -965,9 +965,9 @@
 
 class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
   dag OutOperandList = (outs);
-  dag InOperandList = (ins i32imm:$stype);
+  dag InOperandList = (ins uimm5:$stype);
   string AsmString = !strconcat("sync", "\t$stype");
-  list<dag> Pattern = [(MipsSync imm:$stype)];
+  list<dag> Pattern = [(MipsSync immZExt5:$stype)];
   InstrItinClass Itinerary = NoItinerary;
   bit HasSideEffects = 1;
 }
Index: lib/Target/Mips/Mips16InstrInfo.td
===================================================================
--- lib/Target/Mips/Mips16InstrInfo.td
+++ lib/Target/Mips/Mips16InstrInfo.td
@@ -31,6 +31,8 @@
   let EncoderMethod = "getMemEncoding";
 }
 
+def pcrel16 : Operand<i32>;
+
 //
 // I-type instruction format
 //
Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -840,10 +840,6 @@
   let ParserMatchClass = ConstantUImm7Sub1AsmOperandClass;
 }
 
-
-def pcrel16      : Operand<i32> {
-}
-
 def MipsMemAsmOperand : AsmOperandClass {
   let Name = "Mem";
   let ParserMethod = "parseMemOperand";
@@ -1381,8 +1377,8 @@
 // Sync
 let hasSideEffects = 1 in
 class SYNC_FT<string opstr> :
-  InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
-         NoItinerary, FrmOther, opstr>;
+  InstSE<(outs), (ins uimm5:$stype), "sync $stype",
+         [(MipsSync immZExt5:$stype)], NoItinerary, FrmOther, opstr>;
 
 class SYNCI_FT<string opstr> :
   InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
@@ -1765,7 +1761,8 @@
 }
 }
 
-def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
+def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM,
+           ISA_MIPS32;
 def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
 
 let AdditionalPredicates = [NotInMicroMips] in {
Index: test/MC/Mips/micromips/invalid.s
===================================================================
--- test/MC/Mips/micromips/invalid.s
+++ test/MC/Mips/micromips/invalid.s
@@ -48,5 +48,7 @@
   sra $2, $3, 32      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   srl $2, $3, -1      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   srl $2, $3, 32      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sync -1             # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
+  sync 32             # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
   swe $2, -513($gp)   # CHECK: :[[@LINE]]:11: error: expected memory with $gp and 9-bit signed offset
   swe $2, 512($gp)    # CHECK: :[[@LINE]]:11: error: expected memory with $gp and 9-bit signed offset
Index: test/MC/Mips/micromips32r6/invalid.s
===================================================================
--- test/MC/Mips/micromips32r6/invalid.s
+++ test/MC/Mips/micromips32r6/invalid.s
@@ -99,6 +99,8 @@
   sh16  $4, 68($17)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   sh16  $16, 8($17)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sh16  $7, 8($9)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sync -1                  # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
+  sync 32                  # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
   sw16  $9, 4($17)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sw16  $4, 64($17)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   sw16  $16, 4($17)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Index: test/MC/Mips/mips32r2/invalid.s
===================================================================
--- test/MC/Mips/mips32r2/invalid.s
+++ test/MC/Mips/mips32r2/invalid.s
@@ -36,6 +36,8 @@
         srl $2, $3, 32       # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
         sra $2, $3, -1       # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
         sra $2, $3, 32       # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
+        sync -1              # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
+        sync 32              # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         syscall -1           # CHECK: :[[@LINE]]:17: error: expected 20-bit unsigned immediate
         syscall 1048576      # CHECK: :[[@LINE]]:17: error: expected 20-bit unsigned immediate
         rotr $2, $3, -1      # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
Index: test/MC/Mips/mips32r6/invalid.s
===================================================================
--- test/MC/Mips/mips32r6/invalid.s
+++ test/MC/Mips/mips32r6/invalid.s
@@ -49,3 +49,5 @@
         mfc2  $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
         sdc2 $20, -1025($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         sdc2 $20, 1024($s2)  # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
+        sync -1              # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
+        sync 32              # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate