Index: lib/Target/SystemZ/README.txt
===================================================================
--- lib/Target/SystemZ/README.txt
+++ lib/Target/SystemZ/README.txt
@@ -80,7 +80,8 @@
 --
 
 We don't use the halfword forms of LOAD REVERSED and STORE REVERSED
-(LRVH and STRVH).
+(LRVH and STRVH). However, the inline assembly parser does support
+these opcodes.
 
 --
 
Index: lib/Target/SystemZ/SystemZInstrInfo.td
===================================================================
--- lib/Target/SystemZ/SystemZInstrInfo.td
+++ lib/Target/SystemZ/SystemZInstrInfo.td
@@ -570,10 +570,13 @@
 
 // Byte-swapping loads.  Unlike normal loads, these instructions are
 // allowed to access storage more than once.
+def LRVH : UnaryRXY<"lrvh", 0xE31F, loadu<bswap, nonvolatile_load>, GR32, 2>;
 def LRV  : UnaryRXY<"lrv",  0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>;
 def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>;
 
 // Likewise byte-swapping stores.
+def STRVH : StoreRXY<"strvh", 0xE33F, storeu<bswap, nonvolatile_store>,
+                     GR32, 2>;
 def STRV  : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>;
 def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>,
                      GR64, 8>;