Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -3654,7 +3654,7 @@ // jalr.hb must be different. unsigned Opcode = Inst.getOpcode(); - if (Opcode == Mips::JALR_HB && + if ((Opcode == Mips::JALR_HB || Opcode == Mips::JALRC_HB_MMR6) && (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())) return Match_RequiresDifferentSrcAndDst; Index: lib/Target/Mips/MicroMips32r6InstrFormats.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrFormats.td +++ lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -473,6 +473,20 @@ let Inst{15-0} = offset; } +class POOL32A_JALRC_FM_MMR6 funct> + : MipsR6Inst, MMR6Arch { + bits<5> rt; + bits<5> rs; + + bits<32> Inst; + + let Inst{31-26} = 0; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-6} = funct; + let Inst{5-0} = 0b111100; +} + class POOL32A_ERET_FM_MMR6 funct> : MMR6Arch { bits<32> Inst; @@ -916,3 +930,16 @@ let Inst{15-6} = funct; let Inst{5-0} = 0b111100; } + +class POOL32A_DVPEVP_FM_MMR6 funct> + : MMR6Arch, MipsR6Inst { + bits<5> rs; + + bits<32> Inst; + + let Inst{31-26} = 0b000000; + let Inst{25-21} = 0b00000; + let Inst{20-16} = rs; + let Inst{15-6} = funct; + let Inst{5-0} = 0b111100; +} Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrInfo.td +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -140,6 +140,7 @@ class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>; class LW_MMR6_ENC : LOAD_WORD_FM_MMR6; class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6; +class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>; class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>; class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>; class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>; @@ -176,6 +177,8 @@ class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>; class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>; class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>; +class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>; +class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>; class CMP_CBR_RT_Z_MMR6_DESC_BASE @@ -1005,6 +1008,18 @@ let mayStore = 1; } +class JALRC_HB_MMR6_DESC { + dag OutOperandList = (outs GPR32Opnd:$rt); + dag InOperandList = (ins GPR32Opnd:$rs); + string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs"); + list Pattern = []; + InstrItinClass Itinerary = NoItinerary; + Format Form = FrmJ; + bit isIndirectBranch = 1; + bit hasDelaySlot = 0; + bit isCTI = 1; +} + class TLBINV_MMR6_DESC_BASE { dag OutOperandList = (outs); dag InOperandList = (ins); @@ -1015,6 +1030,16 @@ class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv">; class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf">; +class DVPEVP_MMR6_DESC_BASE { + dag OutOperandList = (outs); + dag InOperandList = (ins GPR32Opnd:$rs); + string AsmString = !strconcat(opstr, "\t$rs"); + list Pattern = []; +} + +class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp">; +class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp">; + //===----------------------------------------------------------------------===// // // Instruction Definitions @@ -1275,6 +1300,8 @@ ISA_MICROMIPS32R6; def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC, ISA_MICROMIPS32R6; +def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC, + ISA_MICROMIPS32R6; def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC, ISA_MICROMIPS32R6; def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6; @@ -1307,6 +1334,8 @@ ISA_MICROMIPS32R6; def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC, ISA_MICROMIPS32R6; +def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6; +def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6; } //===----------------------------------------------------------------------===// @@ -1333,6 +1362,10 @@ def : MipsInstAlias<"mthc0 $rt, $rs", (MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>, ISA_MICROMIPS32R6; +def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6; +def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6; //===----------------------------------------------------------------------===// // Index: test/MC/Disassembler/Mips/micromips32r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -268,3 +268,9 @@ 0x01 0x2a 0x0a 0xf4 # CHECK: mthc0 $9, $10, 1 0x55 0x6c 0x38 0x3b # CHECK: mthc1 $11, $f12 0x01 0xae 0x9d 0x3c # CHECK: mthc2 $13, $14 +0x03 0xe4 0x1f 0x3c # CHECK: jalrc.hb $4 +0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5 +0x00 0x00 0x19 0x7c # CHECK: dvp +0x00 0x04 0x19 0x7c # CHECK: dvp $4 +0x00 0x00 0x39 0x7c # CHECK: evp +0x00 0x04 0x39 0x7c # CHECK: evp $4 Index: test/MC/Disassembler/Mips/micromips64r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -189,3 +189,9 @@ 0x5a 0x32 0x2a 0xfc # CHECK: dmtc0 $17, $18, 5 0x56 0x74 0x2c 0x3b # CHECK: dmtc1 $19, $f20 0x02 0xb6 0x7d 0x3c # CHECK: dmtc2 $21, $22 +0x03 0xe4 0x1f 0x3c # CHECK: jalrc.hb $4 +0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5 +0x00 0x00 0x19 0x7c # CHECK: dvp +0x00 0x04 0x19 0x7c # CHECK: dvp $4 +0x00 0x00 0x39 0x7c # CHECK: evp +0x00 0x04 0x39 0x7c # CHECK: evp $4 Index: test/MC/Mips/micromips32r6/invalid.s =================================================================== --- test/MC/Mips/micromips32r6/invalid.s +++ test/MC/Mips/micromips32r6/invalid.s @@ -114,3 +114,5 @@ mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + jalrc.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + jalrc.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different Index: test/MC/Mips/micromips32r6/valid.s =================================================================== --- test/MC/Mips/micromips32r6/valid.s +++ test/MC/Mips/micromips32r6/valid.s @@ -267,3 +267,9 @@ mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4] mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b] mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c] + jalrc.hb $4 # CHECK: jalrc.hb $4 # encoding: [0x03,0xe4,0x1f,0x3c] + jalrc.hb $4, $5 # CHECK: jalrc.hb $4, $5 # encoding: [0x00,0x85,0x1f,0x3c] + dvp # CHECK: dvp $zero # encoding: [0x00,0x00,0x19,0x7c] + dvp $4 # CHECK: dvp $4 # encoding: [0x00,0x04,0x19,0x7c] + evp # CHECK: evp $zero # encoding: [0x00,0x00,0x39,0x7c] + evp $4 # CHECK: evp $4 # encoding: [0x00,0x04,0x39,0x7c] Index: test/MC/Mips/micromips64r6/invalid.s =================================================================== --- test/MC/Mips/micromips64r6/invalid.s +++ test/MC/Mips/micromips64r6/invalid.s @@ -144,3 +144,5 @@ mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate + jalrc.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + jalrc.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different Index: test/MC/Mips/micromips64r6/valid.s =================================================================== --- test/MC/Mips/micromips64r6/valid.s +++ test/MC/Mips/micromips64r6/valid.s @@ -171,5 +171,11 @@ dmtc0 $17, $18, 5 # CHECK: dmtc0 $17, $18, 5 # encoding: [0x5a,0x32,0x2a,0xfc] dmtc1 $19, $f20 # CHECK: dmtc1 $19, $f20 # encoding: [0x56,0x74,0x2c,0x3b] dmtc2 $21, $22 # CHECK: dmtc2 $21, $22 # encoding: [0x02,0xb6,0x7d,0x3c] + jalrc.hb $4 # CHECK: jalrc.hb $4 # encoding: [0x03,0xe4,0x1f,0x3c] + jalrc.hb $4, $5 # CHECK: jalrc.hb $4, $5 # encoding: [0x00,0x85,0x1f,0x3c] + dvp # CHECK: dvp $zero # encoding: [0x00,0x00,0x19,0x7c] + dvp $4 # CHECK: dvp $4 # encoding: [0x00,0x04,0x19,0x7c] + evp # CHECK: evp $zero # encoding: [0x00,0x00,0x39,0x7c] + evp $4 # CHECK: evp $4 # encoding: [0x00,0x04,0x39,0x7c] 1: