Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp
===================================================================
--- lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -3786,6 +3786,9 @@
case Match_SImm10_0:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 10-bit signed immediate");
+ case Match_SImm11_0:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected 10-bit signed immediate");
case Match_UImm16:
case Match_UImm16_Relaxed:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
@@ -3814,6 +3817,9 @@
case Match_MemSImm10Lsl3:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected memory with 13-bit signed offset and multiple of 8");
+ case Match_MemSImm11:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected memory with 11-bit signed offset");
}
llvm_unreachable("Implement any new match types added!");
Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -479,11 +479,13 @@
let SuperClasses = [ConstantSImm10Lsl3AsmOperandClass];
let DiagnosticType = "SImm10_Lsl2";
}
+def ConstantSImm11AsmOperandClass
+ : ConstantSImmAsmOperandClass<11, [ConstantSImm10Lsl2AsmOperandClass]>;
def ConstantSImm10Lsl1AsmOperandClass : AsmOperandClass {
let Name = "SImm10Lsl1";
let RenderMethod = "addImmOperands";
let PredicateMethod = "isScaledSImm<10, 1>";
- let SuperClasses = [ConstantSImm10Lsl2AsmOperandClass];
+ let SuperClasses = [ConstantSImm11AsmOperandClass];
let DiagnosticType = "SImm10_Lsl1";
}
def ConstantUImm10AsmOperandClass
@@ -598,8 +600,6 @@
def imm64: Operand<i64>;
-def simm11 : Operand<i32>;
-
def simm16 : Operand<i32> {
let DecoderMethod= "DecodeSimm16";
}
@@ -763,7 +763,7 @@
}
// Signed operands
-foreach I = {4, 5, 6, 9, 10} in
+foreach I = {4, 5, 6, 9, 10, 11} in
def simm # I : Operand<i32> {
let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">";
let ParserMatchClass =
@@ -854,6 +854,7 @@
let RenderMethod = "addMemOperands";
let ParserMethod = "parseMemOperand";
let PredicateMethod = "isMemWithSimmOffset<11>";
+ let DiagnosticType = "MemSImm11";
}
def MipsMemSimm16AsmOperand : AsmOperandClass {
@@ -1150,7 +1151,8 @@
// COP2 Load/Store
class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
SDPatternOperator OpNode= null_frag> :
- InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
+ InstSE<(outs RC:$rt), (ins mem_simm16:$addr),
+ !strconcat(opstr, "\t$rt, $addr"),
[(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
let DecoderMethod = "DecodeFMem2";
let mayLoad = 1;
@@ -1158,7 +1160,8 @@
class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
SDPatternOperator OpNode= null_frag> :
- InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
+ InstSE<(outs), (ins RC:$rt, mem_simm16:$addr),
+ !strconcat(opstr, "\t$rt, $addr"),
[(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
let DecoderMethod = "DecodeFMem2";
let mayStore = 1;
Index: test/MC/Mips/mips1/invalid-mips2-wrong-error.s
===================================================================
--- test/MC/Mips/mips1/invalid-mips2-wrong-error.s
+++ test/MC/Mips/mips1/invalid-mips2-wrong-error.s
@@ -7,10 +7,12 @@
.set noat
ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
+ ldc2 $8,-1024($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
ldc3 $29,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
sc $t7,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
sdc1 $f31,30574($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
+ sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
sdc3 $12,5835($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Index: test/MC/Mips/mips1/invalid-mips3-wrong-error.s
===================================================================
--- test/MC/Mips/mips1/invalid-mips3-wrong-error.s
+++ test/MC/Mips/mips1/invalid-mips3-wrong-error.s
@@ -8,7 +8,8 @@
.set noat
ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
+ ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
@@ -18,6 +19,7 @@
scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
+ sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Index: test/MC/Mips/mips1/invalid-mips4-wrong-error.s
===================================================================
--- test/MC/Mips/mips1/invalid-mips4-wrong-error.s
+++ test/MC/Mips/mips1/invalid-mips4-wrong-error.s
@@ -10,7 +10,8 @@
bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
+ ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
@@ -20,6 +21,7 @@
scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
+ sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 11-bit signed offset
sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Index: test/MC/Mips/mips32r6/invalid.s
===================================================================
--- test/MC/Mips/mips32r6/invalid.s
+++ test/MC/Mips/mips32r6/invalid.s
@@ -12,8 +12,6 @@
align $4, $2, $3, 4 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
- ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
- sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
@@ -35,6 +33,8 @@
cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
+ ldc2 $20, -1025($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
+ ldc2 $20, 1024($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
@@ -47,3 +47,5 @@
mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mfc2 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mfc2 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
+ sdc2 $20, -1025($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
+ sdc2 $20, 1024($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled