Index: lib/Target/Mips/Mips64InstrInfo.td =================================================================== --- lib/Target/Mips/Mips64InstrInfo.td +++ lib/Target/Mips/Mips64InstrInfo.td @@ -305,8 +305,8 @@ // Cavium Octeon cnMIPS instructions let DecoderNamespace = "CnMips", - EncodingPredicates = [], // FIXME: The lack of HasStdEnc is probably a bug - AdditionalPredicates = [HasCnMips] in { + // FIXME: The lack of HasStdEnc is probably a bug + EncodingPredicates = [] in { class Count1s: InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), @@ -357,73 +357,80 @@ !strconcat(asmstr, "\t$rt, $imm16"), [], NoItinerary, FrmFR>; // Unsigned Byte Add -let Pattern = [(set GPR64Opnd:$rd, - (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>, - ADD_FM<0x1c, 0x28>; + ADD_FM<0x1c, 0x28>, ASE_CNMIPS { + let Pattern = [(set GPR64Opnd:$rd, + (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))]; +} // Branch on Bit Clear /+32 def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd, - uimm5_64_report_uimm6>, BBIT_FM<0x32>; + uimm5_64_report_uimm6>, BBIT_FM<0x32>, ASE_CNMIPS; def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64, - 0x100000000>, - BBIT_FM<0x36>; + 0x100000000>, BBIT_FM<0x36>, ASE_CNMIPS; // Branch on Bit Set /+32 def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd, - uimm5_64_report_uimm6>, BBIT_FM<0x3a>; + uimm5_64_report_uimm6>, BBIT_FM<0x3a>, ASE_CNMIPS; def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64, - 0x100000000>, BBIT_FM<0x3e>; + 0x100000000>, BBIT_FM<0x3e>, ASE_CNMIPS; // Multiply Doubleword to GPR -let Defs = [HI0, LO0, P0, P1, P2] in def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>, - ADD_FM<0x1c, 0x03>; + ADD_FM<0x1c, 0x03>, ASE_CNMIPS { + let Defs = [HI0, LO0, P0, P1, P2]; +} // Extract a signed bit field /+32 -def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>; -def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>; +def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>, ASE_CNMIPS; +def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>, ASE_CNMIPS; // Clear and insert a bit field /+32 -def CINS : ExtsCins<"cins">, EXTS_FM<0x32>; -def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>; +def CINS : ExtsCins<"cins">, EXTS_FM<0x32>, ASE_CNMIPS; +def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>, ASE_CNMIPS; // Move to multiplier/product register -def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>; -def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>; -def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>; -def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>; -def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>; -def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>; +def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>, + ASE_CNMIPS; +def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>, + ASE_CNMIPS; +def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>, + ASE_CNMIPS; +def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>, ASE_CNMIPS; +def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>, ASE_CNMIPS; +def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>, ASE_CNMIPS; // Count Ones in a Word/Doubleword -def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>; -def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>; +def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>, ASE_CNMIPS; +def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>, ASE_CNMIPS; // Set on equal/not equal -def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>; -def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>; -def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>; -def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>; +def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>, ASE_CNMIPS; +def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>, ASE_CNMIPS; +def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>, ASE_CNMIPS; +def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>, ASE_CNMIPS; // 192-bit x 64-bit Unsigned Multiply and Add -let Defs = [P0, P1, P2] in -def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>, - ADD_FM<0x1c, 0x11>; +def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x11>, + ASE_CNMIPS { + let Defs = [P0, P1, P2]; +} // 64-bit Unsigned Multiply and Add Move -let Defs = [MPL0, P0, P1, P2] in -def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>, - ADD_FM<0x1c, 0x10>; +def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x10>, + ASE_CNMIPS { + let Defs = [MPL0, P0, P1, P2]; +} // 64-bit Unsigned Multiply and Add -let Defs = [MPL1, MPL2, P0, P1, P2] in -def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>, - ADD_FM<0x1c, 0x0f>; +def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x0f>, + ASE_CNMIPS { + let Defs = [MPL1, MPL2, P0, P1, P2]; +} // Move between CPU and coprocessor registers -def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd>, MFC2OP_FM<0x12, 1>; -def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd>, MFC2OP_FM<0x12, 5>; +def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd>, MFC2OP_FM<0x12, 1>, ASE_CNMIPS; +def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd>, MFC2OP_FM<0x12, 5>, ASE_CNMIPS; } } @@ -537,16 +544,14 @@ } // Octeon bbit0/bbit1 MipsPattern -let Predicates = [HasMips64, HasCnMips] in { def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), - (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>; + (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), - (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>; + (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), - (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>; + (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), - (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>; -} + (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; // Atomic load patterns. def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>; @@ -629,12 +634,10 @@ def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>; def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>; -let Predicates = [HasMips64, HasCnMips] in { -def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>; -def : MipsInstAlias<"syncs", (SYNC 0x6), 0>; -def : MipsInstAlias<"syncw", (SYNC 0x4), 0>; -def : MipsInstAlias<"syncws", (SYNC 0x5), 0>; -} +def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>, ASE_MIPS64_CNMIPS; +def : MipsInstAlias<"syncs", (SYNC 0x6), 0>, ASE_MIPS64_CNMIPS; +def : MipsInstAlias<"syncw", (SYNC 0x4), 0>, ASE_MIPS64_CNMIPS; +def : MipsInstAlias<"syncws", (SYNC 0x5), 0>, ASE_MIPS64_CNMIPS; // cnMIPS Aliases. Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -315,6 +315,10 @@ list InsnPredicates = [HasCnMips]; } +class ASE_MIPS64_CNMIPS { + list InsnPredicates = [HasMips64, HasCnMips]; +} + class ASE_MSA { list InsnPredicates = [HasMSA]; }