Index: ../docs/ReleaseNotes.rst
===================================================================
--- ../docs/ReleaseNotes.rst
+++ ../docs/ReleaseNotes.rst
@@ -118,6 +118,8 @@
   not be completely surprising if there were a few lingering issues that
   early adopters might bump into.
 
+* New intrinsics ``llvm.masked.load and llvm.masked.store`` were introduced to
+  LLVM IR to allow selective memory access for vector data types.
 
 Changes to the ARM Backends
 ---------------------------
@@ -236,6 +238,13 @@
 Changes to the X86 Target
 -----------------------------
 
+* LLVM now supports the Intel CPU named Skylake with AVX-512 extensions through
+  ``-march=skylake-avx512``. The switch enables the following ISA extensions:
+  AVX-512F, AVX512VL, AVX-512CD, AVX-512BW, AVX-512DQ.
+
+* Enabled support of Intel MIC architecture processor Knights Landing (KNL)
+  through ``-march=knl`` with ISA extensions AVX-512F, AVX-512ER, AVX-512PF.
+
 * TLS is enabled for Cygwin as emutls.
 
 * Smaller code for materializing 32-bit 1 and -1 constants at ``-Os``.