Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1600,6 +1600,10 @@ case Mips::BLTZAL_MM: case Mips::BC1F_MM: case Mips::BC1T_MM: + case Mips::BC1EQZC_MMR6: + case Mips::BC1NEZC_MMR6: + case Mips::BC2EQZC_MMR6: + case Mips::BC2NEZC_MMR6: assert(MCID.getNumOperands() == 2 && "unexpected number of operands"); Offset = Inst.getOperand(1); if (!Offset.isImm()) Index: lib/Target/Mips/MicroMips32r6InstrFormats.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrFormats.td +++ lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -870,3 +870,29 @@ let Inst{15-6} = funct; let Inst{5-0} = 0b111100; } + +class POOL32I_BRANCH_COP1_FM_MMR6 funct> + : MMR6Arch, MipsR6Inst { + bits<5> ft; + bits<16> offset; + + bits<32> Inst; + + let Inst{31-26} = 0b010000; + let Inst{25-21} = funct; + let Inst{20-16} = ft; + let Inst{15-0} = offset; +} + +class POOL32I_BRANCH_COP2_FM_MMR6 funct> + : MMR6Arch, MipsR6Inst { + bits<5> ct; + bits<16> offset; + + bits<32> Inst; + + let Inst{31-26} = 0b010000; + let Inst{25-21} = funct; + let Inst{20-16} = ct; + let Inst{15-0} = offset; +} Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrInfo.td +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -170,6 +170,10 @@ class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>; class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>; class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>; +class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP1_FM_MMR6<"bc1eqzc", 0b01000>; +class BC1NEZC_MMR6_ENC : POOL32I_BRANCH_COP1_FM_MMR6<"bc1nezc", 0b01001>; +class BC2EQZC_MMR6_ENC : POOL32I_BRANCH_COP2_FM_MMR6<"bc2eqzc", 0b01010>; +class BC2NEZC_MMR6_ENC : POOL32I_BRANCH_COP2_FM_MMR6<"bc2nezc", 0b01011>; class CMP_CBR_RT_Z_MMR6_DESC_BASE @@ -936,6 +940,24 @@ class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv">; class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf">; +class BRANCH_COP1_MMR6_DESC_BASE : BRANCH_DESC_BASE, HARDFLOAT { + dag InOperandList = (ins FGR64Opnd:$ft, brtarget_mm:$offset); + dag OutOperandList = (outs); + string AsmString = !strconcat(opstr, "\t$ft, $offset"); +} + +class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">; +class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">; + +class BRANCH_COP2_MMR6_DESC_BASE : BRANCH_DESC_BASE { + dag InOperandList = (ins COP2Opnd:$ct, brtarget_mm:$offset); + dag OutOperandList = (outs); + string AsmString = !strconcat(opstr, "\t$ct, $offset"); +} + +class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc">; +class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc">; + //===----------------------------------------------------------------------===// // // Instruction Definitions @@ -1218,6 +1240,14 @@ ISA_MICROMIPS32R6; def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC, ISA_MICROMIPS32R6; +def BC1EQZC_MMR6 : R6MMR6Rel, BC1EQZC_MMR6_ENC, BC1EQZC_MMR6_DESC, + ISA_MICROMIPS32R6; +def BC1NEZC_MMR6 : R6MMR6Rel, BC1NEZC_MMR6_ENC, BC1NEZC_MMR6_DESC, + ISA_MICROMIPS32R6; +def BC2EQZC_MMR6 : R6MMR6Rel, BC2EQZC_MMR6_ENC, BC2EQZC_MMR6_DESC, + ISA_MICROMIPS32R6; +def BC2NEZC_MMR6 : R6MMR6Rel, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC, + ISA_MICROMIPS32R6; } //===----------------------------------------------------------------------===// Index: lib/Target/Mips/Mips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/Mips32r6InstrInfo.td +++ lib/Target/Mips/Mips32r6InstrInfo.td @@ -696,10 +696,12 @@ def AUIPC : R6MMR6Rel, AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6; def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6; def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6; -def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT; -def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT; -def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6; -def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6; +let AdditionalPredicates = [NotInMicroMips] in { + def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT; + def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT; + def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6; + def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6; +} def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6; def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6; def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6; Index: test/MC/Disassembler/Mips/micromips32r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -258,3 +258,11 @@ 0x00 0x0f 0x47 0x7c # CHECK: di $15 0x00 0x00 0x43 0x7c # CHECK: tlbinv 0x00 0x00 0x53 0x7c # CHECK: tlbinvf +0x41 0x00 0x00 0x02 # CHECK: bc1eqzc $f0, 4 +0x41 0x1f 0x00 0x02 # CHECK: bc1eqzc $f31, 4 +0x41 0x20 0x00 0x02 # CHECK: bc1nezc $f0, 4 +0x41 0x3f 0x00 0x02 # CHECK: bc1nezc $f31, 4 +0x41 0x40 0x00 0x04 # CHECK: bc2eqzc $0, 8 +0x41 0x5f 0x00 0x04 # CHECK: bc2eqzc $31, 8 +0x41 0x60 0x00 0x04 # CHECK: bc2nezc $0, 8 +0x41 0x7f 0x00 0x04 # CHECK: bc2nezc $31, 8 Index: test/MC/Disassembler/Mips/micromips64r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -174,3 +174,11 @@ 0x58 0x82 0x20 0x34 # CHECK: dinsu $4, $2, 32, 5 0x58 0x82 0x38 0xc4 # CHECK: dinsm $4, $2, 3, 5 0x58 0x82 0x38 0xcc # CHECK: dins $4, $2, 3, 5 +0x41 0x00 0x00 0x02 # CHECK: bc1eqzc $f0, 4 +0x41 0x1f 0x00 0x02 # CHECK: bc1eqzc $f31, 4 +0x41 0x20 0x00 0x02 # CHECK: bc1nezc $f0, 4 +0x41 0x3f 0x00 0x02 # CHECK: bc1nezc $f31, 4 +0x41 0x40 0x00 0x04 # CHECK: bc2eqzc $0, 8 +0x41 0x5f 0x00 0x04 # CHECK: bc2eqzc $31, 8 +0x41 0x60 0x00 0x04 # CHECK: bc2nezc $0, 8 +0x41 0x7f 0x00 0x04 # CHECK: bc2nezc $31, 8 Index: test/MC/Mips/micromips32r6/invalid.s =================================================================== --- test/MC/Mips/micromips32r6/invalid.s +++ test/MC/Mips/micromips32r6/invalid.s @@ -108,3 +108,19 @@ swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1eqzc $f0, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc1eqzc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc1nezc $f0, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range + bc1nezc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range + bc1eqzc $f0, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc1eqzc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc1nezc $f0, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range + bc1nezc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range + bc2eqzc $0, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc2eqzc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc2nezc $0, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range + bc2nezc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range + bc2eqzc $0, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc2eqzc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc2nezc $0, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range + bc2nezc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range Index: test/MC/Mips/micromips32r6/valid.s =================================================================== --- test/MC/Mips/micromips32r6/valid.s +++ test/MC/Mips/micromips32r6/valid.s @@ -252,3 +252,11 @@ deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c] tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c] tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c] + bc1eqzc $f0, 4 # CHECK: bc1eqzc $f0, 4 # encoding: [0x41,0x00,0x00,0x02] + bc1eqzc $f31, 4 # CHECK: bc1eqzc $f31, 4 # encoding: [0x41,0x1f,0x00,0x02] + bc1nezc $f0, 4 # CHECK: bc1nezc $f0, 4 # encoding: [0x41,0x20,0x00,0x02] + bc1nezc $f31, 4 # CHECK: bc1nezc $f31, 4 # encoding: [0x41,0x3f,0x00,0x02] + bc2eqzc $0, 8 # CHECK: bc2eqzc $0, 8 # encoding: [0x41,0x40,0x00,0x04] + bc2eqzc $31, 8 # CHECK: bc2eqzc $31, 8 # encoding: [0x41,0x5f,0x00,0x04] + bc2nezc $0, 8 # CHECK: bc2nezc $0, 8 # encoding: [0x41,0x60,0x00,0x04] + bc2nezc $31, 8 # CHECK: bc2nezc $31, 8 # encoding: [0x41,0x7f,0x00,0x04] Index: test/MC/Mips/micromips64r6/invalid.s =================================================================== --- test/MC/Mips/micromips64r6/invalid.s +++ test/MC/Mips/micromips64r6/invalid.s @@ -136,3 +136,19 @@ swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1eqzc $f0, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc1eqzc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc1nezc $f0, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range + bc1nezc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range + bc1eqzc $f0, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc1eqzc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc1nezc $f0, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range + bc1nezc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range + bc2eqzc $0, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc2eqzc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc2nezc $0, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range + bc2nezc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range + bc2eqzc $0, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc2eqzc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + bc2nezc $0, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range + bc2nezc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range Index: test/MC/Mips/micromips64r6/valid.s =================================================================== --- test/MC/Mips/micromips64r6/valid.s +++ test/MC/Mips/micromips64r6/valid.s @@ -159,4 +159,12 @@ dinsu $4, $2, 32, 5 # CHECK: dinsu $4, $2, 32, 5 # encoding: [0x58,0x82,0x20,0x34] dinsm $4, $2, 3, 5 # CHECK: dinsm $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xc4] dins $4, $2, 3, 5 # CHECK: dins $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xcc] + bc1eqzc $f0, 4 # CHECK: bc1eqzc $f0, 4 # encoding: [0x41,0x00,0x00,0x02] + bc1eqzc $f31, 4 # CHECK: bc1eqzc $f31, 4 # encoding: [0x41,0x1f,0x00,0x02] + bc1nezc $f0, 4 # CHECK: bc1nezc $f0, 4 # encoding: [0x41,0x20,0x00,0x02] + bc1nezc $f31, 4 # CHECK: bc1nezc $f31, 4 # encoding: [0x41,0x3f,0x00,0x02] + bc2eqzc $0, 8 # CHECK: bc2eqzc $0, 8 # encoding: [0x41,0x40,0x00,0x04] + bc2eqzc $31, 8 # CHECK: bc2eqzc $31, 8 # encoding: [0x41,0x5f,0x00,0x04] + bc2nezc $0, 8 # CHECK: bc2nezc $0, 8 # encoding: [0x41,0x60,0x00,0x04] + bc2nezc $31, 8 # CHECK: bc2nezc $31, 8 # encoding: [0x41,0x7f,0x00,0x04] 1: