Index: lib/Target/PowerPC/PPC.td
===================================================================
--- lib/Target/PowerPC/PPC.td
+++ lib/Target/PowerPC/PPC.td
@@ -134,6 +134,12 @@
   SubtargetFeature<"direct-move", "HasDirectMove", "true",
                    "Enable Power8 direct move instructions",
                    [FeatureVSX]>;
+
+def FeatureP9DirectMove :
+  SubtargetFeature<"p9-direct-move", "HasP9DirectMove", "true",
+                   "Enable Power9 direct move instructions",
+                   [FeatureVSX, FeatureDirectMove]>;
+
 def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
                                              "HasPartwordAtomics", "true",
                                              "Enable l[bh]arx and st[bh]cx.">;
Index: lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- lib/Target/PowerPC/PPCInstrVSX.td
+++ lib/Target/PowerPC/PPCInstrVSX.td
@@ -1017,6 +1017,7 @@
 */
 def HasP8Vector : Predicate<"PPCSubTarget->hasP8Vector()">;
 def HasDirectMove : Predicate<"PPCSubTarget->hasDirectMove()">;
+def HasP9DirectMove : Predicate<"PPCSubTarget->hasP9DirectMove()">;
 let Predicates = [HasP8Vector] in {
 let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
   let isCommutable = 1 in {
@@ -1216,7 +1217,7 @@
 } // AddedComplexity = 400
 } // HasP8Vector
 
-let Predicates = [HasDirectMove, HasVSX] in {
+let Predicates = [HasDirectMove] in {
   // VSX direct move instructions
   def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
                               "mfvsrd $rA, $XT", IIC_VecGeneral,
@@ -1235,7 +1236,23 @@
   def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA),
                                "mtvsrwz $XT, $rA", IIC_VecGeneral,
                                [(set f64:$XT, (PPCmtvsrz i32:$rA))]>;
-} // HasDirectMove, HasVSX
+} // HasDirectMove
+
+let Predicates = [HasP9DirectMove] in {
+  // P9 direct move instructions
+  def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$rA),
+                              "mtvsrws $XT, $rA", IIC_VecGeneral,
+                              []>;
+
+  def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins gprc:$rA, gprc:$rB),
+                       "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral,
+                       []>, Requires<[In64BitMode]>;
+
+  def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs gprc:$rA), (ins vsrc:$XT),
+                              "mfvsrld $rA, $XT", IIC_VecGeneral,
+                              []>, Requires<[In64BitMode]>;
+
+} // HasP9DirectMove
 
 /*  Direct moves of various widths from GPR's into VSR's. Each move lines
     the value up into element 0 (both BE and LE). Namely, entities smaller than
Index: lib/Target/PowerPC/PPCSubtarget.h
===================================================================
--- lib/Target/PowerPC/PPCSubtarget.h
+++ lib/Target/PowerPC/PPCSubtarget.h
@@ -124,6 +124,7 @@
   bool HasHTM;
   bool HasFusion;
   bool HasFloat128;
+  bool HasP9DirectMove;
 
   /// When targeting QPX running a stock PPC64 Linux kernel where the stack
   /// alignment has not been changed, we need to keep the 16-byte alignment
@@ -265,6 +266,7 @@
   bool hasHTM() const { return HasHTM; }
   bool hasFusion() const { return HasFusion; }
   bool hasFloat128() const { return HasFloat128; }
+  bool hasP9DirectMove() const { return HasP9DirectMove; }
 
   const Triple &getTargetTriple() const { return TargetTriple; }
 
Index: lib/Target/PowerPC/PPCSubtarget.cpp
===================================================================
--- lib/Target/PowerPC/PPCSubtarget.cpp
+++ lib/Target/PowerPC/PPCSubtarget.cpp
@@ -105,6 +105,7 @@
   HasHTM = false;
   HasFusion = false;
   HasFloat128 = false;
+  HasP9DirectMove = false;
 }
 
 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
Index: test/MC/Disassembler/PowerPC/vsx.txt
===================================================================
--- test/MC/Disassembler/PowerPC/vsx.txt
+++ test/MC/Disassembler/PowerPC/vsx.txt
@@ -700,3 +700,12 @@
 
 # CHECK: stxvll 57, 12, 27
 0x7f 0x2c 0xdb 0x5b
+
+# CHECK: mtvsrws 34, 3
+0x7c 0x43 0x03 0x27
+
+# CHECK: mtvsrdd 34, 3, 12
+0x7c 0x43 0x63 0x67
+
+# CHECK: mfvsrld 3, 34
+0x7c 0x43 0x02 0x67
Index: test/MC/PowerPC/vsx.s
===================================================================
--- test/MC/PowerPC/vsx.s
+++ test/MC/PowerPC/vsx.s
@@ -758,3 +758,16 @@
 # CHECK-BE: stxvll 57, 12, 27                  # encoding: [0x7f,0x2c,0xdb,0x5b]
 # CHECK-LE: stxvll 57, 12, 27                  # encoding: [0x5b,0xdb,0x2c,0x7f]
             stxvll 57, 12, 27
+
+# P9 Direct Move Instructions
+# CHECK-BE: mtvsrws 34, 3                      # encoding: [0x7c,0x43,0x03,0x27]
+# CHECK-LE: mtvsrws 34, 3                      # encoding: [0x27,0x03,0x43,0x7c]
+            mtvsrws 34, 3
+
+# CHECK-BE: mtvsrdd 34, 3, 12                  # encoding: [0x7c,0x43,0x63,0x67]
+# CHECK-LE: mtvsrdd 34, 3, 12                  # encoding: [0x67,0x63,0x43,0x7c]
+            mtvsrdd 34, 3, 12
+
+# CHECK-BE: mfvsrld 3, 34                      # encoding: [0x7c,0x43,0x02,0x67]
+# CHECK-LE: mfvsrld 3, 34                      # encoding: [0x67,0x02,0x43,0x7c]
+            mfvsrld 3, 34