Index: include/llvm/CodeGen/Passes.h =================================================================== --- include/llvm/CodeGen/Passes.h +++ include/llvm/CodeGen/Passes.h @@ -392,9 +392,6 @@ /// load-linked/store-conditional loops. extern char &AtomicExpandID; - /// Lowers unsupported integer division. - extern char &IntegerDivisionID; - /// MachineLoopInfo - This pass is a loop analysis pass. extern char &MachineLoopInfoID; @@ -649,9 +646,6 @@ /// createJumpInstrTables - This pass creates jump-instruction tables. ModulePass *createJumpInstrTablesPass(); - /// Lower unsupported integer division - FunctionPass *createIntegerDivisionPass(const TargetMachine *TM); - /// createForwardControlFlowIntegrityPass - This pass adds control-flow /// integrity. ModulePass *createForwardControlFlowIntegrityPass(); Index: include/llvm/InitializePasses.h =================================================================== --- include/llvm/InitializePasses.h +++ include/llvm/InitializePasses.h @@ -149,7 +149,6 @@ void initializeInstructionCombiningPassPass(PassRegistry&); void initializeInstCountPass(PassRegistry&); void initializeInstNamerPass(PassRegistry&); -void initializeIntegerDivisionPass(PassRegistry&); void initializeInternalizePassPass(PassRegistry&); void initializeIntervalPartitionPass(PassRegistry&); void initializeJumpThreadingPass(PassRegistry&); Index: include/llvm/LinkAllPasses.h =================================================================== --- include/llvm/LinkAllPasses.h +++ include/llvm/LinkAllPasses.h @@ -145,8 +145,6 @@ (void) llvm::createStripDeadPrototypesPass(); (void) llvm::createTailCallEliminationPass(); (void) llvm::createJumpThreadingPass(); - /*AMDGPU64bit*/ - //(void) llvm::createIntegerDivisionPass(nullptr); (void) llvm::createUnifyFunctionExitNodesPass(); (void) llvm::createInstCountPass(); (void) llvm::createConstantHoistingPass(); Index: lib/Target/AMDGPU/AMDGPU.h =================================================================== --- lib/Target/AMDGPU/AMDGPU.h +++ lib/Target/AMDGPU/AMDGPU.h @@ -85,9 +85,6 @@ void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); extern char &AMDGPUAnnotateUniformValuesPassID; - -/*Modified Integer Division : IR Pass to perform 64bit integer division*/ - void initializeAMDGPUIntegerDivisionPass(PassRegistry&); extern char AMDGPU64bitDivisionID; Index: lib/Target/AMDGPU/AMDGPU64bitDivision.h =================================================================== --- lib/Target/AMDGPU/AMDGPU64bitDivision.h +++ lib/Target/AMDGPU/AMDGPU64bitDivision.h @@ -1,20 +1,3 @@ -#include "AMDGPUISelLowering.h" -#include "AMDGPU.h" -#include "AMDGPUDiagnosticInfoUnsupported.h" -#include "AMDGPUFrameLowering.h" -#include "AMDGPUIntrinsicInfo.h" -#include "AMDGPURegisterInfo.h" -#include "AMDGPUSubtarget.h" -#include "R600MachineFunctionInfo.h" -#include "SIMachineFunctionInfo.h" -#include "llvm/CodeGen/CallingConvLower.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" -#include "llvm/IR/DataLayout.h" -#include "llvm/IR/IRBuilder.h" - namespace llvm { class BinaryOperator; Index: lib/Target/AMDGPU/AMDGPUISelLowering.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -253,8 +253,6 @@ setOperationAction(ISD::BSWAP, VT, Expand); setOperationAction(ISD::CTTZ, VT, Expand); setOperationAction(ISD::CTLZ, VT, Expand); - - setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); } Index: lib/Target/AMDGPU/AMDGPUIntegerDivisionPass.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUIntegerDivisionPass.cpp +++ lib/Target/AMDGPU/AMDGPUIntegerDivisionPass.cpp @@ -1,4 +1,4 @@ -//===-- IntegerDivisionPass.cpp - Expand div/mod instructions -------------===// +//===-- AMDGPUIntegerDivisionPass.cpp - Expand div/mod instructions -------------===// // // The LLVM Compiler Infrastructure // @@ -7,11 +7,11 @@ // //===----------------------------------------------------------------------===// // -/// \file +/// \file: An IR level pass to perform 64bit Integer division //===----------------------------------------------------------------------===// /*Modified Integer Division Pass*/ - +#include "AMDGPU.h" #include "llvm/CodeGen/Passes.h" #include "llvm/IR/IRBuilder.h" #include "llvm/IR/InstVisitor.h" @@ -19,12 +19,11 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/Transforms/Utils/IntegerDivision.h" -#include "AMDGPU.h" #include "AMDGPU64bitDivision.h" using namespace llvm; -#define DEBUG_TYPE "AMDGPU integer-division" +#define DEBUG_TYPE "amdgpu-integer-division" namespace { @@ -34,7 +33,7 @@ const TargetMachine *TM; const TargetLowering *TLI; - int checkingVariable; + //int checkingVariable; bool shouldExpandDivRem(const BinaryOperator &I); @@ -64,14 +63,8 @@ } // End anonymous namespace char AMDGPUIntegerDivision::ID = 0; -//char &llvm::IntegerDivisionID = AMDGPUIntegerDivision::ID; INITIALIZE_TM_PASS(AMDGPUIntegerDivision, DEBUG_TYPE,"Expand integer division", false, false); - char &llvm::AMDGPUIntegerDivisionID = AMDGPUIntegerDivision::ID; -/*INITIALIZE_PASS_BEGIN(AMDGPUIntegerDivision, DEBUG_TYPE, - "Add AMDGPU function attributes", false, false) -INITIALIZE_PASS_END(AMDGPUIntegerDivision, DEBUG_TYPE, - "Add AMDGPU function attributes", false, false)*/ bool AMDGPUIntegerDivision::doInitialization(Module &M) { return false; @@ -101,9 +94,8 @@ bool AMDGPUIntegerDivision::shouldExpandDivRem(const BinaryOperator &I) { assert(TLI); - bool shouldExpandInIr = TLI && TLI->shouldExpandDivRemInIR(I); - // TODO:Uthkarsh later modify to handle signed 64 bit too. - bool isUdiv64 = I.getOpcode() == Instruction::UDiv && I.getType()->getIntegerBitWidth() == 64; + bool shouldExpandInIr = TLI && TLI->shouldExpandDivRemInIR(I); + bool isUdiv64 = I.getOpcode() == Instruction::UDiv && I.getType()->isIntegerTy(64); return shouldExpandInIr && isUdiv64; } /*TODO:Uthkarsh @@ -145,6 +137,4 @@ FunctionPass *llvm::createAMDGPUIntegerDivisionPass(const TargetMachine *TM) { return new AMDGPUIntegerDivision(TM); -} - -//static RegisterPass X("AMD GPU Integer Division", "IR level 64 bit integer division",false,false); \ No newline at end of file +} \ No newline at end of file