Index: include/llvm/CodeGen/MachineBasicBlock.h
===================================================================
--- include/llvm/CodeGen/MachineBasicBlock.h
+++ include/llvm/CodeGen/MachineBasicBlock.h
@@ -734,6 +734,25 @@
   /// unless you know what you're doing, because it doesn't update Pred's
   /// successors list. Use Pred->removeSuccessor instead.
   void removePredecessor(MachineBasicBlock *Pred);
+
+public:
+  enum MBBCFIType {
+    IN_PATH,
+    PROLOGUE,
+    EPILOGUE,
+    OUT_PATH
+  };
+
+  enum MBBCFIType getMBBCFIType() {
+    return CFIType;
+  }
+
+  void setMBBCFIType(enum MBBCFIType type) {
+    CFIType = type;
+  }
+
+private:
+  enum MBBCFIType CFIType = IN_PATH;
 };
 
 raw_ostream& operator<<(raw_ostream &OS, const MachineBasicBlock &MBB);
Index: lib/CodeGen/BranchFolding.cpp
===================================================================
--- lib/CodeGen/BranchFolding.cpp
+++ lib/CodeGen/BranchFolding.cpp
@@ -285,6 +285,9 @@
   I2 = MBB2->end();
 
   unsigned TailLen = 0;
+  MachineFunction &MF = *MBB1->getParent();
+  bool IsX86 = MF.getTarget().getTargetTriple().getArch() == Triple::x86_64 ||
+               MF.getTarget().getTargetTriple().getArch() == Triple::x86;
   while (I1 != MBB1->begin() && I2 != MBB2->begin()) {
     --I1; --I2;
     // Skip debugging pseudos; necessary to avoid changing the code.
@@ -312,17 +315,25 @@
       --I2;
     }
     // I1, I2==first (untested) non-DBGs preceding known match
-    if (!I1->isIdenticalTo(*I2) ||
-        // FIXME: This check is dubious. It's used to get around a problem where
-        // people incorrectly expect inline asm directives to remain in the same
-        // relative order. This is untenable because normal compiler
-        // optimizations (like this one) may reorder and/or merge these
-        // directives.
-        I1->isInlineAsm()) {
+    if (!IsX86) {
+      if (!I1->isIdenticalTo(*I2) ||
+          // FIXME: This check is dubious. It's used to get around a problem
+          // where people incorrectly expect inline asm directives to remain
+          // in the same relative order. This is untenable because normal
+          // compiler optimizations (like this one) may reorder and/or merge
+          // these directives.
+          I1->isInlineAsm()) {
+        ++I1; ++I2;
+        break;
+      }
+    } else if ((!I1->isIdenticalTo(*I2) && !I1->isCFIInstruction()) ||
+               I1->isInlineAsm()) {
       ++I1; ++I2;
       break;
     }
-    ++TailLen;
+
+    if ((IsX86 && !I1->isCFIInstruction()) || !IsX86)
+      ++TailLen;
   }
   // Back past possible debugging pseudos at beginning of block.  This matters
   // when one block differs from the other only by whether debugging pseudos
@@ -406,6 +417,27 @@
     FuncletMembership[NewMBB] = n;
   }
 
+  bool IsX86 = MF.getTarget().getTargetTriple().getArch() == Triple::x86_64 ||
+               MF.getTarget().getTargetTriple().getArch() == Triple::x86;
+  if (IsX86 && CurMBB.getMBBCFIType() == MachineBasicBlock::EPILOGUE) {
+    MachineBasicBlock::iterator InstrIter;
+    CurMBB.setMBBCFIType(MachineBasicBlock::IN_PATH);
+    NewMBB->setMBBCFIType(MachineBasicBlock::IN_PATH);
+    for (InstrIter = CurMBB.instr_begin(); InstrIter != CurMBB.instr_end();
+         ++InstrIter) {
+      if (InstrIter->isCFIInstruction()) {
+        CurMBB.setMBBCFIType(MachineBasicBlock::EPILOGUE);
+        break;
+      }
+    }
+    for (InstrIter = NewMBB->instr_begin(); InstrIter != NewMBB->instr_end();
+         ++InstrIter) {
+      if (InstrIter->isCFIInstruction()) {
+        NewMBB->setMBBCFIType(MachineBasicBlock::EPILOGUE);
+        break;
+      }
+    }
+  }
   return NewMBB;
 }
 
@@ -781,9 +813,13 @@
     while ((MBBICommon != MBBIECommon) && MBBICommon->isDebugValue())
       ++MBBICommon;
 
+    MachineFunction &MF = *MBB->getParent();
+    bool IsX86 = MF.getTarget().getTargetTriple().getArch() == Triple::x86_64 ||
+                 MF.getTarget().getTargetTriple().getArch() == Triple::x86;
     assert(MBBICommon != MBBIECommon &&
            "Reached BB end within common tail length!");
-    assert(MBBICommon->isIdenticalTo(*MBBI) && "Expected matching MIIs!");
+    if (!(IsX86 && MBBICommon->isCFIInstruction()))
+      assert(MBBICommon->isIdenticalTo(*MBBI) && "Expected matching MIIs!");
 
     // Merge MMOs from memory operations in the common block.
     if (MBBICommon->mayLoad() || MBBICommon->mayStore())
@@ -901,6 +937,9 @@
     }
 
     MachineBasicBlock *MBB = SameTails[commonTailIndex].getBlock();
+    MachineFunction &MF = *MBB->getParent();
+    bool IsX86 = MF.getTarget().getTargetTriple().getArch() == Triple::x86_64 ||
+                 MF.getTarget().getTargetTriple().getArch() == Triple::x86;
 
     // Recompute common tail MBB's edge weights and block frequency.
     setCommonTailEdgeWeights(*MBB);
@@ -923,6 +962,11 @@
       mergeOperations(SameTails[i].getTailStartPos(), *MBB);
       // Hack the end off BB i, making it jump to BB commonTailIndex instead.
       ReplaceTailWithBranchTo(SameTails[i].getTailStartPos(), MBB);
+
+      if (IsX86 && MBB->getMBBCFIType() == MachineBasicBlock::EPILOGUE) {
+        SameTails[i].getBlock()->setMBBCFIType(MachineBasicBlock::IN_PATH);
+      }
+
       // BB i is no longer a predecessor of SuccBB; remove it from the worklist.
       MergePotentials.erase(SameTails[i].getMPIter());
     }
@@ -1334,6 +1378,12 @@
       PrevBB.removeSuccessor(PrevBB.succ_begin());
       assert(PrevBB.succ_empty());
       PrevBB.transferSuccessors(MBB);
+
+      bool IsX86 =
+          MF.getTarget().getTargetTriple().getArch() == Triple::x86_64 ||
+          MF.getTarget().getTargetTriple().getArch() == Triple::x86;
+      if (IsX86 && MBB->getMBBCFIType() == MachineBasicBlock::EPILOGUE)
+        PrevBB.setMBBCFIType(MBB->getMBBCFIType());
       MadeChange = true;
       return MadeChange;
     }
Index: lib/CodeGen/TailDuplicator.cpp
===================================================================
--- lib/CodeGen/TailDuplicator.cpp
+++ lib/CodeGen/TailDuplicator.cpp
@@ -432,6 +432,11 @@
     }
   }
   PredBB->insert(PredBB->instr_end(), NewMI);
+
+  bool IsX86 = MF->getTarget().getTargetTriple().getArch() == Triple::x86_64 ||
+               MF->getTarget().getTargetTriple().getArch() == Triple::x86;
+  if(IsX86 && NewMI->isCFIInstruction())
+    PredBB->setMBBCFIType(MachineBasicBlock::EPILOGUE);
 }
 
 /// After FromBB is tail duplicated into its predecessor blocks, the successors
@@ -570,10 +575,13 @@
   // Check the instructions in the block to determine whether tail-duplication
   // is invalid or unlikely to be profitable.
   unsigned InstrCount = 0;
+  bool IsX86 = MF->getTarget().getTargetTriple().getArch() == Triple::x86_64 ||
+               MF->getTarget().getTargetTriple().getArch() == Triple::x86;
   for (MachineInstr &MI : TailBB) {
     // Non-duplicable things shouldn't be tail-duplicated.
     if (MI.isNotDuplicable())
-      return false;
+      if (!IsX86 || (IsX86 && !MI.isCFIInstruction()))
+        return false;
 
     // Convergent instructions can be duplicated only if doing so doesn't add
     // new control dependencies, which is what we're going to do here.
@@ -593,7 +601,8 @@
       return false;
 
     if (!MI.isPHI() && !MI.isDebugValue())
-      InstrCount += 1;
+       if (!IsX86 || (IsX86 && !MI.isCFIInstruction()))
+         InstrCount += 1;
 
     if (InstrCount > MaxDuplicateCount)
       return false;
Index: lib/CodeGen/TargetInstrInfo.cpp
===================================================================
--- lib/CodeGen/TargetInstrInfo.cpp
+++ lib/CodeGen/TargetInstrInfo.cpp
@@ -390,7 +390,12 @@
 
 MachineInstr *TargetInstrInfo::duplicate(MachineInstr &Orig,
                                          MachineFunction &MF) const {
-  assert(!Orig.isNotDuplicable() && "Instruction cannot be duplicated");
+  bool IsX86 = MF.getTarget().getTargetTriple().getArch() == Triple::x86_64 ||
+               MF.getTarget().getTargetTriple().getArch() == Triple::x86;
+
+  if (!(IsX86 && Orig.isCFIInstruction()))
+    assert(!Orig.isNotDuplicable() && "Instruction cannot be duplicated");
+
   return MF.CloneMachineInstr(&Orig);
 }
 
Index: lib/Target/X86/CMakeLists.txt
===================================================================
--- lib/Target/X86/CMakeLists.txt
+++ lib/Target/X86/CMakeLists.txt
@@ -36,6 +36,7 @@
 set(sources
   X86AsmPrinter.cpp
   X86CallFrameOptimization.cpp
+  X86CFIInstrInserter.cpp
   X86ExpandPseudo.cpp
   X86FastISel.cpp
   X86FixupBWInsts.cpp
Index: lib/Target/X86/X86.h
===================================================================
--- lib/Target/X86/X86.h
+++ lib/Target/X86/X86.h
@@ -86,6 +86,10 @@
 /// the upper portions of registers, and to save code size.
 FunctionPass *createX86FixupBWInsts();
 
+/// Return a pass that inserts CFI instructions in order to
+/// provide precise unwind info for a machine function.
+FunctionPass *createX86CFIInstrInserter();
+
 void initializeFixupBWInstPassPass(PassRegistry &);
 
 /// This pass replaces EVEX ecnoded of AVX-512 instructiosn by VEX 
Index: lib/Target/X86/X86CFIInstrInserter.cpp
===================================================================
--- /dev/null
+++ lib/Target/X86/X86CFIInstrInserter.cpp
@@ -0,0 +1,152 @@
+//===------ X86CFIInstrInserter.cpp - Insert needed CFI instructions ------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass inserts additional CFI instructions where needed in order to
+// provide precise unwind info for a machine function.
+//
+//===----------------------------------------------------------------------===//
+
+#include "X86.h"
+#include "X86FrameLowering.h"
+#include "X86Subtarget.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+
+using namespace llvm;
+
+namespace {
+class X86CFIInstrInserter : public MachineFunctionPass {
+public:
+  X86CFIInstrInserter() : MachineFunctionPass(ID) {}
+  bool runOnMachineFunction(MachineFunction &MF) override;
+  static char ID;
+
+private:
+  StringRef getPassName() const override {
+    return "X86 CFI Instruction Inserter";
+  }
+
+  // Insert CFI instructions to the beginnings of MBBs, if that insertion is
+  // needed. CorrectCFA will insert additional CFI instructions if the epilogue
+  // sets offset or register values that do not apply to MBBs below it.
+  void CorrectCFA(MachineFunction &MF);
+
+  const X86Subtarget *ST;
+  const X86RegisterInfo *RI;
+  const X86FrameLowering *TFL;
+  const MCRegisterInfo *MRI;
+  unsigned StackPtr;
+  unsigned FramePtr;
+  bool Is64Bit;
+
+  // Initial frame state register
+  int InitialRegister;
+
+  // Initial frame state offset
+  int InitialOffset;
+
+  // Were any CFI instructions inserted
+  bool InsertedCFIInstr = false;
+  bool HasFP;
+  MachineFrameInfo *MFI;
+  int StackSize;
+};
+
+char X86CFIInstrInserter::ID = 0;
+}
+
+FunctionPass *llvm::createX86CFIInstrInserter() {
+  return new X86CFIInstrInserter();
+}
+
+bool X86CFIInstrInserter::runOnMachineFunction(MachineFunction &MF) {
+  bool NeedsDwarfCFI =
+      MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry();
+
+  if (!NeedsDwarfCFI)
+    return false;
+
+  ST = &MF.getSubtarget<X86Subtarget>();
+  RI = ST->getRegisterInfo();
+  TFL = ST->getFrameLowering();
+  MRI = MF.getMMI().getContext().getRegisterInfo();
+  Is64Bit = ST->is64Bit();
+
+  MachineFrameInfo *MFI = &MF.getFrameInfo();
+
+  FramePtr = Is64Bit ? X86::RBP : X86::EBP;
+  StackPtr = Is64Bit ? X86::RSP : X86::ESP;
+
+  InitialRegister = RI->getDwarfRegNum(StackPtr, true);
+  InitialOffset = -RI->getSlotSize();
+
+  HasFP = TFL->hasFP(MF);
+  StackSize = -MFI->getStackSize();
+  // Update ordinal numbers of MBBs
+  MF.RenumberBlocks();
+
+  // Insert appropriate CFI instructions for each MBB if CFA calculation rule
+  // needs to be corrected for that MBB
+  CorrectCFA(MF);
+
+  return InsertedCFIInstr;
+}
+
+void X86CFIInstrInserter::CorrectCFA(MachineFunction &MF) {
+  MachineBasicBlock &FirstMBB = MF.front();
+  MachineBasicBlock::MBBCFIType PrevMBBType = FirstMBB.getMBBCFIType();
+  bool ShouldInsertCFI = false;
+
+  for (auto &MBB : MF) {
+    if (!ShouldInsertCFI && (PrevMBBType == MachineBasicBlock::PROLOGUE ||
+                             PrevMBBType == MachineBasicBlock::EPILOGUE))
+      ShouldInsertCFI = true;
+    // Skip the first MBB in a function
+    if (MBB.getNumber() == FirstMBB.getNumber())
+      continue;
+
+    MachineBasicBlock::MBBCFIType CurrMBBType = MBB.getMBBCFIType();
+
+    auto MBBI = MBB.begin();
+    DebugLoc DL = MBB.findDebugLoc(MBBI);
+
+    if (ShouldInsertCFI) {
+      // Cover cases where MBBs have prologue offset set by previous CFI
+      // instructions but should have initial offset at their beginning
+      if (PrevMBBType == MachineBasicBlock::PROLOGUE ||
+          PrevMBBType == MachineBasicBlock::IN_PATH) {
+        if (CurrMBBType == MachineBasicBlock::PROLOGUE ||
+            CurrMBBType == MachineBasicBlock::OUT_PATH) {
+          TFL->BuildCFI(MBB, MBBI, DL,
+                        MCCFIInstruction::createDefCfa(nullptr, InitialRegister,
+                                                       InitialOffset));
+          InsertedCFIInstr = true;
+        }
+        // Cover cases where MBBs have initial offset set by previous CFI
+        // instructions but should have prologue offset at their beginning
+      } else if (PrevMBBType == MachineBasicBlock::EPILOGUE ||
+                 PrevMBBType == MachineBasicBlock::OUT_PATH) {
+        if (CurrMBBType == MachineBasicBlock::EPILOGUE ||
+            CurrMBBType == MachineBasicBlock::IN_PATH) {
+          if (HasFP)
+            TFL->BuildCFI(MBB, MBBI, DL,
+                          MCCFIInstruction::createDefCfa(
+                              nullptr, MRI->getDwarfRegNum(FramePtr, true),
+                              2 * InitialOffset));
+          else
+            TFL->BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfa(
+                                             nullptr, InitialRegister,
+                                             InitialOffset + StackSize));
+          InsertedCFIInstr = true;
+        }
+      }
+    }
+    PrevMBBType = CurrMBBType;
+  }
+}
Index: lib/Target/X86/X86FrameLowering.cpp
===================================================================
--- lib/Target/X86/X86FrameLowering.cpp
+++ lib/Target/X86/X86FrameLowering.cpp
@@ -32,6 +32,7 @@
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Support/Debug.h"
 #include <cstdlib>
+#include <queue>
 
 using namespace llvm;
 
@@ -935,7 +936,8 @@
           ? getX86SubSuperRegister(FramePtr, 64) : FramePtr;
   unsigned BasePtr = TRI->getBaseRegister();
   bool HasWinCFI = false;
-  
+  bool InsertedCFI = false;
+
   // Debug location must be unknown since the first debug location is used
   // to determine the end of the prologue.
   DebugLoc DL;
@@ -1060,6 +1062,7 @@
       unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
       BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createOffset(
                                   nullptr, DwarfFramePtr, 2 * stackGrowth));
+      InsertedCFI = true;
     }
 
     if (NeedsWinCFI) {
@@ -1083,6 +1086,7 @@
         unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
         BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaRegister(
                                     nullptr, DwarfFramePtr));
+        InsertedCFI = true;
       }
     }
 
@@ -1122,6 +1126,7 @@
       BuildCFI(MBB, MBBI, DL,
                MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
       StackOffset += stackGrowth;
+      InsertedCFI = true;
     }
 
     if (NeedsWinCFI) {
@@ -1384,6 +1389,7 @@
       assert(StackSize);
       BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaOffset(
                                   nullptr, -StackSize + stackGrowth));
+      InsertedCFI = true;
     }
 
     // Emit DWARF info specifying the offsets of the callee-saved registers.
@@ -1405,6 +1411,48 @@
 
   // At this point we know if the function has WinCFI or not.
   MF.setHasWinCFI(HasWinCFI);
+
+  if (InsertedCFI) {
+    // Mark this MBB as prologue
+    MBB.setMBBCFIType(MachineBasicBlock::PROLOGUE);
+
+    // TODO: Do this search more efficiently
+    std::queue<MachineBasicBlock*> Predecessors;
+    Predecessors.push(&MBB);
+    std::queue<MachineBasicBlock*> Successors;
+
+    while (!Predecessors.empty()) {
+      MachineBasicBlock* TopMBB = Predecessors.front();
+      Predecessors.pop();
+      // Find all MBBs that precede prologue and mark them as MBBs out of the
+      // prologue/epilogue path
+      for (auto Pred : TopMBB->predecessors()) {
+        if (Pred->getNumber() == TopMBB->getNumber()) continue;
+        Pred->setMBBCFIType(MachineBasicBlock::OUT_PATH);
+        Predecessors.push(Pred);
+        // Find successors of the MBBs that precede prologue (except prologue
+        // itself), that are also not in the prologue/epilogue path
+        for (auto Succ : Pred->successors()) {
+          if (Succ->getNumber() == TopMBB->getNumber()) continue;
+          if (Succ->getNumber() == MBB.getNumber()) continue;
+          Succ->setMBBCFIType(MachineBasicBlock::OUT_PATH);
+          Successors.push(Succ);
+        }
+      }
+    }
+    // Go through all successors of the MBBs that precede prologue (except
+    // prologue itself), and mark them as not in the prologue/epilogue path
+    while (!Successors.empty()) {
+      MachineBasicBlock* TopMBB = Successors.front();
+      Successors.pop();
+      for (auto Succ : TopMBB->successors()) {
+        if (Succ->getNumber() == TopMBB->getNumber()) continue;
+        if (Succ->getNumber() == MBB.getNumber()) continue;
+        Succ->setMBBCFIType(MachineBasicBlock::OUT_PATH);
+        Successors.push(Succ);
+      }
+    }
+  }
 }
 
 bool X86FrameLowering::canUseLEAForSPInEpilogue(
@@ -1515,6 +1563,12 @@
   unsigned CSSize = X86FI->getCalleeSavedFrameSize();
   uint64_t NumBytes = 0;
 
+  bool NeedsDwarfCFI = (MF.getMMI().hasDebugInfo() ||
+                        MF.getFunction()->needsUnwindTableEntry()) &&
+                       (!MF.getSubtarget<X86Subtarget>().isTargetDarwin() &&
+                        !MF.getSubtarget<X86Subtarget>().isOSWindows());
+  bool InsertedCFI = false;
+
   if (RetOpcode && *RetOpcode == X86::CATCHRET) {
     // SEH shouldn't use catchret.
     assert(!isAsynchronousEHPersonality(
@@ -1549,6 +1603,14 @@
     BuildMI(MBB, MBBI, DL,
             TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr)
         .setMIFlag(MachineInstr::FrameDestroy);
+    if (NeedsDwarfCFI) {
+      unsigned DwarfStackPtr =
+          TRI->getDwarfRegNum(Is64Bit ? X86::RSP : X86::ESP, true);
+      BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfa(
+                                  nullptr, DwarfStackPtr, -SlotSize));
+      --MBBI;
+      InsertedCFI = true;
+    }
   } else {
     NumBytes = StackSize - CSSize;
   }
@@ -1633,6 +1695,12 @@
   } else if (NumBytes) {
     // Adjust stack pointer back: ESP += numbytes.
     emitSPUpdate(MBB, MBBI, NumBytes, /*InEpilogue=*/true);
+    if (!hasFP(MF) && NeedsDwarfCFI) {
+      // Define the current CFA rule to use the provided offset.
+      BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaOffset(
+                                  nullptr, -CSSize - SlotSize));
+      InsertedCFI = true;
+    }
     --MBBI;
   }
 
@@ -1645,6 +1713,23 @@
   if (NeedsWinCFI && MF.hasWinCFI())
     BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
 
+  if (!hasFP(MF) && NeedsDwarfCFI) {
+    MBBI = FirstCSPop;
+    int64_t Offset = -CSSize - SlotSize;
+    // Mark callee-saved pop instruction.
+    // Define the current CFA rule to use the provided offset.
+    while (MBBI != MBB.end()) {
+      MachineBasicBlock::iterator PI = MBBI;
+      unsigned Opc = PI->getOpcode();
+      ++MBBI;
+      if (Opc == X86::POP32r || Opc == X86::POP64r) {
+        Offset += SlotSize;
+        BuildCFI(MBB, MBBI, DL,
+                 MCCFIInstruction::createDefCfaOffset(nullptr, Offset));
+        InsertedCFI = true;
+      }
+    }
+  }
   if (!RetOpcode || !isTailCallOpcode(*RetOpcode)) {
     // Add the return addr area delta back since we are not tail calling.
     int Offset = -1 * X86FI->getTCReturnAddrDelta();
@@ -1657,6 +1742,23 @@
       emitSPUpdate(MBB, MBBI, Offset, /*InEpilogue=*/true);
     }
   }
+
+  if (InsertedCFI) {
+    MBB.setMBBCFIType(MachineBasicBlock::EPILOGUE);
+    std::queue<MachineBasicBlock *> Successors;
+    Successors.push(&MBB);
+    // Find all successors of the epilogue and mark them as not in the
+    // prologue/epilogue path
+    while (!Successors.empty()) {
+      MachineBasicBlock *TopMBB = Successors.front();
+      Successors.pop();
+      for (auto Succ : TopMBB->successors()) {
+        if (Succ->getNumber() == TopMBB->getNumber()) continue;
+        Succ->setMBBCFIType(MachineBasicBlock::OUT_PATH);
+        Successors.push(Succ);
+      }
+    }
+  }
 }
 
 // NOTE: this only has a subset of the full frame index logic. In
@@ -2243,9 +2345,16 @@
       assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
              "Scratch register is live-in and not saved");
 
-      if (SaveScratch2)
+      if (SaveScratch2) {
         BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
           .addReg(ScratchReg2, RegState::Kill);
+        if (MF.getMMI().hasDebugInfo()) {
+          MachineBasicBlock::iterator It = checkMBB->getLastNonDebugInstr();
+          ++It;
+          BuildCFI(*checkMBB, It, DL,
+                  MCCFIInstruction::createAdjustCfaOffset(nullptr, SlotSize));
+        }
+      }
 
       BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
         .addImm(TlsOffset);
@@ -2503,6 +2612,9 @@
     stackCheckMBB->addSuccessor(incStackMBB, {1, 100});
     incStackMBB->addSuccessor(&PrologueMBB, {99, 100});
     incStackMBB->addSuccessor(incStackMBB, {1, 100});
+
+    stackCheckMBB->setMBBCFIType(MachineBasicBlock::OUT_PATH);
+    incStackMBB->setMBBCFIType(MachineBasicBlock::OUT_PATH);
   }
 #ifdef EXPENSIVE_CHECKS
   MF.verify();
@@ -2856,6 +2968,7 @@
     if (DensityAScaled == DensityBScaled)
       return A.ObjectAlignment < B.ObjectAlignment;
     
+
     return DensityAScaled < DensityBScaled;
   }
 };
Index: lib/Target/X86/X86TargetMachine.cpp
===================================================================
--- lib/Target/X86/X86TargetMachine.cpp
+++ lib/Target/X86/X86TargetMachine.cpp
@@ -443,4 +443,8 @@
     addPass(createX86FixupLEAs());
     addPass(createX86EvexToVexInsts());
   }
+
+  const Triple &TT = TM->getTargetTriple();
+  if (!TT.isOSDarwin() && !TT.isOSWindows())
+    addPass(createX86CFIInstrInserter());
 }
Index: test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll
===================================================================
--- test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll
+++ test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll
@@ -23,6 +23,7 @@
 }
 
 ; CHECK: lpad
-; CHECK-NEXT: Ltmp
+; CHECK-NEXT: Lcfi
+; CHECK: Ltmp
 
 declare i32 @__gxx_personality_v0(...)
Index: test/CodeGen/X86/2011-10-19-widen_vselect.ll
===================================================================
--- test/CodeGen/X86/2011-10-19-widen_vselect.ll
+++ test/CodeGen/X86/2011-10-19-widen_vselect.ll
@@ -91,6 +91,8 @@
 ; X32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X32-NEXT:    movsd %xmm0, {{[0-9]+}}(%esp)
 ; X32-NEXT:    addl $60, %esp
+; X32-NEXT:  .Lcfi1:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: full_test:
Index: test/CodeGen/X86/avg.ll
===================================================================
--- test/CodeGen/X86/avg.ll
+++ test/CodeGen/X86/avg.ll
@@ -451,6 +451,8 @@
 ; SSE2-NEXT:    movdqu %xmm12, (%rax)
 ; SSE2-NEXT:    movdqu %xmm14, (%rax)
 ; SSE2-NEXT:    addq $152, %rsp
+; SSE2-NEXT:  .Lcfi1:
+; SSE2-NEXT:    .cfi_def_cfa_offset 8
 ; SSE2-NEXT:    retq
 ;
 ; AVX2-LABEL: avg_v64i8:
Index: test/CodeGen/X86/avx512-i1test.ll
===================================================================
--- test/CodeGen/X86/avx512-i1test.ll
+++ test/CodeGen/X86/avx512-i1test.ll
@@ -10,20 +10,20 @@
 ; CHECK:       # BB#0: # %L_10
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    testb %al, %al
-; CHECK-NEXT:    je .LBB0_1
-; CHECK-NEXT:  # BB#4: # %L_30
+; CHECK-NEXT:    je .LBB0_2
+; CHECK-NEXT:  # BB#1: # %L_30
 ; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB0_1: # %bb56
+; CHECK-NEXT:  .LBB0_2: # %bb56
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    jmp .LBB0_2
+; CHECK-NEXT:    jmp .LBB0_4
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB0_3: # %bb35
-; CHECK-NEXT:    # in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT:    # in Loop: Header=BB0_4 Depth=1
 ; CHECK-NEXT:    testb %al, %al
-; CHECK-NEXT:  .LBB0_2: # %bb33
+; CHECK-NEXT:  .LBB0_4: # %bb33
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    testb %al, %al
-; CHECK-NEXT:    jne .LBB0_2
+; CHECK-NEXT:    jne .LBB0_4
 ; CHECK-NEXT:    jmp .LBB0_3
 bb1:
   br i1 undef, label %L_10, label %L_10
@@ -68,10 +68,10 @@
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    # kill: %EDI<def> %EDI<kill> %RDI<def>
 ; CHECK-NEXT:    testl %esi, %esi
-; CHECK-NEXT:    je .LBB1_1
-; CHECK-NEXT:  # BB#2: # %if.then
+; CHECK-NEXT:    je .LBB1_2
+; CHECK-NEXT:  # BB#1: # %if.then
 ; CHECK-NEXT:    jmp bar # TAILCALL
-; CHECK-NEXT:  .LBB1_1: # %return
+; CHECK-NEXT:  .LBB1_2: # %return
 ; CHECK-NEXT:    orq $-2, %rdi
 ; CHECK-NEXT:    movq %rdi, %rax
 ; CHECK-NEXT:    retq
Index: test/CodeGen/X86/avx512-vbroadcast.ll
===================================================================
--- test/CodeGen/X86/avx512-vbroadcast.ll
+++ test/CodeGen/X86/avx512-vbroadcast.ll
@@ -414,6 +414,8 @@
 ; ALL-NEXT:    callq func_f32
 ; ALL-NEXT:    vbroadcastss (%rsp), %zmm0 # 16-byte Folded Reload
 ; ALL-NEXT:    addq $24, %rsp
+; ALL-NEXT:  .Lcfi1:
+; ALL-NEXT:    .cfi_def_cfa_offset 8
 ; ALL-NEXT:    retq
   %a  = fadd float %x, %x
   call void @func_f32(float %a)
@@ -427,13 +429,15 @@
 ; ALL-LABEL: broadcast_sd_spill:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    subq $24, %rsp
-; ALL-NEXT:  .Lcfi1:
+; ALL-NEXT:  .Lcfi2:
 ; ALL-NEXT:    .cfi_def_cfa_offset 32
 ; ALL-NEXT:    vaddsd %xmm0, %xmm0, %xmm0
 ; ALL-NEXT:    vmovapd %xmm0, (%rsp) # 16-byte Spill
 ; ALL-NEXT:    callq func_f64
 ; ALL-NEXT:    vbroadcastsd (%rsp), %zmm0 # 16-byte Folded Reload
 ; ALL-NEXT:    addq $24, %rsp
+; ALL-NEXT:  .Lcfi3:
+; ALL-NEXT:    .cfi_def_cfa_offset 8
 ; ALL-NEXT:    retq
   %a  = fadd double %x, %x
   call void @func_f64(double %a)
Index: test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
===================================================================
--- test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
+++ test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
@@ -289,6 +289,8 @@
 ; AVX512F-32-NEXT:    movl (%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $12, %esp
+; AVX512F-32-NEXT:  .Lcfi1:
+; AVX512F-32-NEXT:    .cfi_def_cfa_offset 4
 ; AVX512F-32-NEXT:    retl
   %res = call i64 @llvm.x86.avx512.mask.pcmpeq.b.512(<64 x i8> %a, <64 x i8> %b, i64 -1)
   ret i64 %res
@@ -305,7 +307,7 @@
 ; AVX512F-32-LABEL: test_mask_pcmpeq_b:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $12, %esp
-; AVX512F-32-NEXT:  .Lcfi1:
+; AVX512F-32-NEXT:  .Lcfi2:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 16
 ; AVX512F-32-NEXT:    kmovq {{[0-9]+}}(%esp), %k1
 ; AVX512F-32-NEXT:    vpcmpeqb %zmm1, %zmm0, %k0 {%k1}
@@ -313,6 +315,8 @@
 ; AVX512F-32-NEXT:    movl (%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $12, %esp
+; AVX512F-32-NEXT:  .Lcfi3:
+; AVX512F-32-NEXT:    .cfi_def_cfa_offset 4
 ; AVX512F-32-NEXT:    retl
   %res = call i64 @llvm.x86.avx512.mask.pcmpeq.b.512(<64 x i8> %a, <64 x i8> %b, i64 %mask)
   ret i64 %res
@@ -366,13 +370,15 @@
 ; AVX512F-32-LABEL: test_pcmpgt_b:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $12, %esp
-; AVX512F-32-NEXT:  .Lcfi2:
+; AVX512F-32-NEXT:  .Lcfi4:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 16
 ; AVX512F-32-NEXT:    vpcmpgtb %zmm1, %zmm0, %k0
 ; AVX512F-32-NEXT:    kmovq %k0, (%esp)
 ; AVX512F-32-NEXT:    movl (%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $12, %esp
+; AVX512F-32-NEXT:  .Lcfi5:
+; AVX512F-32-NEXT:    .cfi_def_cfa_offset 4
 ; AVX512F-32-NEXT:    retl
   %res = call i64 @llvm.x86.avx512.mask.pcmpgt.b.512(<64 x i8> %a, <64 x i8> %b, i64 -1)
   ret i64 %res
@@ -389,7 +395,7 @@
 ; AVX512F-32-LABEL: test_mask_pcmpgt_b:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $12, %esp
-; AVX512F-32-NEXT:  .Lcfi3:
+; AVX512F-32-NEXT:  .Lcfi6:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 16
 ; AVX512F-32-NEXT:    kmovq {{[0-9]+}}(%esp), %k1
 ; AVX512F-32-NEXT:    vpcmpgtb %zmm1, %zmm0, %k0 {%k1}
@@ -397,6 +403,8 @@
 ; AVX512F-32-NEXT:    movl (%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $12, %esp
+; AVX512F-32-NEXT:  .Lcfi7:
+; AVX512F-32-NEXT:    .cfi_def_cfa_offset 4
 ; AVX512F-32-NEXT:    retl
   %res = call i64 @llvm.x86.avx512.mask.pcmpgt.b.512(<64 x i8> %a, <64 x i8> %b, i64 %mask)
   ret i64 %res
Index: test/CodeGen/X86/avx512bw-intrinsics.ll
===================================================================
--- test/CodeGen/X86/avx512bw-intrinsics.ll
+++ test/CodeGen/X86/avx512bw-intrinsics.ll
@@ -68,6 +68,8 @@
 ; AVX512F-32-NEXT:    addl (%esp), %eax
 ; AVX512F-32-NEXT:    adcxl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $68, %esp
+; AVX512F-32-NEXT:  .Lcfi1:
+; AVX512F-32-NEXT:    .cfi_def_cfa_offset 4
 ; AVX512F-32-NEXT:    retl
   %res0 = call i64 @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 0, i64 -1)
   %res1 = call i64 @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 1, i64 -1)
@@ -119,7 +121,7 @@
 ; AVX512F-32-LABEL: test_mask_cmp_b_512:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $68, %esp
-; AVX512F-32-NEXT:  .Lcfi1:
+; AVX512F-32-NEXT:  .Lcfi2:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 72
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k0
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k1
@@ -157,6 +159,8 @@
 ; AVX512F-32-NEXT:    addl {{[0-9]+}}(%esp), %eax
 ; AVX512F-32-NEXT:    adcxl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $68, %esp
+; AVX512F-32-NEXT:  .Lcfi3:
+; AVX512F-32-NEXT:    .cfi_def_cfa_offset 4
 ; AVX512F-32-NEXT:    retl
   %res0 = call i64 @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 0, i64 %mask)
   %res1 = call i64 @llvm.x86.avx512.mask.cmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 1, i64 %mask)
@@ -209,7 +213,7 @@
 ; AVX512F-32-LABEL: test_ucmp_b_512:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $68, %esp
-; AVX512F-32-NEXT:  .Lcfi2:
+; AVX512F-32-NEXT:  .Lcfi4:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 72
 ; AVX512F-32-NEXT:    vpcmpequb %zmm1, %zmm0, %k0
 ; AVX512F-32-NEXT:    kmovq %k0, {{[0-9]+}}(%esp)
@@ -244,6 +248,8 @@
 ; AVX512F-32-NEXT:    addl (%esp), %eax
 ; AVX512F-32-NEXT:    adcxl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $68, %esp
+; AVX512F-32-NEXT:  .Lcfi5:
+; AVX512F-32-NEXT:    .cfi_def_cfa_offset 4
 ; AVX512F-32-NEXT:    retl
   %res0 = call i64 @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 0, i64 -1)
   %res1 = call i64 @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 1, i64 -1)
@@ -295,7 +301,7 @@
 ; AVX512F-32-LABEL: test_mask_x86_avx512_ucmp_b_512:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $68, %esp
-; AVX512F-32-NEXT:  .Lcfi3:
+; AVX512F-32-NEXT:  .Lcfi6:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 72
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k0
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k1
@@ -333,6 +339,8 @@
 ; AVX512F-32-NEXT:    addl {{[0-9]+}}(%esp), %eax
 ; AVX512F-32-NEXT:    adcxl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $68, %esp
+; AVX512F-32-NEXT:  .Lcfi7:
+; AVX512F-32-NEXT:    .cfi_def_cfa_offset 4
 ; AVX512F-32-NEXT:    retl
   %res0 = call i64 @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 0, i64 %mask)
   %res1 = call i64 @llvm.x86.avx512.mask.ucmp.b.512(<64 x i8> %a0, <64 x i8> %a1, i32 1, i64 %mask)
@@ -2239,7 +2247,7 @@
 ; AVX512F-32-LABEL: test_int_x86_avx512_kunpck_qd:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $12, %esp
-; AVX512F-32-NEXT:  .Lcfi4:
+; AVX512F-32-NEXT:  .Lcfi8:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 16
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k0
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k1
@@ -2248,6 +2256,8 @@
 ; AVX512F-32-NEXT:    movl (%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $12, %esp
+; AVX512F-32-NEXT:  .Lcfi9:
+; AVX512F-32-NEXT:    .cfi_def_cfa_offset 4
 ; AVX512F-32-NEXT:    retl
   %res = call i64 @llvm.x86.avx512.kunpck.dq(i64 %x0, i64 %x1)
   ret i64 %res
@@ -2265,13 +2275,15 @@
 ; AVX512F-32-LABEL: test_int_x86_avx512_cvtb2mask_512:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $12, %esp
-; AVX512F-32-NEXT:  .Lcfi5:
+; AVX512F-32-NEXT:  .Lcfi10:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 16
 ; AVX512F-32-NEXT:    vpmovb2m %zmm0, %k0
 ; AVX512F-32-NEXT:    kmovq %k0, (%esp)
 ; AVX512F-32-NEXT:    movl (%esp), %eax
 ; AVX512F-32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $12, %esp
+; AVX512F-32-NEXT:  .Lcfi11:
+; AVX512F-32-NEXT:    .cfi_def_cfa_offset 4
 ; AVX512F-32-NEXT:    retl
     %res = call i64 @llvm.x86.avx512.cvtb2mask.512(<64 x i8> %x0)
     ret i64 %res
@@ -2487,7 +2499,7 @@
 ; AVX512F-32-LABEL: test_int_x86_avx512_ptestm_b_512:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $20, %esp
-; AVX512F-32-NEXT:  .Lcfi6:
+; AVX512F-32-NEXT:  .Lcfi12:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 24
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k0
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k1
@@ -2501,6 +2513,8 @@
 ; AVX512F-32-NEXT:    addl {{[0-9]+}}(%esp), %eax
 ; AVX512F-32-NEXT:    adcxl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $20, %esp
+; AVX512F-32-NEXT:  .Lcfi13:
+; AVX512F-32-NEXT:    .cfi_def_cfa_offset 4
 ; AVX512F-32-NEXT:    retl
   %res = call i64 @llvm.x86.avx512.ptestm.b.512(<64 x i8> %x0, <64 x i8> %x1, i64 %x2)
   %res1 = call i64 @llvm.x86.avx512.ptestm.b.512(<64 x i8> %x0, <64 x i8> %x1, i64-1)
@@ -2552,7 +2566,7 @@
 ; AVX512F-32-LABEL: test_int_x86_avx512_ptestnm_b_512:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    subl $20, %esp
-; AVX512F-32-NEXT:  .Lcfi7:
+; AVX512F-32-NEXT:  .Lcfi14:
 ; AVX512F-32-NEXT:    .cfi_def_cfa_offset 24
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k0
 ; AVX512F-32-NEXT:    kmovd {{[0-9]+}}(%esp), %k1
@@ -2566,6 +2580,8 @@
 ; AVX512F-32-NEXT:    addl {{[0-9]+}}(%esp), %eax
 ; AVX512F-32-NEXT:    adcxl {{[0-9]+}}(%esp), %edx
 ; AVX512F-32-NEXT:    addl $20, %esp
+; AVX512F-32-NEXT:  .Lcfi15:
+; AVX512F-32-NEXT:    .cfi_def_cfa_offset 4
 ; AVX512F-32-NEXT:    retl
   %res = call i64 @llvm.x86.avx512.ptestnm.b.512(<64 x i8> %x0, <64 x i8> %x1, i64 %x2)
   %res1 = call i64 @llvm.x86.avx512.ptestnm.b.512(<64 x i8> %x0, <64 x i8> %x1, i64-1)
Index: test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll
===================================================================
--- test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll
+++ test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll
@@ -33,6 +33,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpbroadcastd %xmm1, %xmm0 {%k1}
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi1:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_mask_broadcastd_epi32:
@@ -57,7 +59,7 @@
 ; X32-LABEL: test_mm_maskz_broadcastd_epi32:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi1:
+; X32-NEXT:  .Lcfi2:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -66,6 +68,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpbroadcastd %xmm0, %xmm0 {%k1} {z}
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi3:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_maskz_broadcastd_epi32:
@@ -162,7 +166,7 @@
 ; X32-LABEL: test_mm_mask_broadcastq_epi64:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi2:
+; X32-NEXT:  .Lcfi4:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
@@ -171,6 +175,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpbroadcastq %xmm1, %xmm0 {%k1}
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi5:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_mask_broadcastq_epi64:
@@ -192,7 +198,7 @@
 ; X32-LABEL: test_mm_maskz_broadcastq_epi64:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi3:
+; X32-NEXT:  .Lcfi6:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
@@ -201,6 +207,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpbroadcastq %xmm0, %xmm0 {%k1} {z}
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi7:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_maskz_broadcastq_epi64:
@@ -236,7 +244,7 @@
 ; X32-LABEL: test_mm256_mask_broadcastq_epi64:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi4:
+; X32-NEXT:  .Lcfi8:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -245,6 +253,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpbroadcastq %xmm1, %ymm0 {%k1}
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi9:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_mask_broadcastq_epi64:
@@ -266,7 +276,7 @@
 ; X32-LABEL: test_mm256_maskz_broadcastq_epi64:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi5:
+; X32-NEXT:  .Lcfi10:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -275,6 +285,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpbroadcastq %xmm0, %ymm0 {%k1} {z}
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi11:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_maskz_broadcastq_epi64:
@@ -310,7 +322,7 @@
 ; X32-LABEL: test_mm_mask_broadcastsd_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi6:
+; X32-NEXT:  .Lcfi12:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
@@ -319,6 +331,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovddup {{.*#+}} xmm0 {%k1} = xmm1[0,0]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi13:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_mask_broadcastsd_pd:
@@ -340,7 +354,7 @@
 ; X32-LABEL: test_mm_maskz_broadcastsd_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi7:
+; X32-NEXT:  .Lcfi14:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
@@ -349,6 +363,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovddup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi15:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_maskz_broadcastsd_pd:
@@ -384,7 +400,7 @@
 ; X32-LABEL: test_mm256_mask_broadcastsd_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi8:
+; X32-NEXT:  .Lcfi16:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -393,6 +409,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vbroadcastsd %xmm1, %ymm0 {%k1}
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi17:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_mask_broadcastsd_pd:
@@ -414,7 +432,7 @@
 ; X32-LABEL: test_mm256_maskz_broadcastsd_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi9:
+; X32-NEXT:  .Lcfi18:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -423,6 +441,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vbroadcastsd %xmm0, %ymm0 {%k1} {z}
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi19:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_maskz_broadcastsd_pd:
@@ -458,7 +478,7 @@
 ; X32-LABEL: test_mm_mask_broadcastss_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi10:
+; X32-NEXT:  .Lcfi20:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -467,6 +487,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vbroadcastss %xmm1, %xmm0 {%k1}
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi21:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_mask_broadcastss_ps:
@@ -488,7 +510,7 @@
 ; X32-LABEL: test_mm_maskz_broadcastss_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi11:
+; X32-NEXT:  .Lcfi22:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -497,6 +519,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vbroadcastss %xmm0, %xmm0 {%k1} {z}
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi23:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_maskz_broadcastss_ps:
@@ -584,7 +608,7 @@
 ; X32-LABEL: test_mm_mask_movddup_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi12:
+; X32-NEXT:  .Lcfi24:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
@@ -593,6 +617,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovddup {{.*#+}} xmm0 {%k1} = xmm1[0,0]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi25:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_mask_movddup_pd:
@@ -614,7 +640,7 @@
 ; X32-LABEL: test_mm_maskz_movddup_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi13:
+; X32-NEXT:  .Lcfi26:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
@@ -623,6 +649,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovddup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi27:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_maskz_movddup_pd:
@@ -658,7 +686,7 @@
 ; X32-LABEL: test_mm256_mask_movddup_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi14:
+; X32-NEXT:  .Lcfi28:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -667,6 +695,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovddup {{.*#+}} ymm0 {%k1} = ymm1[0,0,2,2]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi29:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_mask_movddup_pd:
@@ -688,7 +718,7 @@
 ; X32-LABEL: test_mm256_maskz_movddup_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi15:
+; X32-NEXT:  .Lcfi30:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -697,6 +727,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovddup {{.*#+}} ymm0 {%k1} {z} = ymm0[0,0,2,2]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi31:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_maskz_movddup_pd:
@@ -732,7 +764,7 @@
 ; X32-LABEL: test_mm_mask_movehdup_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi16:
+; X32-NEXT:  .Lcfi32:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -741,6 +773,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovshdup {{.*#+}} xmm0 {%k1} = xmm1[1,1,3,3]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi33:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_mask_movehdup_ps:
@@ -762,7 +796,7 @@
 ; X32-LABEL: test_mm_maskz_movehdup_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi17:
+; X32-NEXT:  .Lcfi34:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -771,6 +805,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovshdup {{.*#+}} xmm0 {%k1} {z} = xmm0[1,1,3,3]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi35:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_maskz_movehdup_ps:
@@ -858,7 +894,7 @@
 ; X32-LABEL: test_mm_mask_moveldup_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi18:
+; X32-NEXT:  .Lcfi36:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -867,6 +903,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovsldup {{.*#+}} xmm0 {%k1} = xmm1[0,0,2,2]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi37:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_mask_moveldup_ps:
@@ -888,7 +926,7 @@
 ; X32-LABEL: test_mm_maskz_moveldup_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi19:
+; X32-NEXT:  .Lcfi38:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -897,6 +935,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vmovsldup {{.*#+}} xmm0 {%k1} {z} = xmm0[0,0,2,2]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi39:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_maskz_moveldup_ps:
@@ -984,7 +1024,7 @@
 ; X32-LABEL: test_mm256_mask_permutex_epi64:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi20:
+; X32-NEXT:  .Lcfi40:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -993,6 +1033,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpermq {{.*#+}} ymm0 {%k1} = ymm1[1,0,0,0]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi41:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_mask_permutex_epi64:
@@ -1014,7 +1056,7 @@
 ; X32-LABEL: test_mm256_maskz_permutex_epi64:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi21:
+; X32-NEXT:  .Lcfi42:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -1023,6 +1065,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpermq {{.*#+}} ymm0 {%k1} {z} = ymm0[1,0,0,0]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi43:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_maskz_permutex_epi64:
@@ -1058,7 +1102,7 @@
 ; X32-LABEL: test_mm256_mask_permutex_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi22:
+; X32-NEXT:  .Lcfi44:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -1067,6 +1111,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpermpd {{.*#+}} ymm0 {%k1} = ymm1[1,0,0,0]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi45:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_mask_permutex_pd:
@@ -1088,7 +1134,7 @@
 ; X32-LABEL: test_mm256_maskz_permutex_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi23:
+; X32-NEXT:  .Lcfi46:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -1097,6 +1143,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vpermpd {{.*#+}} ymm0 {%k1} {z} = ymm0[1,0,0,0]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi47:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_maskz_permutex_pd:
@@ -1132,7 +1180,7 @@
 ; X32-LABEL: test_mm_mask_shuffle_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi24:
+; X32-NEXT:  .Lcfi48:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
@@ -1141,6 +1189,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vunpckhpd {{.*#+}} xmm0 {%k1} = xmm1[1],xmm2[1]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi49:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_mask_shuffle_pd:
@@ -1162,7 +1212,7 @@
 ; X32-LABEL: test_mm_maskz_shuffle_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi25:
+; X32-NEXT:  .Lcfi50:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $3, %al
@@ -1171,6 +1221,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vunpckhpd {{.*#+}} xmm0 {%k1} {z} = xmm0[1],xmm1[1]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi51:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_maskz_shuffle_pd:
@@ -1206,7 +1258,7 @@
 ; X32-LABEL: test_mm256_mask_shuffle_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi26:
+; X32-NEXT:  .Lcfi52:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -1215,6 +1267,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vshufpd {{.*#+}} ymm0 {%k1} = ymm1[1],ymm2[1],ymm1[2],ymm2[2]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi53:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_mask_shuffle_pd:
@@ -1236,7 +1290,7 @@
 ; X32-LABEL: test_mm256_maskz_shuffle_pd:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi27:
+; X32-NEXT:  .Lcfi54:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -1245,6 +1299,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vshufpd {{.*#+}} ymm0 {%k1} {z} = ymm0[1],ymm1[1],ymm0[2],ymm1[2]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi55:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm256_maskz_shuffle_pd:
@@ -1280,7 +1336,7 @@
 ; X32-LABEL: test_mm_mask_shuffle_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi28:
+; X32-NEXT:  .Lcfi56:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -1289,6 +1345,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vshufps {{.*#+}} xmm0 {%k1} = xmm1[0,1],xmm2[0,0]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi57:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_mask_shuffle_ps:
@@ -1310,7 +1368,7 @@
 ; X32-LABEL: test_mm_maskz_shuffle_ps:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:  .Lcfi29:
+; X32-NEXT:  .Lcfi58:
 ; X32-NEXT:    .cfi_def_cfa_offset 8
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    andb $15, %al
@@ -1319,6 +1377,8 @@
 ; X32-NEXT:    kmovw %eax, %k1
 ; X32-NEXT:    vshufps {{.*#+}} xmm0 {%k1} {z} = xmm0[0,1],xmm1[0,0]
 ; X32-NEXT:    popl %eax
+; X32-NEXT:  .Lcfi59:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_maskz_shuffle_ps:
Index: test/CodeGen/X86/avx512vl-vbroadcast.ll
===================================================================
--- test/CodeGen/X86/avx512vl-vbroadcast.ll
+++ test/CodeGen/X86/avx512vl-vbroadcast.ll
@@ -13,6 +13,8 @@
 ; CHECK-NEXT:    callq func_f32
 ; CHECK-NEXT:    vbroadcastss (%rsp), %ymm0 # 16-byte Folded Reload
 ; CHECK-NEXT:    addq $24, %rsp
+; CHECK-NEXT:  .Lcfi1:
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
   %a  = fadd float %x, %x
   call void @func_f32(float %a)
@@ -25,13 +27,15 @@
 ; CHECK-LABEL: _128_broadcast_ss_spill:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    subq $24, %rsp
-; CHECK-NEXT:  .Lcfi1:
+; CHECK-NEXT:  .Lcfi2:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    vaddss %xmm0, %xmm0, %xmm0
 ; CHECK-NEXT:    vmovaps %xmm0, (%rsp) # 16-byte Spill
 ; CHECK-NEXT:    callq func_f32
 ; CHECK-NEXT:    vbroadcastss (%rsp), %xmm0 # 16-byte Folded Reload
 ; CHECK-NEXT:    addq $24, %rsp
+; CHECK-NEXT:  .Lcfi3:
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
   %a  = fadd float %x, %x
   call void @func_f32(float %a)
@@ -45,13 +49,15 @@
 ; CHECK-LABEL: _256_broadcast_sd_spill:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    subq $24, %rsp
-; CHECK-NEXT:  .Lcfi2:
+; CHECK-NEXT:  .Lcfi4:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    vaddsd %xmm0, %xmm0, %xmm0
 ; CHECK-NEXT:    vmovapd %xmm0, (%rsp) # 16-byte Spill
 ; CHECK-NEXT:    callq func_f64
 ; CHECK-NEXT:    vbroadcastsd (%rsp), %ymm0 # 16-byte Folded Reload
 ; CHECK-NEXT:    addq $24, %rsp
+; CHECK-NEXT:  .Lcfi5:
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
   %a  = fadd double %x, %x
   call void @func_f64(double %a)
Index: test/CodeGen/X86/block-placement.ll
===================================================================
--- test/CodeGen/X86/block-placement.ll
+++ test/CodeGen/X86/block-placement.ll
@@ -476,12 +476,12 @@
 ; CHECK-LABEL: fpcmp_unanalyzable_branch:
 ; CHECK:       # BB#0: # %entry
 ; CHECK:       # BB#1: # %entry.if.then_crit_edge
-; CHECK:       .LBB10_5: # %if.then
-; CHECK:       .LBB10_6: # %if.end
-; CHECK:       # BB#3: # %exit
-; CHECK:       jne .LBB10_4
-; CHECK-NEXT:  jnp .LBB10_6
-; CHECK:       jmp .LBB10_5
+; CHECK:       .LBB10_2: # %if.then
+; CHECK:       .LBB10_3: # %if.end
+; CHECK:       # BB#5: # %exit
+; CHECK:       jne .LBB10_6
+; CHECK-NEXT:  jnp .LBB10_3
+; CHECK:       jmp .LBB10_2
 
 entry:
 ; Note that this branch must be strongly biased toward
Index: test/CodeGen/X86/bmi-intrinsics-fast-isel.ll
===================================================================
--- test/CodeGen/X86/bmi-intrinsics-fast-isel.ll
+++ test/CodeGen/X86/bmi-intrinsics-fast-isel.ll
@@ -14,11 +14,11 @@
 ; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movzwl %ax, %ecx
 ; X32-NEXT:    cmpl $0, %ecx
-; X32-NEXT:    jne .LBB0_1
-; X32-NEXT:  # BB#2:
+; X32-NEXT:    jne .LBB0_2
+; X32-NEXT:  # BB#1:
 ; X32-NEXT:    movw $16, %ax
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB0_1:
+; X32-NEXT:  .LBB0_2:
 ; X32-NEXT:    tzcntw %ax, %ax
 ; X32-NEXT:    retl
 ;
@@ -136,11 +136,11 @@
 ; X32:       # BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    cmpl $0, %eax
-; X32-NEXT:    jne .LBB6_1
-; X32-NEXT:  # BB#2:
+; X32-NEXT:    jne .LBB6_2
+; X32-NEXT:  # BB#1:
 ; X32-NEXT:    movl $32, %eax
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB6_1:
+; X32-NEXT:  .LBB6_2:
 ; X32-NEXT:    tzcntl %eax, %eax
 ; X32-NEXT:    retl
 ;
@@ -166,11 +166,11 @@
 ; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movzwl %ax, %ecx
 ; X32-NEXT:    cmpl $0, %ecx
-; X32-NEXT:    jne .LBB7_1
-; X32-NEXT:  # BB#2:
+; X32-NEXT:    jne .LBB7_2
+; X32-NEXT:  # BB#1:
 ; X32-NEXT:    movw $16, %ax
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB7_1:
+; X32-NEXT:  .LBB7_2:
 ; X32-NEXT:    tzcntw %ax, %ax
 ; X32-NEXT:    retl
 ;
@@ -301,11 +301,11 @@
 ; X32:       # BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    cmpl $0, %eax
-; X32-NEXT:    jne .LBB13_1
-; X32-NEXT:  # BB#2:
+; X32-NEXT:    jne .LBB13_2
+; X32-NEXT:  # BB#1:
 ; X32-NEXT:    movl $32, %eax
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB13_1:
+; X32-NEXT:  .LBB13_2:
 ; X32-NEXT:    tzcntl %eax, %eax
 ; X32-NEXT:    retl
 ;
Index: test/CodeGen/X86/clz.ll
===================================================================
--- test/CodeGen/X86/clz.ll
+++ test/CodeGen/X86/clz.ll
@@ -99,13 +99,13 @@
 ; X32:       # BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    testl %eax, %eax
-; X32-NEXT:    jne .LBB3_1
-; X32-NEXT:  # BB#2:
+; X32-NEXT:    jne .LBB3_2
+; X32-NEXT:  # BB#1:
 ; X32-NEXT:    bsfl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    addl $32, %eax
 ; X32-NEXT:    xorl %edx, %edx
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB3_1:
+; X32-NEXT:  .LBB3_2:
 ; X32-NEXT:    bsfl %eax, %eax
 ; X32-NEXT:    xorl %edx, %edx
 ; X32-NEXT:    retl
@@ -119,13 +119,13 @@
 ; X32-CLZ:       # BB#0:
 ; X32-CLZ-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-CLZ-NEXT:    testl %eax, %eax
-; X32-CLZ-NEXT:    jne .LBB3_1
-; X32-CLZ-NEXT:  # BB#2:
+; X32-CLZ-NEXT:    jne .LBB3_2
+; X32-CLZ-NEXT:  # BB#1:
 ; X32-CLZ-NEXT:    tzcntl {{[0-9]+}}(%esp), %eax
 ; X32-CLZ-NEXT:    addl $32, %eax
 ; X32-CLZ-NEXT:    xorl %edx, %edx
 ; X32-CLZ-NEXT:    retl
-; X32-CLZ-NEXT:  .LBB3_1:
+; X32-CLZ-NEXT:  .LBB3_2:
 ; X32-CLZ-NEXT:    tzcntl %eax, %eax
 ; X32-CLZ-NEXT:    xorl %edx, %edx
 ; X32-CLZ-NEXT:    retl
@@ -233,14 +233,14 @@
 ; X32:       # BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    testl %eax, %eax
-; X32-NEXT:    jne .LBB7_1
-; X32-NEXT:  # BB#2:
+; X32-NEXT:    jne .LBB7_2
+; X32-NEXT:  # BB#1:
 ; X32-NEXT:    bsrl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    xorl $31, %eax
 ; X32-NEXT:    addl $32, %eax
 ; X32-NEXT:    xorl %edx, %edx
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB7_1:
+; X32-NEXT:  .LBB7_2:
 ; X32-NEXT:    bsrl %eax, %eax
 ; X32-NEXT:    xorl $31, %eax
 ; X32-NEXT:    xorl %edx, %edx
@@ -256,13 +256,13 @@
 ; X32-CLZ:       # BB#0:
 ; X32-CLZ-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-CLZ-NEXT:    testl %eax, %eax
-; X32-CLZ-NEXT:    jne .LBB7_1
-; X32-CLZ-NEXT:  # BB#2:
+; X32-CLZ-NEXT:    jne .LBB7_2
+; X32-CLZ-NEXT:  # BB#1:
 ; X32-CLZ-NEXT:    lzcntl {{[0-9]+}}(%esp), %eax
 ; X32-CLZ-NEXT:    addl $32, %eax
 ; X32-CLZ-NEXT:    xorl %edx, %edx
 ; X32-CLZ-NEXT:    retl
-; X32-CLZ-NEXT:  .LBB7_1:
+; X32-CLZ-NEXT:  .LBB7_2:
 ; X32-CLZ-NEXT:    lzcntl %eax, %eax
 ; X32-CLZ-NEXT:    xorl %edx, %edx
 ; X32-CLZ-NEXT:    retl
@@ -281,14 +281,14 @@
 ; X32:       # BB#0:
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    testb %al, %al
-; X32-NEXT:    je .LBB8_1
-; X32-NEXT:  # BB#2: # %cond.false
+; X32-NEXT:    je .LBB8_2
+; X32-NEXT:  # BB#1: # %cond.false
 ; X32-NEXT:    movzbl %al, %eax
 ; X32-NEXT:    bsrl %eax, %eax
 ; X32-NEXT:    xorl $7, %eax
 ; X32-NEXT:    # kill: %AL<def> %AL<kill> %EAX<kill>
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB8_1:
+; X32-NEXT:  .LBB8_2:
 ; X32-NEXT:    movb    $8, %al
 ; X32-NEXT:    # kill: %AL<def> %AL<kill> %EAX<kill>
 ; X32-NEXT:    retl
@@ -296,14 +296,14 @@
 ; X64-LABEL: ctlz_i8_zero_test:
 ; X64:       # BB#0:
 ; X64-NEXT:    testb %dil, %dil
-; X64-NEXT:    je .LBB8_1
-; X64-NEXT:  # BB#2: # %cond.false
+; X64-NEXT:    je .LBB8_2
+; X64-NEXT:  # BB#1: # %cond.false
 ; X64-NEXT:    movzbl %dil, %eax
 ; X64-NEXT:    bsrl %eax, %eax
 ; X64-NEXT:    xorl $7, %eax
 ; X64-NEXT:    # kill: %AL<def> %AL<kill> %EAX<kill>
 ; X64-NEXT:    retq
-; X64-NEXT:  .LBB8_1:
+; X64-NEXT:  .LBB8_2:
 ; X64-NEXT:    movb    $8, %al
 ; X64-NEXT:    # kill: %AL<def> %AL<kill> %EAX<kill>
 ; X64-NEXT:    retq
@@ -333,13 +333,13 @@
 ; X32:       # BB#0:
 ; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    testw %ax, %ax
-; X32-NEXT:    je .LBB9_1
-; X32-NEXT:  # BB#2: # %cond.false
+; X32-NEXT:    je .LBB9_2
+; X32-NEXT:  # BB#1: # %cond.false
 ; X32-NEXT:    bsrw %ax, %ax
 ; X32-NEXT:    xorl $15, %eax
 ; X32-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB9_1:
+; X32-NEXT:  .LBB9_2:
 ; X32-NEXT:    movw    $16, %ax
 ; X32-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; X32-NEXT:    retl
@@ -347,13 +347,13 @@
 ; X64-LABEL: ctlz_i16_zero_test:
 ; X64:       # BB#0:
 ; X64-NEXT:    testw %di, %di
-; X64-NEXT:    je .LBB9_1
-; X64-NEXT:  # BB#2: # %cond.false
+; X64-NEXT:    je .LBB9_2
+; X64-NEXT:  # BB#1: # %cond.false
 ; X64-NEXT:    bsrw %di, %ax
 ; X64-NEXT:    xorl $15, %eax
 ; X64-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; X64-NEXT:    retq
-; X64-NEXT:  .LBB9_1:
+; X64-NEXT:  .LBB9_2:
 ; X64-NEXT:    movw $16, %ax
 ; X64-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
 ; X64-NEXT:    retq
@@ -377,24 +377,24 @@
 ; X32:       # BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    testl %eax, %eax
-; X32-NEXT:    je .LBB10_1
-; X32-NEXT:  # BB#2: # %cond.false
+; X32-NEXT:    je .LBB10_2
+; X32-NEXT:  # BB#1: # %cond.false
 ; X32-NEXT:    bsrl %eax, %eax
 ; X32-NEXT:    xorl $31, %eax
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB10_1:
+; X32-NEXT:  .LBB10_2:
 ; X32-NEXT:    movl    $32, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: ctlz_i32_zero_test:
 ; X64:       # BB#0:
 ; X64-NEXT:    testl %edi, %edi
-; X64-NEXT:    je .LBB10_1
-; X64-NEXT:  # BB#2: # %cond.false
+; X64-NEXT:    je .LBB10_2
+; X64-NEXT:  # BB#1: # %cond.false
 ; X64-NEXT:    bsrl %edi, %eax
 ; X64-NEXT:    xorl $31, %eax
 ; X64-NEXT:    retq
-; X64-NEXT:  .LBB10_1:
+; X64-NEXT:  .LBB10_2:
 ; X64-NEXT:    movl $32, %eax
 ; X64-NEXT:    retq
 ;
@@ -423,13 +423,13 @@
 ; X32-NEXT:    movl %edx, %eax
 ; X32-NEXT:  .LBB11_2:
 ; X32-NEXT:    testl %ecx, %ecx
-; X32-NEXT:    jne .LBB11_3
-; X32-NEXT:  # BB#4:
+; X32-NEXT:    jne .LBB11_4
+; X32-NEXT:  # BB#3:
 ; X32-NEXT:    xorl $31, %eax
 ; X32-NEXT:    addl $32, %eax
 ; X32-NEXT:    xorl %edx, %edx
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB11_3:
+; X32-NEXT:  .LBB11_4:
 ; X32-NEXT:    bsrl %ecx, %eax
 ; X32-NEXT:    xorl $31, %eax
 ; X32-NEXT:    xorl %edx, %edx
@@ -438,12 +438,12 @@
 ; X64-LABEL: ctlz_i64_zero_test:
 ; X64:       # BB#0:
 ; X64-NEXT:    testq %rdi, %rdi
-; X64-NEXT:    je .LBB11_1
-; X64-NEXT:  # BB#2: # %cond.false
+; X64-NEXT:    je .LBB11_2
+; X64-NEXT:  # BB#1: # %cond.false
 ; X64-NEXT:    bsrq %rdi, %rax
 ; X64-NEXT:    xorq $63, %rax
 ; X64-NEXT:    retq
-; X64-NEXT:  .LBB11_1:
+; X64-NEXT:  .LBB11_2:
 ; X64-NEXT:    movl $64, %eax
 ; X64-NEXT:    retq
 ;
@@ -451,13 +451,13 @@
 ; X32-CLZ:       # BB#0:
 ; X32-CLZ-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-CLZ-NEXT:    testl %eax, %eax
-; X32-CLZ-NEXT:    jne .LBB11_1
-; X32-CLZ-NEXT:  # BB#2:
+; X32-CLZ-NEXT:    jne .LBB11_2
+; X32-CLZ-NEXT:  # BB#1:
 ; X32-CLZ-NEXT:    lzcntl {{[0-9]+}}(%esp), %eax
 ; X32-CLZ-NEXT:    addl $32, %eax
 ; X32-CLZ-NEXT:    xorl %edx, %edx
 ; X32-CLZ-NEXT:    retl
-; X32-CLZ-NEXT:  .LBB11_1:
+; X32-CLZ-NEXT:  .LBB11_2:
 ; X32-CLZ-NEXT:    lzcntl %eax, %eax
 ; X32-CLZ-NEXT:    xorl %edx, %edx
 ; X32-CLZ-NEXT:    retl
@@ -476,13 +476,13 @@
 ; X32:       # BB#0:
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
 ; X32-NEXT:    testb %al, %al
-; X32-NEXT:    je .LBB12_1
-; X32-NEXT:  # BB#2: # %cond.false
+; X32-NEXT:    je .LBB12_2
+; X32-NEXT:  # BB#1: # %cond.false
 ; X32-NEXT:    movzbl %al, %eax
 ; X32-NEXT:    bsfl %eax, %eax
 ; X32-NEXT:    # kill: %AL<def> %AL<kill> %EAX<kill>
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB12_1
+; X32-NEXT:  .LBB12_2
 ; X32-NEXT:    movb $8, %al
 ; X32-NEXT:    # kill: %AL<def> %AL<kill> %EAX<kill>
 ; X32-NEXT:    retl
@@ -490,13 +490,13 @@
 ; X64-LABEL: cttz_i8_zero_test:
 ; X64:       # BB#0:
 ; X64-NEXT:    testb %dil, %dil
-; X64-NEXT:    je .LBB12_1
-; X64-NEXT:  # BB#2: # %cond.false
+; X64-NEXT:    je .LBB12_2
+; X64-NEXT:  # BB#1: # %cond.false
 ; X64-NEXT:    movzbl %dil, %eax
 ; X64-NEXT:    bsfl %eax, %eax
 ; X64-NEXT:    # kill: %AL<def> %AL<kill> %EAX<kill>
 ; X64-NEXT:    retq
-; X64-NEXT:  .LBB12_1:
+; X64-NEXT:  .LBB12_2:
 ; X64-NEXT:    movb $8, %al
 ; X64-NEXT:    # kill: %AL<def> %AL<kill> %EAX<kill>
 ; X64-NEXT:    retq
@@ -526,22 +526,22 @@
 ; X32:       # BB#0:
 ; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    testw %ax, %ax
-; X32-NEXT:    je .LBB13_1
-; X32-NEXT:  # BB#2: # %cond.false
+; X32-NEXT:    je .LBB13_2
+; X32-NEXT:  # BB#1: # %cond.false
 ; X32-NEXT:    bsfw %ax, %ax
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB13_1
+; X32-NEXT:  .LBB13_2
 ; X32-NEXT:    movw $16, %ax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: cttz_i16_zero_test:
 ; X64:       # BB#0:
 ; X64-NEXT:    testw %di, %di
-; X64-NEXT:    je .LBB13_1
-; X64-NEXT:  # BB#2: # %cond.false
+; X64-NEXT:    je .LBB13_2
+; X64-NEXT:  # BB#1: # %cond.false
 ; X64-NEXT:    bsfw %di, %ax
 ; X64-NEXT:    retq
-; X64-NEXT:  .LBB13_1:
+; X64-NEXT:  .LBB13_2:
 ; X64-NEXT:    movw $16, %ax
 ; X64-NEXT:    retq
 ;
@@ -564,22 +564,22 @@
 ; X32:       # BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    testl %eax, %eax
-; X32-NEXT:    je .LBB14_1
-; X32-NEXT:  # BB#2: # %cond.false
+; X32-NEXT:    je .LBB14_2
+; X32-NEXT:  # BB#1: # %cond.false
 ; X32-NEXT:    bsfl %eax, %eax
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB14_1
+; X32-NEXT:  .LBB14_2
 ; X32-NEXT:    movl $32, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: cttz_i32_zero_test:
 ; X64:       # BB#0:
 ; X64-NEXT:    testl %edi, %edi
-; X64-NEXT:    je .LBB14_1
-; X64-NEXT:  # BB#2: # %cond.false
+; X64-NEXT:    je .LBB14_2
+; X64-NEXT:  # BB#1: # %cond.false
 ; X64-NEXT:    bsfl %edi, %eax
 ; X64-NEXT:    retq
-; X64-NEXT:  .LBB14_1:
+; X64-NEXT:  .LBB14_2:
 ; X64-NEXT:    movl $32, %eax
 ; X64-NEXT:    retq
 ;
@@ -608,12 +608,12 @@
 ; X32-NEXT:    movl %edx, %eax
 ; X32-NEXT:  .LBB15_2:
 ; X32-NEXT:    testl %ecx, %ecx
-; X32-NEXT:    jne .LBB15_3
-; X32-NEXT:  # BB#4:
+; X32-NEXT:    jne .LBB15_4
+; X32-NEXT:  # BB#3:
 ; X32-NEXT:    addl $32, %eax
 ; X32-NEXT:    xorl %edx, %edx
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB15_3:
+; X32-NEXT:  .LBB15_4:
 ; X32-NEXT:    bsfl %ecx, %eax
 ; X32-NEXT:    xorl %edx, %edx
 ; X32-NEXT:    retl
@@ -621,11 +621,11 @@
 ; X64-LABEL: cttz_i64_zero_test:
 ; X64:       # BB#0:
 ; X64-NEXT:    testq %rdi, %rdi
-; X64-NEXT:    je .LBB15_1
-; X64-NEXT:  # BB#2: # %cond.false
+; X64-NEXT:    je .LBB15_2
+; X64-NEXT:  # BB#1: # %cond.false
 ; X64-NEXT:    bsfq %rdi, %rax
 ; X64-NEXT:    retq
-; X64-NEXT:  .LBB15_1:
+; X64-NEXT:  .LBB15_2:
 ; X64-NEXT:    movl $64, %eax
 ; X64-NEXT:    retq
 ;
@@ -633,13 +633,13 @@
 ; X32-CLZ:       # BB#0:
 ; X32-CLZ-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-CLZ-NEXT:    testl %eax, %eax
-; X32-CLZ-NEXT:    jne .LBB15_1
-; X32-CLZ-NEXT:  # BB#2:
+; X32-CLZ-NEXT:    jne .LBB15_2
+; X32-CLZ-NEXT:  # BB#1:
 ; X32-CLZ-NEXT:    tzcntl {{[0-9]+}}(%esp), %eax
 ; X32-CLZ-NEXT:    addl $32, %eax
 ; X32-CLZ-NEXT:    xorl %edx, %edx
 ; X32-CLZ-NEXT:    retl
-; X32-CLZ-NEXT:  .LBB15_1:
+; X32-CLZ-NEXT:  .LBB15_2:
 ; X32-CLZ-NEXT:    tzcntl %eax, %eax
 ; X32-CLZ-NEXT:    xorl %edx, %edx
 ; X32-CLZ-NEXT:    retl
@@ -662,24 +662,24 @@
 ; X32:       # BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    orl $1, %eax
-; X32-NEXT:    je .LBB16_1
-; X32-NEXT:  # BB#2: # %cond.false
+; X32-NEXT:    je .LBB16_2
+; X32-NEXT:  # BB#1: # %cond.false
 ; X32-NEXT:    bsrl %eax, %eax
 ; X32-NEXT:    xorl $31, %eax
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB16_1
+; X32-NEXT:  .LBB16_2
 ; X32-NEXT:    movl $32, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: ctlz_i32_fold_cmov:
 ; X64:       # BB#0:
 ; X64-NEXT:    orl $1, %edi
-; X64-NEXT:    je .LBB16_1
-; X64-NEXT:  # BB#2: # %cond.false
+; X64-NEXT:    je .LBB16_2
+; X64-NEXT:  # BB#1: # %cond.false
 ; X64-NEXT:    bsrl %edi, %eax
 ; X64-NEXT:    xorl $31, %eax
 ; X64-NEXT:    retq
-; X64-NEXT:  .LBB16_1:
+; X64-NEXT:  .LBB16_2:
 ; X64-NEXT:    movl $32, %eax
 ; X64-NEXT:    retq
 ;
@@ -738,13 +738,13 @@
 ; X32:       # BB#0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    testl %eax, %eax
-; X32-NEXT:    je .LBB18_1
-; X32-NEXT:  # BB#2: # %cond.false
+; X32-NEXT:    je .LBB18_2
+; X32-NEXT:  # BB#1: # %cond.false
 ; X32-NEXT:    bsrl %eax, %eax
 ; X32-NEXT:    xorl $31, %eax
 ; X32-NEXT:    xorl $31, %eax
 ; X32-NEXT:    retl
-; X32-NEXT:  .LBB18_1:
+; X32-NEXT:  .LBB18_2:
 ; X32-NEXT:    movl $32, %eax
 ; X32-NEXT:    xorl $31, %eax
 ; X32-NEXT:    retl
@@ -752,13 +752,13 @@
 ; X64-LABEL: ctlz_bsr_zero_test:
 ; X64:       # BB#0:
 ; X64-NEXT:    testl %edi, %edi
-; X64-NEXT:    je .LBB18_1
-; X64-NEXT:  # BB#2: # %cond.false
+; X64-NEXT:    je .LBB18_2
+; X64-NEXT:  # BB#1: # %cond.false
 ; X64-NEXT:    bsrl %edi, %eax
 ; X64-NEXT:    xorl $31, %eax
 ; X64-NEXT:    xorl $31, %eax
 ; X64-NEXT:    retq
-; X64-NEXT:  .LBB18_1:
+; X64-NEXT:  .LBB18_2:
 ; X64-NEXT:    movl $32, %eax
 ; X64-NEXT:    xorl $31, %eax
 ; X64-NEXT:    retq
Index: test/CodeGen/X86/conditional-tailcall.ll
===================================================================
--- test/CodeGen/X86/conditional-tailcall.ll
+++ test/CodeGen/X86/conditional-tailcall.ll
@@ -134,7 +134,7 @@
 
 ; Make sure Machine Copy Propagation doesn't delete the mov to %ecx becaue it
 ; thinks the conditional tail call clobbers it.
-; CHECK64-LABEL: .LBB3_11:
+; CHECK64-LABEL: .LBB3_9:
 ; CHECK64:       movzbl  (%rdi), %ecx
 ; CHECK64-NEXT:  addl    $-48, %ecx
 ; CHECK64-NEXT:  cmpl    $10, %ecx
Index: test/CodeGen/X86/emutls-pie.ll
===================================================================
--- test/CodeGen/X86/emutls-pie.ll
+++ test/CodeGen/X86/emutls-pie.ll
@@ -18,13 +18,19 @@
 ; X32-NEXT: calll my_emutls_get_address@PLT
 ; X32-NEXT: movl (%eax), %eax
 ; X32-NEXT: addl $8, %esp
+; X32-NEXT: .Lcfi5:
+; X32-NEXT: .cfi_def_cfa_offset 8
 ; X32-NEXT: popl %ebx
+; X32-NEXT: .Lcfi6:
+; X32-NEXT: .cfi_def_cfa_offset 4
 ; X32-NEXT: retl
 ; X64-LABEL: my_get_xyz:
 ; X64:      movq my_emutls_v_xyz@GOTPCREL(%rip), %rdi
 ; X64-NEXT: callq my_emutls_get_address@PLT
 ; X64-NEXT: movl (%rax), %eax
 ; X64-NEXT: popq %rcx
+; X64-NEXT: .Lcfi1:
+; X64-NEXT: .cfi_def_cfa_offset 8
 ; X64-NEXT: retq
 
 entry:
@@ -44,13 +50,19 @@
 ; X32-NEXT: calll __emutls_get_address@PLT
 ; X32-NEXT: movl (%eax), %eax
 ; X32-NEXT: addl $8, %esp
+; X32-NEXT: .Lcfi12:
+; X32-NEXT: .cfi_def_cfa_offset 8
 ; X32-NEXT: popl %ebx
+; X32-NEXT: .Lcfi13:
+; X32-NEXT: .cfi_def_cfa_offset 4
 ; X32-NEXT: retl
 ; X64-LABEL: f1:
 ; X64:      leaq __emutls_v.i(%rip), %rdi
 ; X64-NEXT: callq __emutls_get_address@PLT
 ; X64-NEXT: movl (%rax), %eax
 ; X64-NEXT: popq %rcx
+; X64-NEXT: .Lcfi3:
+; X64-NEXT: .cfi_def_cfa_offset 8
 ; X64-NEXT: retq
 
 entry:
Index: test/CodeGen/X86/emutls.ll
===================================================================
--- test/CodeGen/X86/emutls.ll
+++ test/CodeGen/X86/emutls.ll
@@ -16,12 +16,16 @@
 ; X32-NEXT:    calll my_emutls_get_address
 ; X32-NEXT:    movl (%eax), %eax
 ; X32-NEXT:    addl $12, %esp
+; X32-NEXT:  .Lcfi1:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ; X64-LABEL: my_get_xyz:
 ; X64:         movl $my_emutls_v_xyz, %edi
 ; X64-NEXT:    callq my_emutls_get_address
 ; X64-NEXT:    movl (%rax), %eax
 ; X64-NEXT:    popq %rcx
+; X64-NEXT:  .Lcfi1:
+; X64-NEXT:    .cfi_def_cfa_offset 8
 ; X64-NEXT:    retq
 
 entry:
@@ -45,12 +49,16 @@
 ; X32-NEXT:    calll __emutls_get_address
 ; X32-NEXT:    movl (%eax), %eax
 ; X32-NEXT:    addl $12, %esp
+; X32-NEXT:  .Lcfi3:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ; X64-LABEL: f1:
 ; X64:         movl $__emutls_v.i1, %edi
 ; X64-NEXT:    callq __emutls_get_address
 ; X64-NEXT:    movl (%rax), %eax
 ; X64-NEXT:    popq %rcx
+; X64-NEXT:  .Lcfi3:
+; X64-NEXT:    .cfi_def_cfa_offset 8
 ; X64-NEXT:    retq
 
 entry:
@@ -63,11 +71,15 @@
 ; X32:         movl $__emutls_v.i1, (%esp)
 ; X32-NEXT:    calll __emutls_get_address
 ; X32-NEXT:    addl $12, %esp
+; X32-NEXT:  .Lcfi5:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 ; X64-LABEL: f2:
 ; X64:         movl $__emutls_v.i1, %edi
 ; X64-NEXT:    callq __emutls_get_address
 ; X64-NEXT:    popq %rcx
+; X64-NEXT:  .Lcfi5:
+; X64-NEXT:    .cfi_def_cfa_offset 8
 ; X64-NEXT:    retq
 
 entry:
@@ -92,6 +104,8 @@
 ; X32:         movl $__emutls_v.i2, (%esp)
 ; X32-NEXT:    calll __emutls_get_address
 ; X32-NEXT:    addl $12, %esp
+; X32-NEXT:  .Lcfi7:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 
 entry:
@@ -116,6 +130,8 @@
 ; X32:         movl $__emutls_v.i3, (%esp)
 ; X32-NEXT:    calll __emutls_get_address
 ; X32-NEXT:    addl $12, %esp
+; X32-NEXT:  .Lcfi9:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 
 entry:
@@ -128,6 +144,8 @@
 ; X32-NEXT:    calll __emutls_get_address
 ; X32-NEXT:    movl (%eax), %eax
 ; X32-NEXT:    addl $12, %esp
+; X32-NEXT:  .Lcfi11:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 
 entry:
@@ -140,6 +158,8 @@
 ; X32:         movl $__emutls_v.i4, (%esp)
 ; X32-NEXT:    calll __emutls_get_address
 ; X32-NEXT:    addl $12, %esp
+; X32-NEXT:  .Lcfi13:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 
 entry:
@@ -152,6 +172,8 @@
 ; X32-NEXT:    calll __emutls_get_address
 ; X32-NEXT:    movl (%eax), %eax
 ; X32-NEXT:    addl $12, %esp
+; X32-NEXT:  .Lcfi15:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 
 entry:
@@ -164,6 +186,8 @@
 ; X32:         movl $__emutls_v.i5, (%esp)
 ; X32-NEXT:    calll __emutls_get_address
 ; X32-NEXT:    addl $12, %esp
+; X32-NEXT:  .Lcfi17:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 
 entry:
@@ -176,6 +200,8 @@
 ; X32-NEXT:    calll __emutls_get_address
 ; X32-NEXT:    movzwl (%eax), %eax
 ; X32-NEXT:    addl $12, %esp
+; X32-NEXT:  .Lcfi19:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 
 entry:
@@ -189,6 +215,8 @@
 ; X32-NEXT:    calll __emutls_get_address
 ; X32-NEXT:    movswl (%eax), %eax
 ; X32-NEXT:    addl $12, %esp
+; X32-NEXT:  .Lcfi21:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 
 entry:
@@ -203,6 +231,8 @@
 ; X32-NEXT:    calll __emutls_get_address
 ; X32-NEXT:    movb (%eax), %al
 ; X32-NEXT:    addl $12, %esp
+; X32-NEXT:  .Lcfi23:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 
 entry:
@@ -216,6 +246,8 @@
 ; X32-NEXT:    calll __emutls_get_address
 ; X32-NEXT:    movsbl (%eax), %eax
 ; X32-NEXT:    addl $12, %esp
+; X32-NEXT:  .Lcfi25:
+; X32-NEXT:    .cfi_def_cfa_offset 4
 ; X32-NEXT:    retl
 
 entry:
Index: test/CodeGen/X86/fast-isel-store.ll
===================================================================
--- test/CodeGen/X86/fast-isel-store.ll
+++ test/CodeGen/X86/fast-isel-store.ll
@@ -376,6 +376,8 @@
 ; SSE64-NEXT:    movupd %xmm0, (%eax)
 ; SSE64-NEXT:    movupd %xmm1, 16(%eax)
 ; SSE64-NEXT:    addl $12, %esp
+; SSE64-NEXT:  .Lcfi1:
+; SSE64-NEXT:    .cfi_def_cfa_offset 4
 ; SSE64-NEXT:    retl
 ;
 ; AVX32-LABEL: test_store_4xf64:
@@ -407,7 +409,7 @@
 ; SSE64-LABEL: test_store_4xf64_aligned:
 ; SSE64:       # BB#0:
 ; SSE64-NEXT:    subl $12, %esp
-; SSE64-NEXT:  .Lcfi1:
+; SSE64-NEXT:  .Lcfi2:
 ; SSE64-NEXT:    .cfi_def_cfa_offset 16
 ; SSE64-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE64-NEXT:    addpd {{[0-9]+}}(%esp), %xmm1
@@ -415,6 +417,8 @@
 ; SSE64-NEXT:    movapd %xmm0, (%eax)
 ; SSE64-NEXT:    movapd %xmm1, 16(%eax)
 ; SSE64-NEXT:    addl $12, %esp
+; SSE64-NEXT:  .Lcfi3:
+; SSE64-NEXT:    .cfi_def_cfa_offset 4
 ; SSE64-NEXT:    retl
 ;
 ; AVX32-LABEL: test_store_4xf64_aligned:
@@ -446,7 +450,7 @@
 ; SSE64-LABEL: test_store_16xi32:
 ; SSE64:       # BB#0:
 ; SSE64-NEXT:    subl $12, %esp
-; SSE64-NEXT:  .Lcfi2:
+; SSE64-NEXT:  .Lcfi4:
 ; SSE64-NEXT:    .cfi_def_cfa_offset 16
 ; SSE64-NEXT:    movaps {{[0-9]+}}(%esp), %xmm3
 ; SSE64-NEXT:    movl {{[0-9]+}}(%esp), %eax
@@ -455,6 +459,8 @@
 ; SSE64-NEXT:    movups %xmm2, 32(%eax)
 ; SSE64-NEXT:    movups %xmm3, 48(%eax)
 ; SSE64-NEXT:    addl $12, %esp
+; SSE64-NEXT:  .Lcfi5:
+; SSE64-NEXT:    .cfi_def_cfa_offset 4
 ; SSE64-NEXT:    retl
 ;
 ; AVXONLY32-LABEL: test_store_16xi32:
@@ -496,7 +502,7 @@
 ; SSE64-LABEL: test_store_16xi32_aligned:
 ; SSE64:       # BB#0:
 ; SSE64-NEXT:    subl $12, %esp
-; SSE64-NEXT:  .Lcfi3:
+; SSE64-NEXT:  .Lcfi6:
 ; SSE64-NEXT:    .cfi_def_cfa_offset 16
 ; SSE64-NEXT:    movaps {{[0-9]+}}(%esp), %xmm3
 ; SSE64-NEXT:    movl {{[0-9]+}}(%esp), %eax
@@ -505,6 +511,8 @@
 ; SSE64-NEXT:    movaps %xmm2, 32(%eax)
 ; SSE64-NEXT:    movaps %xmm3, 48(%eax)
 ; SSE64-NEXT:    addl $12, %esp
+; SSE64-NEXT:  .Lcfi7:
+; SSE64-NEXT:    .cfi_def_cfa_offset 4
 ; SSE64-NEXT:    retl
 ;
 ; AVXONLY32-LABEL: test_store_16xi32_aligned:
@@ -546,7 +554,7 @@
 ; SSE64-LABEL: test_store_16xf32:
 ; SSE64:       # BB#0:
 ; SSE64-NEXT:    subl $12, %esp
-; SSE64-NEXT:  .Lcfi4:
+; SSE64-NEXT:  .Lcfi8:
 ; SSE64-NEXT:    .cfi_def_cfa_offset 16
 ; SSE64-NEXT:    movaps {{[0-9]+}}(%esp), %xmm3
 ; SSE64-NEXT:    movl {{[0-9]+}}(%esp), %eax
@@ -555,6 +563,8 @@
 ; SSE64-NEXT:    movups %xmm2, 32(%eax)
 ; SSE64-NEXT:    movups %xmm3, 48(%eax)
 ; SSE64-NEXT:    addl $12, %esp
+; SSE64-NEXT:  .Lcfi9:
+; SSE64-NEXT:    .cfi_def_cfa_offset 4
 ; SSE64-NEXT:    retl
 ;
 ; AVXONLY32-LABEL: test_store_16xf32:
@@ -596,7 +606,7 @@
 ; SSE64-LABEL: test_store_16xf32_aligned:
 ; SSE64:       # BB#0:
 ; SSE64-NEXT:    subl $12, %esp
-; SSE64-NEXT:  .Lcfi5:
+; SSE64-NEXT:  .Lcfi10:
 ; SSE64-NEXT:    .cfi_def_cfa_offset 16
 ; SSE64-NEXT:    movaps {{[0-9]+}}(%esp), %xmm3
 ; SSE64-NEXT:    movl {{[0-9]+}}(%esp), %eax
@@ -605,6 +615,8 @@
 ; SSE64-NEXT:    movaps %xmm2, 32(%eax)
 ; SSE64-NEXT:    movaps %xmm3, 48(%eax)
 ; SSE64-NEXT:    addl $12, %esp
+; SSE64-NEXT:  .Lcfi11:
+; SSE64-NEXT:    .cfi_def_cfa_offset 4
 ; SSE64-NEXT:    retl
 ;
 ; AVXONLY32-LABEL: test_store_16xf32_aligned:
@@ -650,7 +662,7 @@
 ; SSE64-LABEL: test_store_8xf64:
 ; SSE64:       # BB#0:
 ; SSE64-NEXT:    subl $12, %esp
-; SSE64-NEXT:  .Lcfi6:
+; SSE64-NEXT:  .Lcfi12:
 ; SSE64-NEXT:    .cfi_def_cfa_offset 16
 ; SSE64-NEXT:    movapd {{[0-9]+}}(%esp), %xmm3
 ; SSE64-NEXT:    movl {{[0-9]+}}(%esp), %eax
@@ -663,6 +675,8 @@
 ; SSE64-NEXT:    movupd %xmm2, 32(%eax)
 ; SSE64-NEXT:    movupd %xmm3, 48(%eax)
 ; SSE64-NEXT:    addl $12, %esp
+; SSE64-NEXT:  .Lcfi13:
+; SSE64-NEXT:    .cfi_def_cfa_offset 4
 ; SSE64-NEXT:    retl
 ;
 ; AVXONLY32-LABEL: test_store_8xf64:
@@ -692,6 +706,8 @@
 ; AVXONLY64-NEXT:    vmovupd %ymm1, 32(%eax)
 ; AVXONLY64-NEXT:    movl %ebp, %esp
 ; AVXONLY64-NEXT:    popl %ebp
+; AVXONLY64-NEXT:  .Lcfi3:
+; AVXONLY64-NEXT:    .cfi_def_cfa %esp, 4
 ; AVXONLY64-NEXT:    retl
 ;
 ; AVX51232-LABEL: test_store_8xf64:
@@ -727,7 +743,7 @@
 ; SSE64-LABEL: test_store_8xf64_aligned:
 ; SSE64:       # BB#0:
 ; SSE64-NEXT:    subl $12, %esp
-; SSE64-NEXT:  .Lcfi7:
+; SSE64-NEXT:  .Lcfi14:
 ; SSE64-NEXT:    .cfi_def_cfa_offset 16
 ; SSE64-NEXT:    movapd {{[0-9]+}}(%esp), %xmm3
 ; SSE64-NEXT:    movl {{[0-9]+}}(%esp), %eax
@@ -740,6 +756,8 @@
 ; SSE64-NEXT:    movapd %xmm2, 32(%eax)
 ; SSE64-NEXT:    movapd %xmm3, 48(%eax)
 ; SSE64-NEXT:    addl $12, %esp
+; SSE64-NEXT:  .Lcfi15:
+; SSE64-NEXT:    .cfi_def_cfa_offset 4
 ; SSE64-NEXT:    retl
 ;
 ; AVXONLY32-LABEL: test_store_8xf64_aligned:
@@ -753,12 +771,12 @@
 ; AVXONLY64-LABEL: test_store_8xf64_aligned:
 ; AVXONLY64:       # BB#0:
 ; AVXONLY64-NEXT:    pushl %ebp
-; AVXONLY64-NEXT:  .Lcfi3:
-; AVXONLY64-NEXT:    .cfi_def_cfa_offset 8
 ; AVXONLY64-NEXT:  .Lcfi4:
+; AVXONLY64-NEXT:    .cfi_def_cfa_offset 8
+; AVXONLY64-NEXT:  .Lcfi5:
 ; AVXONLY64-NEXT:    .cfi_offset %ebp, -8
 ; AVXONLY64-NEXT:    movl %esp, %ebp
-; AVXONLY64-NEXT:  .Lcfi5:
+; AVXONLY64-NEXT:  .Lcfi6:
 ; AVXONLY64-NEXT:    .cfi_def_cfa_register %ebp
 ; AVXONLY64-NEXT:    andl $-32, %esp
 ; AVXONLY64-NEXT:    subl $32, %esp
@@ -769,6 +787,8 @@
 ; AVXONLY64-NEXT:    vmovapd %ymm1, 32(%eax)
 ; AVXONLY64-NEXT:    movl %ebp, %esp
 ; AVXONLY64-NEXT:    popl %ebp
+; AVXONLY64-NEXT:  .Lcfi7:
+; AVXONLY64-NEXT:    .cfi_def_cfa %esp, 4
 ; AVXONLY64-NEXT:    retl
 ;
 ; AVX51232-LABEL: test_store_8xf64_aligned:
Index: test/CodeGen/X86/fp-une-cmp.ll
===================================================================
--- test/CodeGen/X86/fp-une-cmp.ll
+++ test/CodeGen/X86/fp-une-cmp.ll
@@ -54,11 +54,11 @@
 ; CHECK-NEXT:    mulsd %xmm1, %xmm0
 ; CHECK-NEXT:    xorpd %xmm1, %xmm1
 ; CHECK-NEXT:    ucomisd %xmm1, %xmm0
-; CHECK-NEXT:    jne .LBB1_1
-; CHECK-NEXT:    jp .LBB1_1
+; CHECK-NEXT:    jne .LBB1_2
+; CHECK-NEXT:    jp .LBB1_2
 ; CHECK-NEXT:  # %bb2
 ; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB1_1: # %bb1
+; CHECK-NEXT:  .LBB1_2: # %bb1
 ; CHECK-NEXT:    addsd {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
 
@@ -84,11 +84,11 @@
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    xorps %xmm1, %xmm1
 ; CHECK-NEXT:    ucomiss %xmm1, %xmm0
-; CHECK-NEXT:    jne .LBB2_2
-; CHECK-NEXT:    jnp .LBB2_1
-; CHECK-NEXT:  .LBB2_2: # %if.then
+; CHECK-NEXT:    jne .LBB2_1
+; CHECK-NEXT:    jnp .LBB2_2
+; CHECK-NEXT:  .LBB2_1: # %if.then
 ; CHECK-NEXT:    jmp a # TAILCALL
-; CHECK-NEXT:  .LBB2_1: # %if.end
+; CHECK-NEXT:  .LBB2_2: # %if.end
 ; CHECK-NEXT:    retq
 entry:
   %cmp = fcmp une float %f, 0.000000e+00
@@ -104,7 +104,7 @@
 
 ; Test that an FP oeq/une conditional branch can be inverted successfully even
 ; when the true and false targets are the same (PR27750).
-; 
+;
 ; CHECK-LABEL: pr27750
 ; CHECK: ucomiss
 ; CHECK-NEXT: jne [[TARGET:.*]]
Index: test/CodeGen/X86/fp128-select.ll
===================================================================
--- test/CodeGen/X86/fp128-select.ll
+++ test/CodeGen/X86/fp128-select.ll
@@ -12,12 +12,12 @@
 ; MMX-LABEL: test_select:
 ; MMX:       # BB#0:
 ; MMX-NEXT:    testb %dl, %dl
-; MMX-NEXT:    jne .LBB0_1
-; MMX-NEXT:  # BB#2:
+; MMX-NEXT:    jne .LBB0_2
+; MMX-NEXT:  # BB#1:
 ; MMX-NEXT:    movaps {{.*}}(%rip), %xmm0
 ; MMX-NEXT:    movaps %xmm0, (%rsi)
 ; MMX-NEXT:    retq
-; MMX-NEXT:  .LBB0_1:
+; MMX-NEXT:  .LBB0_2:
 ; MMX-NEXT:    movaps (%rdi), %xmm0
 ; MMX-NEXT:    movaps %xmm0, (%rsi)
 ; MMX-NEXT:    retq
Index: test/CodeGen/X86/frame-lowering-debug-intrinsic-2.ll
===================================================================
--- test/CodeGen/X86/frame-lowering-debug-intrinsic-2.ll
+++ test/CodeGen/X86/frame-lowering-debug-intrinsic-2.ll
@@ -18,9 +18,14 @@
 }
 
 ; CHECK-LABEL: noDebug
-; CHECK:       addq  $24, %rsp
+; CHECK:       addq  $16, %rsp
+; CHECK:       addq  $8, %rsp
 ; CHECK:       popq  %rbx
+; CHECK-NEXT:  :
+; CHECK-NEXT:  .cfi_def_cfa_offset 16
 ; CHECK-NEXT:  popq  %r14
+; CHECK-NEXT:  :
+; CHECK-NEXT:  .cfi_def_cfa_offset 8
 ; CHECK-NEXT:  retq
 
 
@@ -41,9 +46,16 @@
 
 ; CHECK-LABEL: withDebug
 ; CHECK:       #DEBUG_VALUE: test:j <- %RBX
-; CHECK-NEXT:  addq  $24, %rsp
+; CHECK-NEXT:  addq  $16, %rsp
+; CHECK-NEXT:  :
+; CHECK-NEXT: .cfi_adjust_cfa_offset -16
+; CHECK-NEXT:  addq  $8, %rsp
 ; CHECK:       popq  %rbx
+; CHECK-NEXT:  :
+; CHECK-NEXT:  .cfi_def_cfa_offset 16
 ; CHECK-NEXT:  popq  %r14
+; CHECK-NEXT:  :
+; CHECK-NEXT:  .cfi_def_cfa_offset 8
 ; CHECK-NEXT:  retq
 
 declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64)
Index: test/CodeGen/X86/frame-lowering-debug-intrinsic.ll
===================================================================
--- test/CodeGen/X86/frame-lowering-debug-intrinsic.ll
+++ test/CodeGen/X86/frame-lowering-debug-intrinsic.ll
@@ -9,6 +9,8 @@
 
 ; CHECK-LABEL: fn1NoDebug
 ; CHECK: popq %rcx
+; CHECK-NEXT: .Lcfi1:
+; CHECK-NEXT: .cfi_def_cfa_offset 8
 ; CHECK-NEXT: ret
 
 define i64 @fn1WithDebug(i64 %a) !dbg !4 {
@@ -19,6 +21,8 @@
 
 ; CHECK-LABEL: fn1WithDebug
 ; CHECK: popq %rcx
+; CHECK-NEXT: .Lcfi3:
+; CHECK-NEXT:	.cfi_def_cfa_offset 8
 ; CHECK-NEXT: ret
 
 %struct.Buffer = type { i8, [63 x i8] }
@@ -33,6 +37,8 @@
 ; CHECK-NOT: sub
 ; CHECK: mov
 ; CHECK-NEXT: pop
+; CHECK-NEXT: .Lcfi7:
+; CHECK-NEXT:	.cfi_def_cfa %rsp, 8
 ; CHECK-NEXT: ret
 
 define void @fn2WithDebug(%struct.Buffer* byval align 64 %p1) !dbg !4 {
@@ -46,6 +52,8 @@
 ; CHECK-NOT: sub
 ; CHECK: mov
 ; CHECK-NEXT: pop
+; CHECK-NEXT: .Lcfi11:
+; CHECK-NEXT:	.cfi_def_cfa %rsp, 8
 ; CHECK-NEXT: ret
 
 declare i64 @fn(i64, i64)
Index: test/CodeGen/X86/haddsub-2.ll
===================================================================
--- test/CodeGen/X86/haddsub-2.ll
+++ test/CodeGen/X86/haddsub-2.ll
@@ -736,11 +736,23 @@
 ; SSE3-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
 ; SSE3-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm5[0],xmm1[1],xmm5[1],xmm1[2],xmm5[2],xmm1[3],xmm5[3]
 ; SSE3-NEXT:    popq %rbx
+; SSE3-NEXT:  .Lcfi12:
+; SSE3-NEXT:    .cfi_def_cfa_offset 48
 ; SSE3-NEXT:    popq %r12
+; SSE3-NEXT:  .Lcfi13:
+; SSE3-NEXT:    .cfi_def_cfa_offset 40
 ; SSE3-NEXT:    popq %r13
+; SSE3-NEXT:  .Lcfi14:
+; SSE3-NEXT:    .cfi_def_cfa_offset 32
 ; SSE3-NEXT:    popq %r14
+; SSE3-NEXT:  .Lcfi15:
+; SSE3-NEXT:    .cfi_def_cfa_offset 24
 ; SSE3-NEXT:    popq %r15
+; SSE3-NEXT:  .Lcfi16:
+; SSE3-NEXT:    .cfi_def_cfa_offset 16
 ; SSE3-NEXT:    popq %rbp
+; SSE3-NEXT:  .Lcfi17:
+; SSE3-NEXT:    .cfi_def_cfa_offset 8
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: avx2_vphadd_w_test:
@@ -1263,34 +1275,34 @@
 ; SSE3-LABEL: avx2_hadd_w:
 ; SSE3:       # BB#0:
 ; SSE3-NEXT:    pushq %rbp
-; SSE3-NEXT:  .Lcfi12:
+; SSE3-NEXT:  .Lcfi18:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 16
 ; SSE3-NEXT:    pushq %r15
-; SSE3-NEXT:  .Lcfi13:
+; SSE3-NEXT:  .Lcfi19:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 24
 ; SSE3-NEXT:    pushq %r14
-; SSE3-NEXT:  .Lcfi14:
+; SSE3-NEXT:  .Lcfi20:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 32
 ; SSE3-NEXT:    pushq %r13
-; SSE3-NEXT:  .Lcfi15:
+; SSE3-NEXT:  .Lcfi21:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 40
 ; SSE3-NEXT:    pushq %r12
-; SSE3-NEXT:  .Lcfi16:
+; SSE3-NEXT:  .Lcfi22:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 48
 ; SSE3-NEXT:    pushq %rbx
-; SSE3-NEXT:  .Lcfi17:
+; SSE3-NEXT:  .Lcfi23:
 ; SSE3-NEXT:    .cfi_def_cfa_offset 56
-; SSE3-NEXT:  .Lcfi18:
+; SSE3-NEXT:  .Lcfi24:
 ; SSE3-NEXT:    .cfi_offset %rbx, -56
-; SSE3-NEXT:  .Lcfi19:
+; SSE3-NEXT:  .Lcfi25:
 ; SSE3-NEXT:    .cfi_offset %r12, -48
-; SSE3-NEXT:  .Lcfi20:
+; SSE3-NEXT:  .Lcfi26:
 ; SSE3-NEXT:    .cfi_offset %r13, -40
-; SSE3-NEXT:  .Lcfi21:
+; SSE3-NEXT:  .Lcfi27:
 ; SSE3-NEXT:    .cfi_offset %r14, -32
-; SSE3-NEXT:  .Lcfi22:
+; SSE3-NEXT:  .Lcfi28:
 ; SSE3-NEXT:    .cfi_offset %r15, -24
-; SSE3-NEXT:  .Lcfi23:
+; SSE3-NEXT:  .Lcfi29:
 ; SSE3-NEXT:    .cfi_offset %rbp, -16
 ; SSE3-NEXT:    movd %xmm0, %eax
 ; SSE3-NEXT:    pextrw $1, %xmm0, %ecx
@@ -1375,11 +1387,23 @@
 ; SSE3-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
 ; SSE3-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm5[0],xmm1[1],xmm5[1],xmm1[2],xmm5[2],xmm1[3],xmm5[3]
 ; SSE3-NEXT:    popq %rbx
+; SSE3-NEXT:  .Lcfi30:
+; SSE3-NEXT:    .cfi_def_cfa_offset 48
 ; SSE3-NEXT:    popq %r12
+; SSE3-NEXT:  .Lcfi31:
+; SSE3-NEXT:    .cfi_def_cfa_offset 40
 ; SSE3-NEXT:    popq %r13
+; SSE3-NEXT:  .Lcfi32:
+; SSE3-NEXT:    .cfi_def_cfa_offset 32
 ; SSE3-NEXT:    popq %r14
+; SSE3-NEXT:  .Lcfi33:
+; SSE3-NEXT:    .cfi_def_cfa_offset 24
 ; SSE3-NEXT:    popq %r15
+; SSE3-NEXT:  .Lcfi34:
+; SSE3-NEXT:    .cfi_def_cfa_offset 16
 ; SSE3-NEXT:    popq %rbp
+; SSE3-NEXT:  .Lcfi35:
+; SSE3-NEXT:    .cfi_def_cfa_offset 8
 ; SSE3-NEXT:    retq
 ;
 ; SSSE3-LABEL: avx2_hadd_w:
Index: test/CodeGen/X86/hipe-cc64.ll
===================================================================
--- test/CodeGen/X86/hipe-cc64.ll
+++ test/CodeGen/X86/hipe-cc64.ll
@@ -91,6 +91,8 @@
   ; CHECK-NEXT: movl	$47, %ecx
   ; CHECK-NEXT: movl	$63, %r8d
   ; CHECK-NEXT: popq	%rax
+  ; CHECK-NEXT: .Lcfi1:
+  ; CHECK-NEXT: .cfi_def_cfa_offset 16
   ; CHECK-NEXT: jmp	tailcallee
   %ret = tail call cc11 { i64, i64, i64 } @tailcallee(i64 %hp, i64 %p, i64 15,
      i64 31, i64 47, i64 63, i64 79) #1
Index: test/CodeGen/X86/hipe-prologue.ll
===================================================================
--- test/CodeGen/X86/hipe-prologue.ll
+++ test/CodeGen/X86/hipe-prologue.ll
@@ -26,21 +26,21 @@
   ; X32-Linux-LABEL:       test_basic_hipecc:
   ; X32-Linux:       leal -140(%esp), %ebx
   ; X32-Linux-NEXT:  cmpl 120(%ebp), %ebx
-  ; X32-Linux-NEXT:  jb .LBB1_1
+  ; X32-Linux-NEXT:  jb .LBB1_2
 
   ; X32-Linux:       ret
 
-  ; X32-Linux:       .LBB1_1:
+  ; X32-Linux:       .LBB1_2:
   ; X32-Linux-NEXT:  calll inc_stack_0
 
   ; X64-Linux-LABEL:       test_basic_hipecc:
   ; X64-Linux:       leaq -184(%rsp), %r14
   ; X64-Linux-NEXT:  cmpq 120(%rbp), %r14
-  ; X64-Linux-NEXT:  jb .LBB1_1
+  ; X64-Linux-NEXT:  jb .LBB1_2
 
   ; X64-Linux:       ret
 
-  ; X64-Linux:       .LBB1_1:
+  ; X64-Linux:       .LBB1_2:
   ; X64-Linux-NEXT:  callq inc_stack_0
 
   %mem = alloca i32, i32 10
Index: test/CodeGen/X86/imul.ll
===================================================================
--- test/CodeGen/X86/imul.ll
+++ test/CodeGen/X86/imul.ll
@@ -309,6 +309,8 @@
 ; X86-NEXT:    subl %ecx, %edx
 ; X86-NEXT:    subl %esi, %edx
 ; X86-NEXT:    popl %esi
+; X86-NEXT:  .Lcfi2:
+; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 entry:
 	%tmp3 = mul i64 %a, -31
@@ -351,9 +353,9 @@
 ; X86-LABEL: test7:
 ; X86:       # BB#0: # %entry
 ; X86-NEXT:    pushl %esi
-; X86-NEXT:  .Lcfi2:
-; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:  .Lcfi3:
+; X86-NEXT:    .cfi_def_cfa_offset 8
+; X86-NEXT:  .Lcfi4:
 ; X86-NEXT:    .cfi_offset %esi, -8
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
@@ -366,6 +368,8 @@
 ; X86-NEXT:    subl %ecx, %edx
 ; X86-NEXT:    subl %esi, %edx
 ; X86-NEXT:    popl %esi
+; X86-NEXT:  .Lcfi5:
+; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 entry:
 	%tmp3 = mul i64 %a, -33
@@ -382,9 +386,9 @@
 ; X86-LABEL: testOverflow:
 ; X86:       # BB#0: # %entry
 ; X86-NEXT:    pushl %esi
-; X86-NEXT:  .Lcfi4:
+; X86-NEXT:  .Lcfi6:
 ; X86-NEXT:    .cfi_def_cfa_offset 8
-; X86-NEXT:  .Lcfi5:
+; X86-NEXT:  .Lcfi7:
 ; X86-NEXT:    .cfi_offset %esi, -8
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl $-1, %edx
@@ -396,6 +400,8 @@
 ; X86-NEXT:    addl %esi, %edx
 ; X86-NEXT:    subl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    popl %esi
+; X86-NEXT:  .Lcfi8:
+; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 entry:
 	%tmp3 = mul i64 %a, 9223372036854775807
Index: test/CodeGen/X86/legalize-shift-64.ll
===================================================================
--- test/CodeGen/X86/legalize-shift-64.ll
+++ test/CodeGen/X86/legalize-shift-64.ll
@@ -125,9 +125,17 @@
 ; CHECK-NEXT:    movl %esi, 4(%eax)
 ; CHECK-NEXT:    movl %edi, (%eax)
 ; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:  .Lcfi8:
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    popl %edi
+; CHECK-NEXT:  .Lcfi9:
+; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    popl %ebx
+; CHECK-NEXT:  .Lcfi10:
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    popl %ebp
+; CHECK-NEXT:  .Lcfi11:
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-NEXT:    retl $4
   %shl = shl <2 x i64> %A, %B
   ret <2 x i64> %shl
@@ -138,12 +146,12 @@
 ; CHECK-LABEL: test6:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    pushl %ebp
-; CHECK-NEXT:  .Lcfi8:
+; CHECK-NEXT:  .Lcfi12:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
-; CHECK-NEXT:  .Lcfi9:
+; CHECK-NEXT:  .Lcfi13:
 ; CHECK-NEXT:    .cfi_offset %ebp, -8
 ; CHECK-NEXT:    movl %esp, %ebp
-; CHECK-NEXT:  .Lcfi10:
+; CHECK-NEXT:  .Lcfi14:
 ; CHECK-NEXT:    .cfi_def_cfa_register %ebp
 ; CHECK-NEXT:    andl $-8, %esp
 ; CHECK-NEXT:    subl $16, %esp
@@ -163,15 +171,17 @@
 ; CHECK-NEXT:    movzbl %cl, %ecx
 ; CHECK-NEXT:    xorl $1, %eax
 ; CHECK-NEXT:    orl %ecx, %eax
-; CHECK-NEXT:    je .LBB5_5
+; CHECK-NEXT:    je .LBB5_4
 ; CHECK-NEXT:  # BB#3: # %if.then
 ; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    jmp .LBB5_4
-; CHECK-NEXT:  .LBB5_5: # %if.end
+; CHECK-NEXT:    jmp .LBB5_5
+; CHECK-NEXT:  .LBB5_4: # %if.end
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:  .LBB5_4: # %if.then
+; CHECK-NEXT:  .LBB5_5: # %if.then
 ; CHECK-NEXT:    movl %ebp, %esp
 ; CHECK-NEXT:    popl %ebp
+; CHECK-NEXT:  .Lcfi15:
+; CHECK-NEXT:    .cfi_def_cfa %esp, 4
 ; CHECK-NEXT:    retl
   %x = alloca i32, align 4
   %t = alloca i64, align 8
Index: test/CodeGen/X86/load-combine.ll
===================================================================
--- test/CodeGen/X86/load-combine.ll
+++ test/CodeGen/X86/load-combine.ll
@@ -378,6 +378,8 @@
 ; CHECK-NEXT:    orl %ecx, %eax
 ; CHECK-NEXT:    orl %edx, %eax
 ; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:  .Lcfi2:
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-NEXT:    retl
 ;
 ; CHECK64-LABEL: load_i32_by_i8_bswap_uses:
@@ -482,9 +484,9 @@
 ; CHECK-LABEL: load_i32_by_i8_bswap_store_in_between:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:  .Lcfi2:
-; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:  .Lcfi3:
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:  .Lcfi4:
 ; CHECK-NEXT:    .cfi_offset %esi, -8
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
@@ -500,6 +502,8 @@
 ; CHECK-NEXT:    movzbl 3(%ecx), %eax
 ; CHECK-NEXT:    orl %edx, %eax
 ; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:  .Lcfi5:
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-NEXT:    retl
 ;
 ; CHECK64-LABEL: load_i32_by_i8_bswap_store_in_between:
Index: test/CodeGen/X86/masked_gather_scatter.ll
===================================================================
--- test/CodeGen/X86/masked_gather_scatter.ll
+++ test/CodeGen/X86/masked_gather_scatter.ll
@@ -1711,6 +1711,8 @@
 ; KNL_32-NEXT:    vmovdqa64 %zmm2, %zmm0
 ; KNL_32-NEXT:    movl %ebp, %esp
 ; KNL_32-NEXT:    popl %ebp
+; KNL_32-NEXT:  .Lcfi3:
+; KNL_32-NEXT:    .cfi_def_cfa %esp, 4
 ; KNL_32-NEXT:    retl
 ;
 ; SKX-LABEL: test_gather_16i64:
@@ -1728,12 +1730,12 @@
 ; SKX_32-LABEL: test_gather_16i64:
 ; SKX_32:       # BB#0:
 ; SKX_32-NEXT:    pushl %ebp
-; SKX_32-NEXT:  .Lcfi1:
-; SKX_32-NEXT:    .cfi_def_cfa_offset 8
 ; SKX_32-NEXT:  .Lcfi2:
+; SKX_32-NEXT:    .cfi_def_cfa_offset 8
+; SKX_32-NEXT:  .Lcfi3:
 ; SKX_32-NEXT:    .cfi_offset %ebp, -8
 ; SKX_32-NEXT:    movl %esp, %ebp
-; SKX_32-NEXT:  .Lcfi3:
+; SKX_32-NEXT:  .Lcfi4:
 ; SKX_32-NEXT:    .cfi_def_cfa_register %ebp
 ; SKX_32-NEXT:    andl $-64, %esp
 ; SKX_32-NEXT:    subl $64, %esp
@@ -1748,6 +1750,8 @@
 ; SKX_32-NEXT:    vmovdqa64 %zmm2, %zmm0
 ; SKX_32-NEXT:    movl %ebp, %esp
 ; SKX_32-NEXT:    popl %ebp
+; SKX_32-NEXT:  .Lcfi5:
+; SKX_32-NEXT:    .cfi_def_cfa %esp, 4
 ; SKX_32-NEXT:    retl
   %res = call <16 x i64> @llvm.masked.gather.v16i64(<16 x i64*> %ptrs, i32 4, <16 x i1> %mask, <16 x i64> %src0)
   ret <16 x i64> %res
@@ -1814,12 +1818,12 @@
 ; KNL_32-LABEL: test_gather_16f64:
 ; KNL_32:       # BB#0:
 ; KNL_32-NEXT:    pushl %ebp
-; KNL_32-NEXT:  .Lcfi3:
-; KNL_32-NEXT:    .cfi_def_cfa_offset 8
 ; KNL_32-NEXT:  .Lcfi4:
+; KNL_32-NEXT:    .cfi_def_cfa_offset 8
+; KNL_32-NEXT:  .Lcfi5:
 ; KNL_32-NEXT:    .cfi_offset %ebp, -8
 ; KNL_32-NEXT:    movl %esp, %ebp
-; KNL_32-NEXT:  .Lcfi5:
+; KNL_32-NEXT:  .Lcfi6:
 ; KNL_32-NEXT:    .cfi_def_cfa_register %ebp
 ; KNL_32-NEXT:    andl $-64, %esp
 ; KNL_32-NEXT:    subl $64, %esp
@@ -1834,6 +1838,8 @@
 ; KNL_32-NEXT:    vmovapd %zmm2, %zmm0
 ; KNL_32-NEXT:    movl %ebp, %esp
 ; KNL_32-NEXT:    popl %ebp
+; KNL_32-NEXT:  .Lcfi7:
+; KNL_32-NEXT:    .cfi_def_cfa %esp, 4
 ; KNL_32-NEXT:    retl
 ;
 ; SKX-LABEL: test_gather_16f64:
@@ -1851,12 +1857,12 @@
 ; SKX_32-LABEL: test_gather_16f64:
 ; SKX_32:       # BB#0:
 ; SKX_32-NEXT:    pushl %ebp
-; SKX_32-NEXT:  .Lcfi4:
+; SKX_32-NEXT:  .Lcfi6:
 ; SKX_32-NEXT:    .cfi_def_cfa_offset 8
-; SKX_32-NEXT:  .Lcfi5:
+; SKX_32-NEXT:  .Lcfi7:
 ; SKX_32-NEXT:    .cfi_offset %ebp, -8
 ; SKX_32-NEXT:    movl %esp, %ebp
-; SKX_32-NEXT:  .Lcfi6:
+; SKX_32-NEXT:  .Lcfi8:
 ; SKX_32-NEXT:    .cfi_def_cfa_register %ebp
 ; SKX_32-NEXT:    andl $-64, %esp
 ; SKX_32-NEXT:    subl $64, %esp
@@ -1871,6 +1877,8 @@
 ; SKX_32-NEXT:    vmovapd %zmm2, %zmm0
 ; SKX_32-NEXT:    movl %ebp, %esp
 ; SKX_32-NEXT:    popl %ebp
+; SKX_32-NEXT:  .Lcfi9:
+; SKX_32-NEXT:    .cfi_def_cfa %esp, 4
 ; SKX_32-NEXT:    retl
   %res = call <16 x double> @llvm.masked.gather.v16f64(<16 x double*> %ptrs, i32 4, <16 x i1> %mask, <16 x double> %src0)
   ret <16 x double> %res
@@ -1936,12 +1944,12 @@
 ; KNL_32-LABEL: test_scatter_16i64:
 ; KNL_32:       # BB#0:
 ; KNL_32-NEXT:    pushl %ebp
-; KNL_32-NEXT:  .Lcfi6:
+; KNL_32-NEXT:  .Lcfi8:
 ; KNL_32-NEXT:    .cfi_def_cfa_offset 8
-; KNL_32-NEXT:  .Lcfi7:
+; KNL_32-NEXT:  .Lcfi9:
 ; KNL_32-NEXT:    .cfi_offset %ebp, -8
 ; KNL_32-NEXT:    movl %esp, %ebp
-; KNL_32-NEXT:  .Lcfi8:
+; KNL_32-NEXT:  .Lcfi10:
 ; KNL_32-NEXT:    .cfi_def_cfa_register %ebp
 ; KNL_32-NEXT:    andl $-64, %esp
 ; KNL_32-NEXT:    subl $64, %esp
@@ -1955,6 +1963,8 @@
 ; KNL_32-NEXT:    vpscatterdq %zmm1, (,%ymm0) {%k2}
 ; KNL_32-NEXT:    movl %ebp, %esp
 ; KNL_32-NEXT:    popl %ebp
+; KNL_32-NEXT:  .Lcfi11:
+; KNL_32-NEXT:  	.cfi_def_cfa %esp, 4
 ; KNL_32-NEXT:    vzeroupper
 ; KNL_32-NEXT:    retl
 ;
@@ -1972,12 +1982,12 @@
 ; SKX_32-LABEL: test_scatter_16i64:
 ; SKX_32:       # BB#0:
 ; SKX_32-NEXT:    pushl %ebp
-; SKX_32-NEXT:  .Lcfi7:
+; SKX_32-NEXT:  .Lcfi10:
 ; SKX_32-NEXT:    .cfi_def_cfa_offset 8
-; SKX_32-NEXT:  .Lcfi8:
+; SKX_32-NEXT:  .Lcfi11:
 ; SKX_32-NEXT:    .cfi_offset %ebp, -8
 ; SKX_32-NEXT:    movl %esp, %ebp
-; SKX_32-NEXT:  .Lcfi9:
+; SKX_32-NEXT:  .Lcfi12:
 ; SKX_32-NEXT:    .cfi_def_cfa_register %ebp
 ; SKX_32-NEXT:    andl $-64, %esp
 ; SKX_32-NEXT:    subl $64, %esp
@@ -1991,6 +2001,8 @@
 ; SKX_32-NEXT:    vpscatterdq %zmm1, (,%ymm0) {%k2}
 ; SKX_32-NEXT:    movl %ebp, %esp
 ; SKX_32-NEXT:    popl %ebp
+; SKX_32-NEXT:  .Lcfi13:
+; SKX_32-NEXT:  	.cfi_def_cfa %esp, 4
 ; SKX_32-NEXT:    vzeroupper
 ; SKX_32-NEXT:    retl
   call void @llvm.masked.scatter.v16i64(<16 x i64> %src0, <16 x i64*> %ptrs, i32 4, <16 x i1> %mask)
@@ -2058,12 +2070,12 @@
 ; KNL_32-LABEL: test_scatter_16f64:
 ; KNL_32:       # BB#0:
 ; KNL_32-NEXT:    pushl %ebp
-; KNL_32-NEXT:  .Lcfi9:
+; KNL_32-NEXT:  .Lcfi12:
 ; KNL_32-NEXT:    .cfi_def_cfa_offset 8
-; KNL_32-NEXT:  .Lcfi10:
+; KNL_32-NEXT:  .Lcfi13:
 ; KNL_32-NEXT:    .cfi_offset %ebp, -8
 ; KNL_32-NEXT:    movl %esp, %ebp
-; KNL_32-NEXT:  .Lcfi11:
+; KNL_32-NEXT:  .Lcfi14:
 ; KNL_32-NEXT:    .cfi_def_cfa_register %ebp
 ; KNL_32-NEXT:    andl $-64, %esp
 ; KNL_32-NEXT:    subl $64, %esp
@@ -2077,6 +2089,8 @@
 ; KNL_32-NEXT:    vscatterdpd %zmm1, (,%ymm0) {%k2}
 ; KNL_32-NEXT:    movl %ebp, %esp
 ; KNL_32-NEXT:    popl %ebp
+; KNL_32-NEXT:  .Lcfi15:
+; KNL_32-NEXT:    .cfi_def_cfa %esp, 4
 ; KNL_32-NEXT:    vzeroupper
 ; KNL_32-NEXT:    retl
 ;
@@ -2094,12 +2108,12 @@
 ; SKX_32-LABEL: test_scatter_16f64:
 ; SKX_32:       # BB#0:
 ; SKX_32-NEXT:    pushl %ebp
-; SKX_32-NEXT:  .Lcfi10:
+; SKX_32-NEXT:  .Lcfi14:
 ; SKX_32-NEXT:    .cfi_def_cfa_offset 8
-; SKX_32-NEXT:  .Lcfi11:
+; SKX_32-NEXT:  .Lcfi15:
 ; SKX_32-NEXT:    .cfi_offset %ebp, -8
 ; SKX_32-NEXT:    movl %esp, %ebp
-; SKX_32-NEXT:  .Lcfi12:
+; SKX_32-NEXT:  .Lcfi16:
 ; SKX_32-NEXT:    .cfi_def_cfa_register %ebp
 ; SKX_32-NEXT:    andl $-64, %esp
 ; SKX_32-NEXT:    subl $64, %esp
@@ -2113,6 +2127,8 @@
 ; SKX_32-NEXT:    vscatterdpd %zmm1, (,%ymm0) {%k2}
 ; SKX_32-NEXT:    movl %ebp, %esp
 ; SKX_32-NEXT:    popl %ebp
+; SKX_32-NEXT:  .Lcfi17:
+; SKX_32-NEXT:  	.cfi_def_cfa %esp, 4
 ; SKX_32-NEXT:    vzeroupper
 ; SKX_32-NEXT:    retl
   call void @llvm.masked.scatter.v16f64(<16 x double> %src0, <16 x double*> %ptrs, i32 4, <16 x i1> %mask)
@@ -2139,12 +2155,12 @@
 ; KNL_32-LABEL: test_pr28312:
 ; KNL_32:       # BB#0:
 ; KNL_32-NEXT:    pushl %ebp
-; KNL_32-NEXT:  .Lcfi12:
+; KNL_32-NEXT:  .Lcfi16:
 ; KNL_32-NEXT:    .cfi_def_cfa_offset 8
-; KNL_32-NEXT:  .Lcfi13:
+; KNL_32-NEXT:  .Lcfi17:
 ; KNL_32-NEXT:    .cfi_offset %ebp, -8
 ; KNL_32-NEXT:    movl %esp, %ebp
-; KNL_32-NEXT:  .Lcfi14:
+; KNL_32-NEXT:  .Lcfi18:
 ; KNL_32-NEXT:    .cfi_def_cfa_register %ebp
 ; KNL_32-NEXT:    andl $-32, %esp
 ; KNL_32-NEXT:    subl $32, %esp
@@ -2162,6 +2178,8 @@
 ; KNL_32-NEXT:    vpaddq %ymm0, %ymm1, %ymm0
 ; KNL_32-NEXT:    movl %ebp, %esp
 ; KNL_32-NEXT:    popl %ebp
+; KNL_32-NEXT:  .Lcfi19:
+; KNL_32-NEXT:    .cfi_def_cfa %esp, 4
 ; KNL_32-NEXT:    retl
 ;
 ; SKX-LABEL: test_pr28312:
@@ -2176,12 +2194,12 @@
 ; SKX_32-LABEL: test_pr28312:
 ; SKX_32:       # BB#0:
 ; SKX_32-NEXT:    pushl %ebp
-; SKX_32-NEXT:  .Lcfi13:
+; SKX_32-NEXT:  .Lcfi18:
 ; SKX_32-NEXT:    .cfi_def_cfa_offset 8
-; SKX_32-NEXT:  .Lcfi14:
+; SKX_32-NEXT:  .Lcfi19:
 ; SKX_32-NEXT:    .cfi_offset %ebp, -8
 ; SKX_32-NEXT:    movl %esp, %ebp
-; SKX_32-NEXT:  .Lcfi15:
+; SKX_32-NEXT:  .Lcfi20:
 ; SKX_32-NEXT:    .cfi_def_cfa_register %ebp
 ; SKX_32-NEXT:    andl $-32, %esp
 ; SKX_32-NEXT:    subl $32, %esp
@@ -2192,6 +2210,8 @@
 ; SKX_32-NEXT:    vpaddq %ymm0, %ymm1, %ymm0
 ; SKX_32-NEXT:    movl %ebp, %esp
 ; SKX_32-NEXT:    popl %ebp
+; SKX_32-NEXT:  .Lcfi21:
+; SKX_32-NEXT:    .cfi_def_cfa %esp, 4
 ; SKX_32-NEXT:    retl
   %g1 = call <4 x i64> @llvm.masked.gather.v4i64(<4 x i64*> %p1, i32 8, <4 x i1> %k, <4 x i64> undef)
   %g2 = call <4 x i64> @llvm.masked.gather.v4i64(<4 x i64*> %p1, i32 8, <4 x i1> %k, <4 x i64> undef)
Index: test/CodeGen/X86/memset-nonzero.ll
===================================================================
--- test/CodeGen/X86/memset-nonzero.ll
+++ test/CodeGen/X86/memset-nonzero.ll
@@ -153,6 +153,8 @@
 ; SSE-NEXT:    movl $256, %edx # imm = 0x100
 ; SSE-NEXT:    callq memset
 ; SSE-NEXT:    popq %rax
+; SSE-NEXT:  .Lcfi1:
+; SSE-NEXT:    .cfi_def_cfa_offset 8
 ; SSE-NEXT:    retq
 ;
 ; SSE2FAST-LABEL: memset_256_nonzero_bytes:
Index: test/CodeGen/X86/merge-consecutive-loads-128.ll
===================================================================
--- test/CodeGen/X86/merge-consecutive-loads-128.ll
+++ test/CodeGen/X86/merge-consecutive-loads-128.ll
@@ -76,7 +76,11 @@
 ; X32-SSE1-NEXT:    movl %esi, 4(%eax)
 ; X32-SSE1-NEXT:    movl %edx, (%eax)
 ; X32-SSE1-NEXT:    popl %esi
+; X32-SSE1-NEXT:  .Lcfi4:
+; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
 ; X32-SSE1-NEXT:    popl %edi
+; X32-SSE1-NEXT:  .Lcfi5:
+; X32-SSE1-NEXT:    .cfi_def_cfa_offset 4
 ; X32-SSE1-NEXT:    retl $4
 ;
 ; X32-SSE41-LABEL: merge_2i64_i64_12:
@@ -381,9 +385,9 @@
 ; X32-SSE1-LABEL: merge_4i32_i32_23u5:
 ; X32-SSE1:       # BB#0:
 ; X32-SSE1-NEXT:    pushl %esi
-; X32-SSE1-NEXT:  .Lcfi4:
+; X32-SSE1-NEXT:  .Lcfi6:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
-; X32-SSE1-NEXT:  .Lcfi5:
+; X32-SSE1-NEXT:  .Lcfi7:
 ; X32-SSE1-NEXT:    .cfi_offset %esi, -8
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
@@ -394,6 +398,8 @@
 ; X32-SSE1-NEXT:    movl %edx, (%eax)
 ; X32-SSE1-NEXT:    movl %ecx, 12(%eax)
 ; X32-SSE1-NEXT:    popl %esi
+; X32-SSE1-NEXT:  .Lcfi8:
+; X32-SSE1-NEXT:    .cfi_def_cfa_offset 4
 ; X32-SSE1-NEXT:    retl $4
 ;
 ; X32-SSE41-LABEL: merge_4i32_i32_23u5:
@@ -531,24 +537,24 @@
 ; X32-SSE1-LABEL: merge_8i16_i16_23u567u9:
 ; X32-SSE1:       # BB#0:
 ; X32-SSE1-NEXT:    pushl %ebp
-; X32-SSE1-NEXT:  .Lcfi6:
+; X32-SSE1-NEXT:  .Lcfi9:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
 ; X32-SSE1-NEXT:    pushl %ebx
-; X32-SSE1-NEXT:  .Lcfi7:
+; X32-SSE1-NEXT:  .Lcfi10:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 12
 ; X32-SSE1-NEXT:    pushl %edi
-; X32-SSE1-NEXT:  .Lcfi8:
+; X32-SSE1-NEXT:  .Lcfi11:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 16
 ; X32-SSE1-NEXT:    pushl %esi
-; X32-SSE1-NEXT:  .Lcfi9:
+; X32-SSE1-NEXT:  .Lcfi12:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 20
-; X32-SSE1-NEXT:  .Lcfi10:
+; X32-SSE1-NEXT:  .Lcfi13:
 ; X32-SSE1-NEXT:    .cfi_offset %esi, -20
-; X32-SSE1-NEXT:  .Lcfi11:
+; X32-SSE1-NEXT:  .Lcfi14:
 ; X32-SSE1-NEXT:    .cfi_offset %edi, -16
-; X32-SSE1-NEXT:  .Lcfi12:
+; X32-SSE1-NEXT:  .Lcfi15:
 ; X32-SSE1-NEXT:    .cfi_offset %ebx, -12
-; X32-SSE1-NEXT:  .Lcfi13:
+; X32-SSE1-NEXT:  .Lcfi16:
 ; X32-SSE1-NEXT:    .cfi_offset %ebp, -8
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
@@ -565,9 +571,17 @@
 ; X32-SSE1-NEXT:    movw %dx, (%eax)
 ; X32-SSE1-NEXT:    movw %di, 6(%eax)
 ; X32-SSE1-NEXT:    popl %esi
+; X32-SSE1-NEXT:  .Lcfi17:
+; X32-SSE1-NEXT:    .cfi_def_cfa_offset 16
 ; X32-SSE1-NEXT:    popl %edi
+; X32-SSE1-NEXT:  .Lcfi18:
+; X32-SSE1-NEXT:    .cfi_def_cfa_offset 12
 ; X32-SSE1-NEXT:    popl %ebx
+; X32-SSE1-NEXT:  .Lcfi19:
+; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
 ; X32-SSE1-NEXT:    popl %ebp
+; X32-SSE1-NEXT:  .Lcfi20:
+; X32-SSE1-NEXT:    .cfi_def_cfa_offset 4
 ; X32-SSE1-NEXT:    retl $4
 ;
 ; X32-SSE41-LABEL: merge_8i16_i16_23u567u9:
@@ -645,9 +659,9 @@
 ; X32-SSE1-LABEL: merge_8i16_i16_45u7zzzz:
 ; X32-SSE1:       # BB#0:
 ; X32-SSE1-NEXT:    pushl %esi
-; X32-SSE1-NEXT:  .Lcfi14:
+; X32-SSE1-NEXT:  .Lcfi21:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
-; X32-SSE1-NEXT:  .Lcfi15:
+; X32-SSE1-NEXT:  .Lcfi22:
 ; X32-SSE1-NEXT:    .cfi_offset %esi, -8
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
@@ -662,6 +676,8 @@
 ; X32-SSE1-NEXT:    movw $0, 10(%eax)
 ; X32-SSE1-NEXT:    movw $0, 8(%eax)
 ; X32-SSE1-NEXT:    popl %esi
+; X32-SSE1-NEXT:  .Lcfi23:
+; X32-SSE1-NEXT:    .cfi_def_cfa_offset 4
 ; X32-SSE1-NEXT:    retl $4
 ;
 ; X32-SSE41-LABEL: merge_8i16_i16_45u7zzzz:
@@ -699,12 +715,12 @@
 ; X32-SSE1-LABEL: merge_16i8_i8_01u3456789ABCDuF:
 ; X32-SSE1:       # BB#0:
 ; X32-SSE1-NEXT:    pushl %ebx
-; X32-SSE1-NEXT:  .Lcfi16:
+; X32-SSE1-NEXT:  .Lcfi24:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
 ; X32-SSE1-NEXT:    subl $12, %esp
-; X32-SSE1-NEXT:  .Lcfi17:
+; X32-SSE1-NEXT:  .Lcfi25:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 20
-; X32-SSE1-NEXT:  .Lcfi18:
+; X32-SSE1-NEXT:  .Lcfi26:
 ; X32-SSE1-NEXT:    .cfi_offset %ebx, -8
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
@@ -755,7 +771,11 @@
 ; X32-SSE1-NEXT:    movb {{[0-9]+}}(%esp), %cl # 1-byte Reload
 ; X32-SSE1-NEXT:    movb %cl, 3(%eax)
 ; X32-SSE1-NEXT:    addl $12, %esp
+; X32-SSE1-NEXT:  .Lcfi27:
+; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
 ; X32-SSE1-NEXT:    popl %ebx
+; X32-SSE1-NEXT:  .Lcfi28:
+; X32-SSE1-NEXT:    .cfi_def_cfa_offset 4
 ; X32-SSE1-NEXT:    retl $4
 ;
 ; X32-SSE41-LABEL: merge_16i8_i8_01u3456789ABCDuF:
@@ -872,12 +892,12 @@
 ; X32-SSE1-LABEL: merge_16i8_i8_0123uu67uuuuuzzz:
 ; X32-SSE1:       # BB#0:
 ; X32-SSE1-NEXT:    pushl %ebx
-; X32-SSE1-NEXT:  .Lcfi19:
+; X32-SSE1-NEXT:  .Lcfi29:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
 ; X32-SSE1-NEXT:    pushl %eax
-; X32-SSE1-NEXT:  .Lcfi20:
+; X32-SSE1-NEXT:  .Lcfi30:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 12
-; X32-SSE1-NEXT:  .Lcfi21:
+; X32-SSE1-NEXT:  .Lcfi31:
 ; X32-SSE1-NEXT:    .cfi_offset %ebx, -8
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
@@ -899,7 +919,11 @@
 ; X32-SSE1-NEXT:    movb $0, 14(%eax)
 ; X32-SSE1-NEXT:    movb $0, 13(%eax)
 ; X32-SSE1-NEXT:    addl $4, %esp
+; X32-SSE1-NEXT:  .Lcfi32:
+; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
 ; X32-SSE1-NEXT:    popl %ebx
+; X32-SSE1-NEXT:  .Lcfi33:
+; X32-SSE1-NEXT:    .cfi_def_cfa_offset 4
 ; X32-SSE1-NEXT:    retl $4
 ;
 ; X32-SSE41-LABEL: merge_16i8_i8_0123uu67uuuuuzzz:
@@ -994,14 +1018,14 @@
 ; X32-SSE1-LABEL: merge_2i64_i64_12_volatile:
 ; X32-SSE1:       # BB#0:
 ; X32-SSE1-NEXT:    pushl %edi
-; X32-SSE1-NEXT:  .Lcfi22:
+; X32-SSE1-NEXT:  .Lcfi34:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
 ; X32-SSE1-NEXT:    pushl %esi
-; X32-SSE1-NEXT:  .Lcfi23:
+; X32-SSE1-NEXT:  .Lcfi35:
 ; X32-SSE1-NEXT:    .cfi_def_cfa_offset 12
-; X32-SSE1-NEXT:  .Lcfi24:
+; X32-SSE1-NEXT:  .Lcfi36:
 ; X32-SSE1-NEXT:    .cfi_offset %esi, -12
-; X32-SSE1-NEXT:  .Lcfi25:
+; X32-SSE1-NEXT:  .Lcfi37:
 ; X32-SSE1-NEXT:    .cfi_offset %edi, -8
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-SSE1-NEXT:    movl {{[0-9]+}}(%esp), %ecx
@@ -1014,7 +1038,11 @@
 ; X32-SSE1-NEXT:    movl %esi, 4(%eax)
 ; X32-SSE1-NEXT:    movl %edx, (%eax)
 ; X32-SSE1-NEXT:    popl %esi
+; X32-SSE1-NEXT:  .Lcfi38:
+; X32-SSE1-NEXT:    .cfi_def_cfa_offset 8
 ; X32-SSE1-NEXT:    popl %edi
+; X32-SSE1-NEXT:  .Lcfi39:
+; X32-SSE1-NEXT:    .cfi_def_cfa_offset 4
 ; X32-SSE1-NEXT:    retl $4
 ;
 ; X32-SSE41-LABEL: merge_2i64_i64_12_volatile:
Index: test/CodeGen/X86/movtopush.ll
===================================================================
--- test/CodeGen/X86/movtopush.ll
+++ test/CodeGen/X86/movtopush.ll
@@ -376,8 +376,9 @@
 ; LINUX: pushl   $1
 ; LINUX: .cfi_adjust_cfa_offset 4
 ; LINUX: calll   good
-; LINUX: addl    $28, %esp
+; LINUX: addl    $16, %esp
 ; LINUX: .cfi_adjust_cfa_offset -16
+; LINUX: addl    $12, %esp
 ; LINUX-NOT: add
 ; LINUX: retl
 define void @pr27140() optsize {
Index: test/CodeGen/X86/mul-i256.ll
===================================================================
--- test/CodeGen/X86/mul-i256.ll
+++ test/CodeGen/X86/mul-i256.ll
@@ -195,6 +195,8 @@
 ; X32-NEXT:    popl %edi
 ; X32-NEXT:    popl %ebx
 ; X32-NEXT:    popl %ebp
+; X32-NEXT:  .Lcfi6:
+; X32-NEXT:    .cfi_def_cfa %esp, 4
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test:
@@ -275,9 +277,17 @@
 ; X64-NEXT:    movq %rax, 16(%r10)
 ; X64-NEXT:    movq %rdx, 24(%r10)
 ; X64-NEXT:    popq %rbx
+; X64-NEXT:  .Lcfi8:
+; X64-NEXT:    .cfi_def_cfa_offset 32
 ; X64-NEXT:    popq %r12
+; X64-NEXT:  .Lcfi9:
+; X64-NEXT:    .cfi_def_cfa_offset 24
 ; X64-NEXT:    popq %r14
+; X64-NEXT:  .Lcfi10:
+; X64-NEXT:    .cfi_def_cfa_offset 16
 ; X64-NEXT:    popq %r15
+; X64-NEXT:  .Lcfi11:
+; X64-NEXT:    .cfi_def_cfa_offset 8
 ; X64-NEXT:    retq
 entry:
   %av = load i256, i256* %a
Index: test/CodeGen/X86/pr21792.ll
===================================================================
--- test/CodeGen/X86/pr21792.ll
+++ test/CodeGen/X86/pr21792.ll
@@ -29,6 +29,8 @@
 ; CHECK-NEXT:    leaq stuff+8(%r9), %r9
 ; CHECK-NEXT:    callq toto
 ; CHECK-NEXT:    popq %rax
+; CHECK-NEXT:  .Lcfi1:
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 entry:
   %tmp2 = bitcast <4 x float> %vx to <2 x i64>
Index: test/CodeGen/X86/pr29112.ll
===================================================================
--- test/CodeGen/X86/pr29112.ll
+++ test/CodeGen/X86/pr29112.ll
@@ -66,6 +66,8 @@
 ; CHECK-NEXT:    vaddps {{[0-9]+}}(%rsp), %xmm1, %xmm1 # 16-byte Folded Reload
 ; CHECK-NEXT:    vaddps %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    addq $88, %rsp
+; CHECK-NEXT:  .Lcfi1:
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
   %a1 = shufflevector <16 x float>%c1, <16 x float>%c2, <4 x i32> <i32 4, i32 20, i32 1, i32 17>
 
Index: test/CodeGen/X86/pr30430.ll
===================================================================
--- test/CodeGen/X86/pr30430.ll
+++ test/CodeGen/X86/pr30430.ll
@@ -111,6 +111,8 @@
 ; CHECK-NEXT:    vmovss %xmm14, (%rsp) # 4-byte Spill
 ; CHECK-NEXT:    movq %rbp, %rsp
 ; CHECK-NEXT:    popq %rbp
+; CHECK-NEXT:  .Lcfi3:
+; CHECK-NEXT:    .cfi_def_cfa %rsp, 8
 ; CHECK-NEXT:    retq
 entry:
   %__A.addr.i = alloca float, align 4
Index: test/CodeGen/X86/pr9743.ll
===================================================================
--- test/CodeGen/X86/pr9743.ll
+++ test/CodeGen/X86/pr9743.ll
@@ -14,4 +14,6 @@
 ; CHECK-NEXT: :
 ; CHECK-NEXT:  .cfi_def_cfa_register %rbp
 ; CHECK-NEXT:  popq    %rbp
+; CHECK-NEXT: :
+; CHECK-NEXT:  .cfi_def_cfa %rsp, 8
 ; CHECK-NEXT:  ret
Index: test/CodeGen/X86/push-cfi-debug.ll
===================================================================
--- test/CodeGen/X86/push-cfi-debug.ll
+++ test/CodeGen/X86/push-cfi-debug.ll
@@ -23,8 +23,9 @@
 ; CHECK: .cfi_adjust_cfa_offset 4
 ; CHECK: calll stdfoo
 ; CHECK: .cfi_adjust_cfa_offset -8
-; CHECK: addl $20, %esp
+; CHECK: addl $8, %esp
 ; CHECK: .cfi_adjust_cfa_offset -8
+; CHECK: addl $12, %esp
 define void @test1() #0 !dbg !4 {
 entry:
   tail call void @foo(i32 1, i32 2) #1, !dbg !10
Index: test/CodeGen/X86/push-cfi-obj.ll
===================================================================
--- test/CodeGen/X86/push-cfi-obj.ll
+++ test/CodeGen/X86/push-cfi-obj.ll
@@ -12,7 +12,7 @@
 ; LINUX-NEXT:    ]
 ; LINUX-NEXT:    Address: 0x0
 ; LINUX-NEXT:    Offset: 0x68
-; LINUX-NEXT:    Size: 64
+; LINUX-NEXT:    Size: 72
 ; LINUX-NEXT:    Link: 0
 ; LINUX-NEXT:    Info: 0
 ; LINUX-NEXT:    AddressAlignment: 4
@@ -22,8 +22,9 @@
 ; LINUX-NEXT:    SectionData (
 ; LINUX-NEXT:      0000: 1C000000 00000000 017A504C 5200017C  |.........zPLR..||
 ; LINUX-NEXT:      0010: 08070000 00000000 1B0C0404 88010000  |................|
-; LINUX-NEXT:      0020: 1C000000 24000000 00000000 1D000000  |....$...........|
+; LINUX-NEXT:      0020: 24000000 24000000 00000000 1D000000  |$...$...........|
 ; LINUX-NEXT:      0030: 04000000 00410E08 8502420D 05432E10  |.....A....B..C..|
+; LINUX-NEXT:      0040: 540C0404 410C0508                    |T...A...|
 ; LINUX-NEXT:    )
 
 declare i32 @__gxx_personality_v0(...)
Index: test/CodeGen/X86/push-cfi.ll
===================================================================
--- test/CodeGen/X86/push-cfi.ll
+++ test/CodeGen/X86/push-cfi.ll
@@ -82,8 +82,9 @@
 ; LINUX-NEXT: Lcfi{{[0-9]+}}:
 ; LINUX-NEXT: .cfi_adjust_cfa_offset 4
 ; LINUX-NEXT: call
-; LINUX-NEXT: addl $28, %esp
+; LINUX-NEXT: addl $16, %esp
 ; LINUX: .cfi_adjust_cfa_offset -16
+; LINUX-NEXT: addl $12, %esp
 ; DARWIN-NOT: .cfi_escape
 ; DARWIN-NOT: pushl
 define void @test2_nofp() #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
Index: test/CodeGen/X86/return-ext.ll
===================================================================
--- test/CodeGen/X86/return-ext.ll
+++ test/CodeGen/X86/return-ext.ll
@@ -106,6 +106,8 @@
 ; CHECK: call
 ; CHECK-NEXT: movzbl
 ; CHECK-NEXT: {{pop|add}}
+; CHECK-NEXT: :
+; CHECK-NEXT: .cfi_def_cfa_offset {{4|8}}
 ; CHECK-NEXT: ret
 }
 
@@ -120,6 +122,8 @@
 ; CHECK: call
 ; CHECK-NEXT: movzbl
 ; CHECK-NEXT: {{pop|add}}
+; CHECK-NEXT: :
+; CHECK-NEXT: .cfi_def_cfa_offset {{4|8}}
 ; CHECK-NEXT: ret
 }
 
@@ -134,5 +138,7 @@
 ; CHECK: call
 ; CHECK-NEXT: movzwl
 ; CHECK-NEXT: {{pop|add}}
+; CHECK-NEXT: :
+; CHECK-NEXT: .cfi_def_cfa_offset {{4|8}}
 ; CHECK-NEXT: ret
 }
Index: test/CodeGen/X86/select_const.ll
===================================================================
--- test/CodeGen/X86/select_const.ll
+++ test/CodeGen/X86/select_const.ll
@@ -263,11 +263,11 @@
 ; CHECK-LABEL: sel_constants_add_constant_vec:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    testb $1, %dil
-; CHECK-NEXT:    jne .LBB22_1
-; CHECK-NEXT:  # BB#2:
+; CHECK-NEXT:    jne .LBB22_2
+; CHECK-NEXT:  # BB#1:
 ; CHECK-NEXT:    movaps {{.*#+}} xmm0 = [12,13,14,15]
 ; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB22_1:
+; CHECK-NEXT:  .LBB22_2:
 ; CHECK-NEXT:    movaps {{.*#+}} xmm0 = [4294967293,14,4,4]
 ; CHECK-NEXT:    retq
   %sel = select i1 %cond, <4 x i32> <i32 -4, i32 12, i32 1, i32 0>, <4 x i32> <i32 11, i32 11, i32 11, i32 11>
@@ -279,11 +279,11 @@
 ; CHECK-LABEL: sel_constants_fmul_constant_vec:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    testb $1, %dil
-; CHECK-NEXT:    jne .LBB23_1
-; CHECK-NEXT:  # BB#2:
+; CHECK-NEXT:    jne .LBB23_2
+; CHECK-NEXT:  # BB#1:
 ; CHECK-NEXT:    movaps {{.*#+}} xmm0 = [1.188300e+02,3.454000e+01]
 ; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB23_1:
+; CHECK-NEXT:  .LBB23_2:
 ; CHECK-NEXT:    movaps {{.*#+}} xmm0 = [-2.040000e+01,3.768000e+01]
 ; CHECK-NEXT:    retq
   %sel = select i1 %cond, <2 x double> <double -4.0, double 12.0>, <2 x double> <double 23.3, double 11.0>
Index: test/CodeGen/X86/setcc-lowering.ll
===================================================================
--- test/CodeGen/X86/setcc-lowering.ll
+++ test/CodeGen/X86/setcc-lowering.ll
@@ -76,6 +76,8 @@
 ; KNL-32-NEXT:    jne .LBB1_1
 ; KNL-32-NEXT:  # BB#2: # %for_exit600
 ; KNL-32-NEXT:    popl %esi
+; KNL-32-NEXT:  .Lcfi2:
+; KNL-32-NEXT:    .cfi_def_cfa_offset 4
 ; KNL-32-NEXT:    retl
 allocas:
   br label %for_test11.preheader
Index: test/CodeGen/X86/sse-scalar-fp-arith.ll
===================================================================
--- test/CodeGen/X86/sse-scalar-fp-arith.ll
+++ test/CodeGen/X86/sse-scalar-fp-arith.ll
@@ -1084,12 +1084,12 @@
 ; SSE2-LABEL: add_ss_mask:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    testb $1, %dil
-; SSE2-NEXT:    jne .LBB62_1
-; SSE2-NEXT:  # BB#2:
+; SSE2-NEXT:    jne .LBB62_2
+; SSE2-NEXT:  # BB#1:
 ; SSE2-NEXT:    movaps %xmm2, %xmm1
 ; SSE2-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
 ; SSE2-NEXT:    retq
-; SSE2-NEXT:  .LBB62_1:
+; SSE2-NEXT:  .LBB62_2:
 ; SSE2-NEXT:    addss %xmm0, %xmm1
 ; SSE2-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
 ; SSE2-NEXT:    retq
@@ -1097,12 +1097,12 @@
 ; SSE41-LABEL: add_ss_mask:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    testb $1, %dil
-; SSE41-NEXT:    jne .LBB62_1
-; SSE41-NEXT:  # BB#2:
+; SSE41-NEXT:    jne .LBB62_2
+; SSE41-NEXT:  # BB#1:
 ; SSE41-NEXT:    movaps %xmm2, %xmm1
 ; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
 ; SSE41-NEXT:    retq
-; SSE41-NEXT:  .LBB62_1:
+; SSE41-NEXT:  .LBB62_2:
 ; SSE41-NEXT:    addss %xmm0, %xmm1
 ; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
 ; SSE41-NEXT:    retq
@@ -1139,12 +1139,12 @@
 ; SSE2-LABEL: add_sd_mask:
 ; SSE2:       # BB#0:
 ; SSE2-NEXT:    testb $1, %dil
-; SSE2-NEXT:    jne .LBB63_1
-; SSE2-NEXT:  # BB#2:
+; SSE2-NEXT:    jne .LBB63_2
+; SSE2-NEXT:  # BB#1:
 ; SSE2-NEXT:    movapd %xmm2, %xmm1
 ; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE2-NEXT:    retq
-; SSE2-NEXT:  .LBB63_1:
+; SSE2-NEXT:  .LBB63_2:
 ; SSE2-NEXT:    addsd %xmm0, %xmm1
 ; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE2-NEXT:    retq
@@ -1152,12 +1152,12 @@
 ; SSE41-LABEL: add_sd_mask:
 ; SSE41:       # BB#0:
 ; SSE41-NEXT:    testb $1, %dil
-; SSE41-NEXT:    jne .LBB63_1
-; SSE41-NEXT:  # BB#2:
+; SSE41-NEXT:    jne .LBB63_2
+; SSE41-NEXT:  # BB#1:
 ; SSE41-NEXT:    movapd %xmm2, %xmm1
 ; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE41-NEXT:    retq
-; SSE41-NEXT:  .LBB63_1:
+; SSE41-NEXT:  .LBB63_2:
 ; SSE41-NEXT:    addsd %xmm0, %xmm1
 ; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
 ; SSE41-NEXT:    retq
Index: test/CodeGen/X86/sse1.ll
===================================================================
--- test/CodeGen/X86/sse1.ll
+++ test/CodeGen/X86/sse1.ll
@@ -55,35 +55,35 @@
 ; X32:       # BB#0: # %entry
 ; X32-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
 ; X32-NEXT:    xorps %xmm0, %xmm0
-; X32-NEXT:    je .LBB1_1
-; X32-NEXT:  # BB#2: # %entry
+; X32-NEXT:    je .LBB1_4
+; X32-NEXT:  # BB#1: # %entry
 ; X32-NEXT:    xorps %xmm1, %xmm1
 ; X32-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
 ; X32-NEXT:    jne .LBB1_5
-; X32-NEXT:  .LBB1_4:
+; X32-NEXT:  .LBB1_2:
 ; X32-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
 ; X32-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
-; X32-NEXT:    jne .LBB1_8
-; X32-NEXT:  .LBB1_7:
+; X32-NEXT:    jne .LBB1_6
+; X32-NEXT:  .LBB1_3:
 ; X32-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
-; X32-NEXT:    jmp .LBB1_9
-; X32-NEXT:  .LBB1_1:
+; X32-NEXT:    jmp .LBB1_7
+; X32-NEXT:  .LBB1_4:
 ; X32-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; X32-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
-; X32-NEXT:    je .LBB1_4
+; X32-NEXT:    je .LBB1_2
 ; X32-NEXT:  .LBB1_5: # %entry
 ; X32-NEXT:    xorps %xmm2, %xmm2
 ; X32-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
-; X32-NEXT:    je .LBB1_7
-; X32-NEXT:  .LBB1_8: # %entry
+; X32-NEXT:    je .LBB1_3
+; X32-NEXT:  .LBB1_6: # %entry
 ; X32-NEXT:    xorps %xmm3, %xmm3
-; X32-NEXT:  .LBB1_9: # %entry
+; X32-NEXT:  .LBB1_7: # %entry
 ; X32-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
 ; X32-NEXT:    unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
-; X32-NEXT:    jne .LBB1_11
-; X32-NEXT:  # BB#10:
+; X32-NEXT:    jne .LBB1_9
+; X32-NEXT:  # BB#8:
 ; X32-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-NEXT:  .LBB1_11: # %entry
+; X32-NEXT:  .LBB1_9: # %entry
 ; X32-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; X32-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
 ; X32-NEXT:    retl
@@ -92,35 +92,35 @@
 ; X64:       # BB#0: # %entry
 ; X64-NEXT:    testl %ecx, %ecx
 ; X64-NEXT:    xorps %xmm0, %xmm0
-; X64-NEXT:    je .LBB1_1
-; X64-NEXT:  # BB#2: # %entry
+; X64-NEXT:    je .LBB1_4
+; X64-NEXT:  # BB#1: # %entry
 ; X64-NEXT:    xorps %xmm1, %xmm1
 ; X64-NEXT:    testl %edx, %edx
 ; X64-NEXT:    jne .LBB1_5
-; X64-NEXT:  .LBB1_4:
+; X64-NEXT:  .LBB1_2:
 ; X64-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
 ; X64-NEXT:    testl %r8d, %r8d
-; X64-NEXT:    jne .LBB1_8
-; X64-NEXT:  .LBB1_7:
+; X64-NEXT:    jne .LBB1_6
+; X64-NEXT:  .LBB1_3:
 ; X64-NEXT:    movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
-; X64-NEXT:    jmp .LBB1_9
-; X64-NEXT:  .LBB1_1:
+; X64-NEXT:    jmp .LBB1_7
+; X64-NEXT:  .LBB1_4:
 ; X64-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; X64-NEXT:    testl %edx, %edx
-; X64-NEXT:    je .LBB1_4
+; X64-NEXT:    je .LBB1_2
 ; X64-NEXT:  .LBB1_5: # %entry
 ; X64-NEXT:    xorps %xmm2, %xmm2
 ; X64-NEXT:    testl %r8d, %r8d
-; X64-NEXT:    je .LBB1_7
-; X64-NEXT:  .LBB1_8: # %entry
+; X64-NEXT:    je .LBB1_3
+; X64-NEXT:  .LBB1_6: # %entry
 ; X64-NEXT:    xorps %xmm3, %xmm3
-; X64-NEXT:  .LBB1_9: # %entry
+; X64-NEXT:  .LBB1_7: # %entry
 ; X64-NEXT:    testl %esi, %esi
 ; X64-NEXT:    unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
-; X64-NEXT:    jne .LBB1_11
-; X64-NEXT:  # BB#10:
+; X64-NEXT:    jne .LBB1_9
+; X64-NEXT:  # BB#8:
 ; X64-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-NEXT:  .LBB1_11: # %entry
+; X64-NEXT:  .LBB1_9: # %entry
 ; X64-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; X64-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
 ; X64-NEXT:    retq
Index: test/CodeGen/X86/statepoint-call-lowering.ll
===================================================================
--- test/CodeGen/X86/statepoint-call-lowering.ll
+++ test/CodeGen/X86/statepoint-call-lowering.ll
@@ -83,6 +83,8 @@
 ; CHECK: callq return_i1
 ; CHECK-NEXT: .Ltmp5:
 ; CHECK-NEXT: popq %rcx
+; CHECK-NEXT: :
+; CHECK-NEXT: .cfi_def_cfa_offset 8
 ; CHECK-NEXT: retq
 entry:
   %safepoint_token = tail call token (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0, i32 addrspace(1)* %a)
Index: test/CodeGen/X86/statepoint-gctransition-call-lowering.ll
===================================================================
--- test/CodeGen/X86/statepoint-gctransition-call-lowering.ll
+++ test/CodeGen/X86/statepoint-gctransition-call-lowering.ll
@@ -19,7 +19,9 @@
 ; CHECK: pushq %rax
 ; CHECK: callq return_i1
 ; CHECK: popq %rcx
-; CHECK: retq
+; CHECK-NEXT: :
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
 entry:
   %safepoint_token = tail call token (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 1, i32 0, i32 0)
   %call1 = call zeroext i1 @llvm.experimental.gc.result.i1(token %safepoint_token)
@@ -31,7 +33,9 @@
 ; CHECK: pushq %rax
 ; CHECK: callq return_i32
 ; CHECK: popq %rcx
-; CHECK: retq
+; CHECK-NEXT: :
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
 entry:
   %safepoint_token = tail call token (i64, i32, i32 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i32f(i64 0, i32 0, i32 ()* @return_i32, i32 0, i32 1, i32 0, i32 0)
   %call1 = call zeroext i32 @llvm.experimental.gc.result.i32(token %safepoint_token)
@@ -43,7 +47,9 @@
 ; CHECK: pushq %rax
 ; CHECK: callq return_i32ptr
 ; CHECK: popq %rcx
-; CHECK: retq
+; CHECK-NEXT: :
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
 entry:
   %safepoint_token = tail call token (i64, i32, i32* ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_p0i32f(i64 0, i32 0, i32* ()* @return_i32ptr, i32 0, i32 1, i32 0, i32 0)
   %call1 = call i32* @llvm.experimental.gc.result.p0i32(token %safepoint_token)
@@ -55,7 +61,9 @@
 ; CHECK: pushq %rax
 ; CHECK: callq return_float
 ; CHECK: popq %rax
-; CHECK: retq
+; CHECK-NEXT: :
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
 entry:
   %safepoint_token = tail call token (i64, i32, float ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_f32f(i64 0, i32 0, float ()* @return_float, i32 0, i32 1, i32 0, i32 0)
   %call1 = call float @llvm.experimental.gc.result.f32(token %safepoint_token)
@@ -69,6 +77,8 @@
 ; CHECK: callq return_i1
 ; CHECK-NEXT: .Ltmp4:
 ; CHECK-NEXT: popq %rcx
+; CHECK-NEXT: :
+; CHECK-NEXT: .cfi_def_cfa_offset 8
 ; CHECK-NEXT: retq
 entry:
   %safepoint_token = tail call token (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 1, i32 0, i32 0, i32 addrspace(1)* %a)
@@ -93,7 +103,9 @@
 ; CHECK: pushq %rax
 ; CHECK: callq return_i32
 ; CHECK: popq %rcx
-; CHECK: retq
+; CHECK-NEXT: :
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
 entry:
   %val = alloca i32
   %safepoint_token = call token (i64, i32, i32 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i32f(i64 0, i32 0, i32 ()* @return_i32, i32 0, i32 1, i32 2, i32* %val, i64 42, i32 0)
@@ -106,7 +118,9 @@
 ; CHECK: pushq %rax
 ; CHECK: callq return_i32
 ; CHECK: popq %rcx
-; CHECK: retq
+; CHECK-NEXT: :
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
 entry:
   %val = alloca i32
   %arg = alloca i8
Index: test/CodeGen/X86/statepoint-invoke.ll
===================================================================
--- test/CodeGen/X86/statepoint-invoke.ll
+++ test/CodeGen/X86/statepoint-invoke.ll
@@ -54,7 +54,7 @@
           to label %normal_return unwind label %exceptional_return
 
 normal_return:
-  ; CHECK: popq 
+  ; CHECK: popq
   ; CHECK: retq
   %ret_val = call i64 addrspace(1)* @llvm.experimental.gc.result.p1i64(token %0)
   ret i64 addrspace(1)* %ret_val
@@ -142,6 +142,8 @@
   ; CHECK-LABEL: %normal_return
   ; CHECK: xorl %eax, %eax
   ; CHECK-NEXT: popq
+  ; CHECK-NEXT: :
+  ; CHECK-NEXT: .cfi_def_cfa_offset 8
   ; CHECK-NEXT: retq
   %null.relocated = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(token %sp1, i32 13, i32 13)
   %undef.relocated = call coldcc i64 addrspace(1)* @llvm.experimental.gc.relocate.p1i64(token %sp1, i32 14, i32 14)
@@ -169,6 +171,8 @@
 normal_return:
   ; CHECK: leaq
   ; CHECK-NEXT: popq
+  ; CHECK-NEXT: :
+  ; CHECK-NEXT: .cfi_def_cfa_offset 8
   ; CHECK-NEXT: retq
   %aa.rel = call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %sp, i32 13, i32 13)
   %aa.converted = bitcast i32 addrspace(1)* %aa.rel to i64 addrspace(1)*
@@ -177,6 +181,8 @@
 exceptional_return:
   ; CHECK: movl	$15
   ; CHECK-NEXT: popq
+  ; CHECK-NEXT: :
+  ; CHECK-NEXT: .cfi_def_cfa_offset 8
   ; CHECK-NEXT: retq
   %landing_pad = landingpad token
           cleanup
Index: test/CodeGen/X86/switch-jump-table.ll
===================================================================
--- test/CodeGen/X86/switch-jump-table.ll
+++ test/CodeGen/X86/switch-jump-table.ll
@@ -8,7 +8,7 @@
 ; CHECK-LABEL: foo:
 ; CHECK: movl 4(%esp), [[REG:%e[a-z]{2}]]
 ; CHECK: cmpl $3, [[REG]]
-; CHECK: ja .LBB0_6
+; CHECK: ja .LBB0_3
 ; CHECK-NEXT: # BB#1:
 ; CHECK-NEXT: jmpl *.LJTI0_0(,[[REG]],4)
 ; CHECK: movl $4
@@ -46,9 +46,9 @@
 ; The jump table has four entries.
 ; CHECK-LABEL: .LJTI0_0:
 ; CHECK-NEXT: .long  .LBB0_2
-; CHECK-NEXT: .long  .LBB0_3
 ; CHECK-NEXT: .long  .LBB0_4
 ; CHECK-NEXT: .long  .LBB0_5
+; CHECK-NEXT: .long  .LBB0_6
 }
 
 ; Check if branch probabilities are correctly assigned to the jump table.
Index: test/CodeGen/X86/vec_int_to_fp.ll
===================================================================
--- test/CodeGen/X86/vec_int_to_fp.ll
+++ test/CodeGen/X86/vec_int_to_fp.ll
@@ -1612,12 +1612,12 @@
 ; SSE-NEXT:    movdqa %xmm0, %xmm1
 ; SSE-NEXT:    movd %xmm1, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB39_1
-; SSE-NEXT:  # BB#2:
+; SSE-NEXT:    js .LBB39_2
+; SSE-NEXT:  # BB#1:
 ; SSE-NEXT:    xorps %xmm0, %xmm0
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm0
 ; SSE-NEXT:    jmp .LBB39_3
-; SSE-NEXT:  .LBB39_1:
+; SSE-NEXT:  .LBB39_2:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -1629,13 +1629,13 @@
 ; SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
 ; SSE-NEXT:    movd %xmm1, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB39_4
-; SSE-NEXT:  # BB#5:
+; SSE-NEXT:    js .LBB39_5
+; SSE-NEXT:  # BB#4:
 ; SSE-NEXT:    xorps %xmm1, %xmm1
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm1
 ; SSE-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
 ; SSE-NEXT:    retq
-; SSE-NEXT:  .LBB39_4:
+; SSE-NEXT:  .LBB39_5:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -1650,11 +1650,11 @@
 ; VEX:       # BB#0:
 ; VEX-NEXT:    vpextrq $1, %xmm0, %rax
 ; VEX-NEXT:    testq %rax, %rax
-; VEX-NEXT:    js .LBB39_1
-; VEX-NEXT:  # BB#2:
+; VEX-NEXT:    js .LBB39_2
+; VEX-NEXT:  # BB#1:
 ; VEX-NEXT:    vcvtsi2ssq %rax, %xmm1, %xmm1
 ; VEX-NEXT:    jmp .LBB39_3
-; VEX-NEXT:  .LBB39_1:
+; VEX-NEXT:  .LBB39_2:
 ; VEX-NEXT:    movq %rax, %rcx
 ; VEX-NEXT:    shrq %rcx
 ; VEX-NEXT:    andl $1, %eax
@@ -1664,11 +1664,11 @@
 ; VEX-NEXT:  .LBB39_3:
 ; VEX-NEXT:    vmovq %xmm0, %rax
 ; VEX-NEXT:    testq %rax, %rax
-; VEX-NEXT:    js .LBB39_4
-; VEX-NEXT:  # BB#5:
+; VEX-NEXT:    js .LBB39_5
+; VEX-NEXT:  # BB#4:
 ; VEX-NEXT:    vcvtsi2ssq %rax, %xmm2, %xmm0
 ; VEX-NEXT:    jmp .LBB39_6
-; VEX-NEXT:  .LBB39_4:
+; VEX-NEXT:  .LBB39_5:
 ; VEX-NEXT:    movq %rax, %rcx
 ; VEX-NEXT:    shrq %rcx
 ; VEX-NEXT:    andl $1, %eax
@@ -1731,12 +1731,12 @@
 ; SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
 ; SSE-NEXT:    movd %xmm1, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB40_1
-; SSE-NEXT:  # BB#2:
+; SSE-NEXT:    js .LBB40_2
+; SSE-NEXT:  # BB#1:
 ; SSE-NEXT:    xorps %xmm1, %xmm1
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm1
 ; SSE-NEXT:    jmp .LBB40_3
-; SSE-NEXT:  .LBB40_1:
+; SSE-NEXT:  .LBB40_2:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -1747,12 +1747,12 @@
 ; SSE-NEXT:  .LBB40_3:
 ; SSE-NEXT:    movd %xmm0, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB40_4
-; SSE-NEXT:  # BB#5:
+; SSE-NEXT:    js .LBB40_5
+; SSE-NEXT:  # BB#4:
 ; SSE-NEXT:    xorps %xmm0, %xmm0
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm0
 ; SSE-NEXT:    jmp .LBB40_6
-; SSE-NEXT:  .LBB40_4:
+; SSE-NEXT:  .LBB40_5:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -1769,11 +1769,11 @@
 ; VEX:       # BB#0:
 ; VEX-NEXT:    vpextrq $1, %xmm0, %rax
 ; VEX-NEXT:    testq %rax, %rax
-; VEX-NEXT:    js .LBB40_1
-; VEX-NEXT:  # BB#2:
+; VEX-NEXT:    js .LBB40_2
+; VEX-NEXT:  # BB#1:
 ; VEX-NEXT:    vcvtsi2ssq %rax, %xmm1, %xmm1
 ; VEX-NEXT:    jmp .LBB40_3
-; VEX-NEXT:  .LBB40_1:
+; VEX-NEXT:  .LBB40_2:
 ; VEX-NEXT:    movq %rax, %rcx
 ; VEX-NEXT:    shrq %rcx
 ; VEX-NEXT:    andl $1, %eax
@@ -1783,12 +1783,12 @@
 ; VEX-NEXT:  .LBB40_3:
 ; VEX-NEXT:    vmovq %xmm0, %rax
 ; VEX-NEXT:    testq %rax, %rax
-; VEX-NEXT:    js .LBB40_4
-; VEX-NEXT:  # BB#5:
+; VEX-NEXT:    js .LBB40_5
+; VEX-NEXT:  # BB#4:
 ; VEX-NEXT:    vcvtsi2ssq %rax, %xmm2, %xmm0
 ; VEX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
 ; VEX-NEXT:    retq
-; VEX-NEXT:  .LBB40_4:
+; VEX-NEXT:  .LBB40_5:
 ; VEX-NEXT:    movq %rax, %rcx
 ; VEX-NEXT:    shrq %rcx
 ; VEX-NEXT:    andl $1, %eax
@@ -1847,12 +1847,12 @@
 ; SSE-NEXT:  .LBB41_2:
 ; SSE-NEXT:    movd %xmm1, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB41_3
-; SSE-NEXT:  # BB#4:
+; SSE-NEXT:    js .LBB41_4
+; SSE-NEXT:  # BB#3:
 ; SSE-NEXT:    xorps %xmm0, %xmm0
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm0
 ; SSE-NEXT:    jmp .LBB41_5
-; SSE-NEXT:  .LBB41_3:
+; SSE-NEXT:  .LBB41_4:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -1865,12 +1865,12 @@
 ; SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
 ; SSE-NEXT:    movd %xmm1, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB41_6
-; SSE-NEXT:  # BB#7:
+; SSE-NEXT:    js .LBB41_7
+; SSE-NEXT:  # BB#6:
 ; SSE-NEXT:    xorps %xmm1, %xmm1
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm1
 ; SSE-NEXT:    jmp .LBB41_8
-; SSE-NEXT:  .LBB41_6:
+; SSE-NEXT:  .LBB41_7:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -1887,11 +1887,11 @@
 ; VEX:       # BB#0:
 ; VEX-NEXT:    vpextrq $1, %xmm0, %rax
 ; VEX-NEXT:    testq %rax, %rax
-; VEX-NEXT:    js .LBB41_1
-; VEX-NEXT:  # BB#2:
+; VEX-NEXT:    js .LBB41_2
+; VEX-NEXT:  # BB#1:
 ; VEX-NEXT:    vcvtsi2ssq %rax, %xmm1, %xmm1
 ; VEX-NEXT:    jmp .LBB41_3
-; VEX-NEXT:  .LBB41_1:
+; VEX-NEXT:  .LBB41_2:
 ; VEX-NEXT:    movq %rax, %rcx
 ; VEX-NEXT:    shrq %rcx
 ; VEX-NEXT:    andl $1, %eax
@@ -1901,11 +1901,11 @@
 ; VEX-NEXT:  .LBB41_3:
 ; VEX-NEXT:    vmovq %xmm0, %rax
 ; VEX-NEXT:    testq %rax, %rax
-; VEX-NEXT:    js .LBB41_4
-; VEX-NEXT:  # BB#5:
+; VEX-NEXT:    js .LBB41_5
+; VEX-NEXT:  # BB#4:
 ; VEX-NEXT:    vcvtsi2ssq %rax, %xmm2, %xmm0
 ; VEX-NEXT:    jmp .LBB41_6
-; VEX-NEXT:  .LBB41_4:
+; VEX-NEXT:  .LBB41_5:
 ; VEX-NEXT:    movq %rax, %rcx
 ; VEX-NEXT:    shrq %rcx
 ; VEX-NEXT:    andl $1, %eax
@@ -2147,11 +2147,11 @@
 ; SSE:       # BB#0:
 ; SSE-NEXT:    movd %xmm1, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB47_1
-; SSE-NEXT:  # BB#2:
+; SSE-NEXT:    js .LBB47_2
+; SSE-NEXT:  # BB#1:
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm3
 ; SSE-NEXT:    jmp .LBB47_3
-; SSE-NEXT:  .LBB47_1:
+; SSE-NEXT:  .LBB47_2:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -2161,11 +2161,11 @@
 ; SSE-NEXT:  .LBB47_3:
 ; SSE-NEXT:    movd %xmm0, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB47_4
-; SSE-NEXT:  # BB#5:
+; SSE-NEXT:    js .LBB47_5
+; SSE-NEXT:  # BB#4:
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm2
 ; SSE-NEXT:    jmp .LBB47_6
-; SSE-NEXT:  .LBB47_4:
+; SSE-NEXT:  .LBB47_5:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -2176,12 +2176,12 @@
 ; SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
 ; SSE-NEXT:    movd %xmm1, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB47_7
-; SSE-NEXT:  # BB#8:
+; SSE-NEXT:    js .LBB47_8
+; SSE-NEXT:  # BB#7:
 ; SSE-NEXT:    xorps %xmm1, %xmm1
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm1
 ; SSE-NEXT:    jmp .LBB47_9
-; SSE-NEXT:  .LBB47_7:
+; SSE-NEXT:  .LBB47_8:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -2194,12 +2194,12 @@
 ; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; SSE-NEXT:    movd %xmm0, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB47_10
-; SSE-NEXT:  # BB#11:
+; SSE-NEXT:    js .LBB47_11
+; SSE-NEXT:  # BB#10:
 ; SSE-NEXT:    xorps %xmm0, %xmm0
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm0
 ; SSE-NEXT:    jmp .LBB47_12
-; SSE-NEXT:  .LBB47_10:
+; SSE-NEXT:  .LBB47_11:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -2217,11 +2217,11 @@
 ; AVX1:       # BB#0:
 ; AVX1-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB47_1
-; AVX1-NEXT:  # BB#2:
+; AVX1-NEXT:    js .LBB47_2
+; AVX1-NEXT:  # BB#1:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm1, %xmm1
 ; AVX1-NEXT:    jmp .LBB47_3
-; AVX1-NEXT:  .LBB47_1:
+; AVX1-NEXT:  .LBB47_2:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -2231,11 +2231,11 @@
 ; AVX1-NEXT:  .LBB47_3:
 ; AVX1-NEXT:    vmovq %xmm0, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB47_4
-; AVX1-NEXT:  # BB#5:
+; AVX1-NEXT:    js .LBB47_5
+; AVX1-NEXT:  # BB#4:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm2, %xmm2
 ; AVX1-NEXT:    jmp .LBB47_6
-; AVX1-NEXT:  .LBB47_4:
+; AVX1-NEXT:  .LBB47_5:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -2247,11 +2247,11 @@
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
 ; AVX1-NEXT:    vmovq %xmm0, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB47_7
-; AVX1-NEXT:  # BB#8:
+; AVX1-NEXT:    js .LBB47_8
+; AVX1-NEXT:  # BB#7:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm3, %xmm2
 ; AVX1-NEXT:    jmp .LBB47_9
-; AVX1-NEXT:  .LBB47_7:
+; AVX1-NEXT:  .LBB47_8:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -2262,13 +2262,13 @@
 ; AVX1-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
 ; AVX1-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB47_10
-; AVX1-NEXT:  # BB#11:
+; AVX1-NEXT:    js .LBB47_11
+; AVX1-NEXT:  # BB#10:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm3, %xmm0
 ; AVX1-NEXT:    vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
-; AVX1-NEXT:  .LBB47_10:
+; AVX1-NEXT:  .LBB47_11:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -2283,11 +2283,11 @@
 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB47_1
-; AVX2-NEXT:  # BB#2:
+; AVX2-NEXT:    js .LBB47_2
+; AVX2-NEXT:  # BB#1:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm1, %xmm1
 ; AVX2-NEXT:    jmp .LBB47_3
-; AVX2-NEXT:  .LBB47_1:
+; AVX2-NEXT:  .LBB47_2:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
@@ -2297,11 +2297,11 @@
 ; AVX2-NEXT:  .LBB47_3:
 ; AVX2-NEXT:    vmovq %xmm0, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB47_4
-; AVX2-NEXT:  # BB#5:
+; AVX2-NEXT:    js .LBB47_5
+; AVX2-NEXT:  # BB#4:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm2, %xmm2
 ; AVX2-NEXT:    jmp .LBB47_6
-; AVX2-NEXT:  .LBB47_4:
+; AVX2-NEXT:  .LBB47_5:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
@@ -2313,11 +2313,11 @@
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; AVX2-NEXT:    vmovq %xmm0, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB47_7
-; AVX2-NEXT:  # BB#8:
+; AVX2-NEXT:    js .LBB47_8
+; AVX2-NEXT:  # BB#7:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm3, %xmm2
 ; AVX2-NEXT:    jmp .LBB47_9
-; AVX2-NEXT:  .LBB47_7:
+; AVX2-NEXT:  .LBB47_8:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
@@ -2328,13 +2328,13 @@
 ; AVX2-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
 ; AVX2-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB47_10
-; AVX2-NEXT:  # BB#11:
+; AVX2-NEXT:    js .LBB47_11
+; AVX2-NEXT:  # BB#10:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm3, %xmm0
 ; AVX2-NEXT:    vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
-; AVX2-NEXT:  .LBB47_10:
+; AVX2-NEXT:  .LBB47_11:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
@@ -3826,11 +3826,11 @@
 ; SSE-NEXT:    movdqa 16(%rdi), %xmm3
 ; SSE-NEXT:    movd %xmm3, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB76_1
-; SSE-NEXT:  # BB#2:
+; SSE-NEXT:    js .LBB76_2
+; SSE-NEXT:  # BB#1:
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm2
 ; SSE-NEXT:    jmp .LBB76_3
-; SSE-NEXT:  .LBB76_1:
+; SSE-NEXT:  .LBB76_2:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -3840,11 +3840,11 @@
 ; SSE-NEXT:  .LBB76_3:
 ; SSE-NEXT:    movd %xmm1, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB76_4
-; SSE-NEXT:  # BB#5:
+; SSE-NEXT:    js .LBB76_5
+; SSE-NEXT:  # BB#4:
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm0
 ; SSE-NEXT:    jmp .LBB76_6
-; SSE-NEXT:  .LBB76_4:
+; SSE-NEXT:  .LBB76_5:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -3855,12 +3855,12 @@
 ; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[2,3,0,1]
 ; SSE-NEXT:    movd %xmm3, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB76_7
-; SSE-NEXT:  # BB#8:
+; SSE-NEXT:    js .LBB76_8
+; SSE-NEXT:  # BB#7:
 ; SSE-NEXT:    xorps %xmm3, %xmm3
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm3
 ; SSE-NEXT:    jmp .LBB76_9
-; SSE-NEXT:  .LBB76_7:
+; SSE-NEXT:  .LBB76_8:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -3873,12 +3873,12 @@
 ; SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
 ; SSE-NEXT:    movd %xmm1, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB76_10
-; SSE-NEXT:  # BB#11:
+; SSE-NEXT:    js .LBB76_11
+; SSE-NEXT:  # BB#10:
 ; SSE-NEXT:    xorps %xmm1, %xmm1
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm1
 ; SSE-NEXT:    jmp .LBB76_12
-; SSE-NEXT:  .LBB76_10:
+; SSE-NEXT:  .LBB76_11:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -3896,11 +3896,11 @@
 ; AVX1-NEXT:    vmovdqa (%rdi), %ymm0
 ; AVX1-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB76_1
-; AVX1-NEXT:  # BB#2:
+; AVX1-NEXT:    js .LBB76_2
+; AVX1-NEXT:  # BB#1:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm1, %xmm1
 ; AVX1-NEXT:    jmp .LBB76_3
-; AVX1-NEXT:  .LBB76_1:
+; AVX1-NEXT:  .LBB76_2:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -3910,11 +3910,11 @@
 ; AVX1-NEXT:  .LBB76_3:
 ; AVX1-NEXT:    vmovq %xmm0, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB76_4
-; AVX1-NEXT:  # BB#5:
+; AVX1-NEXT:    js .LBB76_5
+; AVX1-NEXT:  # BB#4:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm2, %xmm2
 ; AVX1-NEXT:    jmp .LBB76_6
-; AVX1-NEXT:  .LBB76_4:
+; AVX1-NEXT:  .LBB76_5:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -3926,11 +3926,11 @@
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
 ; AVX1-NEXT:    vmovq %xmm0, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB76_7
-; AVX1-NEXT:  # BB#8:
+; AVX1-NEXT:    js .LBB76_8
+; AVX1-NEXT:  # BB#7:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm3, %xmm2
 ; AVX1-NEXT:    jmp .LBB76_9
-; AVX1-NEXT:  .LBB76_7:
+; AVX1-NEXT:  .LBB76_8:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -3941,13 +3941,13 @@
 ; AVX1-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
 ; AVX1-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB76_10
-; AVX1-NEXT:  # BB#11:
+; AVX1-NEXT:    js .LBB76_11
+; AVX1-NEXT:  # BB#10:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm3, %xmm0
 ; AVX1-NEXT:    vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
-; AVX1-NEXT:  .LBB76_10:
+; AVX1-NEXT:  .LBB76_11:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -3963,11 +3963,11 @@
 ; AVX2-NEXT:    vmovdqa (%rdi), %ymm0
 ; AVX2-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB76_1
-; AVX2-NEXT:  # BB#2:
+; AVX2-NEXT:    js .LBB76_2
+; AVX2-NEXT:  # BB#1:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm1, %xmm1
 ; AVX2-NEXT:    jmp .LBB76_3
-; AVX2-NEXT:  .LBB76_1:
+; AVX2-NEXT:  .LBB76_2:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
@@ -3977,11 +3977,11 @@
 ; AVX2-NEXT:  .LBB76_3:
 ; AVX2-NEXT:    vmovq %xmm0, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB76_4
-; AVX2-NEXT:  # BB#5:
+; AVX2-NEXT:    js .LBB76_5
+; AVX2-NEXT:  # BB#4:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm2, %xmm2
 ; AVX2-NEXT:    jmp .LBB76_6
-; AVX2-NEXT:  .LBB76_4:
+; AVX2-NEXT:  .LBB76_5:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
@@ -3993,11 +3993,11 @@
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; AVX2-NEXT:    vmovq %xmm0, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB76_7
-; AVX2-NEXT:  # BB#8:
+; AVX2-NEXT:    js .LBB76_8
+; AVX2-NEXT:  # BB#7:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm3, %xmm2
 ; AVX2-NEXT:    jmp .LBB76_9
-; AVX2-NEXT:  .LBB76_7:
+; AVX2-NEXT:  .LBB76_8:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
@@ -4008,13 +4008,13 @@
 ; AVX2-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
 ; AVX2-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB76_10
-; AVX2-NEXT:  # BB#11:
+; AVX2-NEXT:    js .LBB76_11
+; AVX2-NEXT:  # BB#10:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm3, %xmm0
 ; AVX2-NEXT:    vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
-; AVX2-NEXT:  .LBB76_10:
+; AVX2-NEXT:  .LBB76_11:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
@@ -4192,11 +4192,11 @@
 ; SSE-NEXT:    movdqa 48(%rdi), %xmm3
 ; SSE-NEXT:    movd %xmm5, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB80_1
-; SSE-NEXT:  # BB#2:
+; SSE-NEXT:    js .LBB80_2
+; SSE-NEXT:  # BB#1:
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm4
 ; SSE-NEXT:    jmp .LBB80_3
-; SSE-NEXT:  .LBB80_1:
+; SSE-NEXT:  .LBB80_2:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -4206,11 +4206,11 @@
 ; SSE-NEXT:  .LBB80_3:
 ; SSE-NEXT:    movd %xmm1, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB80_4
-; SSE-NEXT:  # BB#5:
+; SSE-NEXT:    js .LBB80_5
+; SSE-NEXT:  # BB#4:
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm0
 ; SSE-NEXT:    jmp .LBB80_6
-; SSE-NEXT:  .LBB80_4:
+; SSE-NEXT:  .LBB80_5:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -4221,11 +4221,11 @@
 ; SSE-NEXT:    pshufd {{.*#+}} xmm5 = xmm5[2,3,0,1]
 ; SSE-NEXT:    movd %xmm5, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB80_7
-; SSE-NEXT:  # BB#8:
+; SSE-NEXT:    js .LBB80_8
+; SSE-NEXT:  # BB#7:
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm6
 ; SSE-NEXT:    jmp .LBB80_9
-; SSE-NEXT:  .LBB80_7:
+; SSE-NEXT:  .LBB80_8:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -4236,12 +4236,12 @@
 ; SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
 ; SSE-NEXT:    movd %xmm1, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB80_10
-; SSE-NEXT:  # BB#11:
+; SSE-NEXT:    js .LBB80_11
+; SSE-NEXT:  # BB#10:
 ; SSE-NEXT:    xorps %xmm5, %xmm5
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm5
 ; SSE-NEXT:    jmp .LBB80_12
-; SSE-NEXT:  .LBB80_10:
+; SSE-NEXT:  .LBB80_11:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -4252,11 +4252,11 @@
 ; SSE-NEXT:  .LBB80_12:
 ; SSE-NEXT:    movd %xmm3, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB80_13
-; SSE-NEXT:  # BB#14:
+; SSE-NEXT:    js .LBB80_14
+; SSE-NEXT:  # BB#13:
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm7
 ; SSE-NEXT:    jmp .LBB80_15
-; SSE-NEXT:  .LBB80_13:
+; SSE-NEXT:  .LBB80_14:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -4266,12 +4266,12 @@
 ; SSE-NEXT:  .LBB80_15:
 ; SSE-NEXT:    movd %xmm2, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB80_16
-; SSE-NEXT:  # BB#17:
+; SSE-NEXT:    js .LBB80_17
+; SSE-NEXT:  # BB#16:
 ; SSE-NEXT:    xorps %xmm1, %xmm1
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm1
 ; SSE-NEXT:    jmp .LBB80_18
-; SSE-NEXT:  .LBB80_16:
+; SSE-NEXT:  .LBB80_17:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -4285,12 +4285,12 @@
 ; SSE-NEXT:    pshufd {{.*#+}} xmm3 = xmm3[2,3,0,1]
 ; SSE-NEXT:    movd %xmm3, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB80_19
-; SSE-NEXT:  # BB#20:
+; SSE-NEXT:    js .LBB80_20
+; SSE-NEXT:  # BB#19:
 ; SSE-NEXT:    xorps %xmm3, %xmm3
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm3
 ; SSE-NEXT:    jmp .LBB80_21
-; SSE-NEXT:  .LBB80_19:
+; SSE-NEXT:  .LBB80_20:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -4304,12 +4304,12 @@
 ; SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
 ; SSE-NEXT:    movd %xmm2, %rax
 ; SSE-NEXT:    testq %rax, %rax
-; SSE-NEXT:    js .LBB80_22
-; SSE-NEXT:  # BB#23:
+; SSE-NEXT:    js .LBB80_23
+; SSE-NEXT:  # BB#22:
 ; SSE-NEXT:    xorps %xmm2, %xmm2
 ; SSE-NEXT:    cvtsi2ssq %rax, %xmm2
 ; SSE-NEXT:    jmp .LBB80_24
-; SSE-NEXT:  .LBB80_22:
+; SSE-NEXT:  .LBB80_23:
 ; SSE-NEXT:    movq %rax, %rcx
 ; SSE-NEXT:    shrq %rcx
 ; SSE-NEXT:    andl $1, %eax
@@ -4328,11 +4328,11 @@
 ; AVX1-NEXT:    vmovdqa 32(%rdi), %ymm2
 ; AVX1-NEXT:    vpextrq $1, %xmm2, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB80_1
-; AVX1-NEXT:  # BB#2:
+; AVX1-NEXT:    js .LBB80_2
+; AVX1-NEXT:  # BB#1:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm1, %xmm1
 ; AVX1-NEXT:    jmp .LBB80_3
-; AVX1-NEXT:  .LBB80_1:
+; AVX1-NEXT:  .LBB80_2:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -4342,11 +4342,11 @@
 ; AVX1-NEXT:  .LBB80_3:
 ; AVX1-NEXT:    vmovq %xmm2, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB80_4
-; AVX1-NEXT:  # BB#5:
+; AVX1-NEXT:    js .LBB80_5
+; AVX1-NEXT:  # BB#4:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm3, %xmm3
 ; AVX1-NEXT:    jmp .LBB80_6
-; AVX1-NEXT:  .LBB80_4:
+; AVX1-NEXT:  .LBB80_5:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -4357,11 +4357,11 @@
 ; AVX1-NEXT:    vextractf128 $1, %ymm2, %xmm2
 ; AVX1-NEXT:    vmovq %xmm2, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB80_7
-; AVX1-NEXT:  # BB#8:
+; AVX1-NEXT:    js .LBB80_8
+; AVX1-NEXT:  # BB#7:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm4, %xmm4
 ; AVX1-NEXT:    jmp .LBB80_9
-; AVX1-NEXT:  .LBB80_7:
+; AVX1-NEXT:  .LBB80_8:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -4371,11 +4371,11 @@
 ; AVX1-NEXT:  .LBB80_9:
 ; AVX1-NEXT:    vpextrq $1, %xmm2, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB80_10
-; AVX1-NEXT:  # BB#11:
+; AVX1-NEXT:    js .LBB80_11
+; AVX1-NEXT:  # BB#10:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm5, %xmm2
 ; AVX1-NEXT:    jmp .LBB80_12
-; AVX1-NEXT:  .LBB80_10:
+; AVX1-NEXT:  .LBB80_11:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -4385,11 +4385,11 @@
 ; AVX1-NEXT:  .LBB80_12:
 ; AVX1-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB80_13
-; AVX1-NEXT:  # BB#14:
+; AVX1-NEXT:    js .LBB80_14
+; AVX1-NEXT:  # BB#13:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm5, %xmm5
 ; AVX1-NEXT:    jmp .LBB80_15
-; AVX1-NEXT:  .LBB80_13:
+; AVX1-NEXT:  .LBB80_14:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -4400,11 +4400,11 @@
 ; AVX1-NEXT:    vinsertps {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[2,3]
 ; AVX1-NEXT:    vmovq %xmm0, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB80_16
-; AVX1-NEXT:  # BB#17:
+; AVX1-NEXT:    js .LBB80_17
+; AVX1-NEXT:  # BB#16:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm6, %xmm3
 ; AVX1-NEXT:    jmp .LBB80_18
-; AVX1-NEXT:  .LBB80_16:
+; AVX1-NEXT:  .LBB80_17:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -4417,11 +4417,11 @@
 ; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm4
 ; AVX1-NEXT:    vmovq %xmm4, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB80_19
-; AVX1-NEXT:  # BB#20:
+; AVX1-NEXT:    js .LBB80_20
+; AVX1-NEXT:  # BB#19:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm6, %xmm5
 ; AVX1-NEXT:    jmp .LBB80_21
-; AVX1-NEXT:  .LBB80_19:
+; AVX1-NEXT:  .LBB80_20:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -4433,11 +4433,11 @@
 ; AVX1-NEXT:    vinsertps {{.*#+}} xmm1 = xmm3[0,1],xmm5[0],xmm3[3]
 ; AVX1-NEXT:    vpextrq $1, %xmm4, %rax
 ; AVX1-NEXT:    testq %rax, %rax
-; AVX1-NEXT:    js .LBB80_22
-; AVX1-NEXT:  # BB#23:
+; AVX1-NEXT:    js .LBB80_23
+; AVX1-NEXT:  # BB#22:
 ; AVX1-NEXT:    vcvtsi2ssq %rax, %xmm6, %xmm2
 ; AVX1-NEXT:    jmp .LBB80_24
-; AVX1-NEXT:  .LBB80_22:
+; AVX1-NEXT:  .LBB80_23:
 ; AVX1-NEXT:    movq %rax, %rcx
 ; AVX1-NEXT:    shrq %rcx
 ; AVX1-NEXT:    andl $1, %eax
@@ -4455,11 +4455,11 @@
 ; AVX2-NEXT:    vmovdqa 32(%rdi), %ymm2
 ; AVX2-NEXT:    vpextrq $1, %xmm2, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB80_1
-; AVX2-NEXT:  # BB#2:
+; AVX2-NEXT:    js .LBB80_2
+; AVX2-NEXT:  # BB#1:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm1, %xmm1
 ; AVX2-NEXT:    jmp .LBB80_3
-; AVX2-NEXT:  .LBB80_1:
+; AVX2-NEXT:  .LBB80_2:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
@@ -4469,11 +4469,11 @@
 ; AVX2-NEXT:  .LBB80_3:
 ; AVX2-NEXT:    vmovq %xmm2, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB80_4
-; AVX2-NEXT:  # BB#5:
+; AVX2-NEXT:    js .LBB80_5
+; AVX2-NEXT:  # BB#4:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm3, %xmm3
 ; AVX2-NEXT:    jmp .LBB80_6
-; AVX2-NEXT:  .LBB80_4:
+; AVX2-NEXT:  .LBB80_5:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
@@ -4484,11 +4484,11 @@
 ; AVX2-NEXT:    vextracti128 $1, %ymm2, %xmm2
 ; AVX2-NEXT:    vmovq %xmm2, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB80_7
-; AVX2-NEXT:  # BB#8:
+; AVX2-NEXT:    js .LBB80_8
+; AVX2-NEXT:  # BB#7:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm4, %xmm4
 ; AVX2-NEXT:    jmp .LBB80_9
-; AVX2-NEXT:  .LBB80_7:
+; AVX2-NEXT:  .LBB80_8:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
@@ -4498,11 +4498,11 @@
 ; AVX2-NEXT:  .LBB80_9:
 ; AVX2-NEXT:    vpextrq $1, %xmm2, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB80_10
-; AVX2-NEXT:  # BB#11:
+; AVX2-NEXT:    js .LBB80_11
+; AVX2-NEXT:  # BB#10:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm5, %xmm2
 ; AVX2-NEXT:    jmp .LBB80_12
-; AVX2-NEXT:  .LBB80_10:
+; AVX2-NEXT:  .LBB80_11:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
@@ -4512,11 +4512,11 @@
 ; AVX2-NEXT:  .LBB80_12:
 ; AVX2-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB80_13
-; AVX2-NEXT:  # BB#14:
+; AVX2-NEXT:    js .LBB80_14
+; AVX2-NEXT:  # BB#13:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm5, %xmm5
 ; AVX2-NEXT:    jmp .LBB80_15
-; AVX2-NEXT:  .LBB80_13:
+; AVX2-NEXT:  .LBB80_14:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
@@ -4527,11 +4527,11 @@
 ; AVX2-NEXT:    vinsertps {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[2,3]
 ; AVX2-NEXT:    vmovq %xmm0, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB80_16
-; AVX2-NEXT:  # BB#17:
+; AVX2-NEXT:    js .LBB80_17
+; AVX2-NEXT:  # BB#16:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm6, %xmm3
 ; AVX2-NEXT:    jmp .LBB80_18
-; AVX2-NEXT:  .LBB80_16:
+; AVX2-NEXT:  .LBB80_17:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
@@ -4544,11 +4544,11 @@
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm4
 ; AVX2-NEXT:    vmovq %xmm4, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB80_19
-; AVX2-NEXT:  # BB#20:
+; AVX2-NEXT:    js .LBB80_20
+; AVX2-NEXT:  # BB#19:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm6, %xmm5
 ; AVX2-NEXT:    jmp .LBB80_21
-; AVX2-NEXT:  .LBB80_19:
+; AVX2-NEXT:  .LBB80_20:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
@@ -4560,11 +4560,11 @@
 ; AVX2-NEXT:    vinsertps {{.*#+}} xmm1 = xmm3[0,1],xmm5[0],xmm3[3]
 ; AVX2-NEXT:    vpextrq $1, %xmm4, %rax
 ; AVX2-NEXT:    testq %rax, %rax
-; AVX2-NEXT:    js .LBB80_22
-; AVX2-NEXT:  # BB#23:
+; AVX2-NEXT:    js .LBB80_23
+; AVX2-NEXT:  # BB#22:
 ; AVX2-NEXT:    vcvtsi2ssq %rax, %xmm6, %xmm2
 ; AVX2-NEXT:    jmp .LBB80_24
-; AVX2-NEXT:  .LBB80_22:
+; AVX2-NEXT:  .LBB80_23:
 ; AVX2-NEXT:    movq %rax, %rcx
 ; AVX2-NEXT:    shrq %rcx
 ; AVX2-NEXT:    andl $1, %eax
Index: test/CodeGen/X86/vector-sext.ll
===================================================================
--- test/CodeGen/X86/vector-sext.ll
+++ test/CodeGen/X86/vector-sext.ll
@@ -3281,11 +3281,23 @@
 ; AVX1-NEXT:    vpinsrw $7, %ebp, %xmm1, %xmm1
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
 ; AVX1-NEXT:    popq %rbx
+; AVX1-NEXT:  .Lcfi12:
+; AVX1-NEXT:    .cfi_def_cfa_offset 48
 ; AVX1-NEXT:    popq %r12
+; AVX1-NEXT:  .Lcfi13:
+; AVX1-NEXT:    .cfi_def_cfa_offset 40
 ; AVX1-NEXT:    popq %r13
+; AVX1-NEXT:  .Lcfi14:
+; AVX1-NEXT:    .cfi_def_cfa_offset 32
 ; AVX1-NEXT:    popq %r14
+; AVX1-NEXT:  .Lcfi15:
+; AVX1-NEXT:    .cfi_def_cfa_offset 24
 ; AVX1-NEXT:    popq %r15
+; AVX1-NEXT:  .Lcfi16:
+; AVX1-NEXT:    .cfi_def_cfa_offset 16
 ; AVX1-NEXT:    popq %rbp
+; AVX1-NEXT:  .Lcfi17:
+; AVX1-NEXT:    .cfi_def_cfa_offset 8
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: load_sext_16i1_to_16i16:
@@ -3384,11 +3396,23 @@
 ; AVX2-NEXT:    vpinsrw $7, %ebp, %xmm1, %xmm1
 ; AVX2-NEXT:    vinserti128 $1, %xmm0, %ymm1, %ymm0
 ; AVX2-NEXT:    popq %rbx
+; AVX2-NEXT:  .Lcfi12:
+; AVX2-NEXT:    .cfi_def_cfa_offset 48
 ; AVX2-NEXT:    popq %r12
+; AVX2-NEXT:  .Lcfi13:
+; AVX2-NEXT:    .cfi_def_cfa_offset 40
 ; AVX2-NEXT:    popq %r13
+; AVX2-NEXT:  .Lcfi14:
+; AVX2-NEXT:    .cfi_def_cfa_offset 32
 ; AVX2-NEXT:    popq %r14
+; AVX2-NEXT:  .Lcfi15:
+; AVX2-NEXT:    .cfi_def_cfa_offset 24
 ; AVX2-NEXT:    popq %r15
+; AVX2-NEXT:  .Lcfi16:
+; AVX2-NEXT:    .cfi_def_cfa_offset 16
 ; AVX2-NEXT:    popq %rbp
+; AVX2-NEXT:  .Lcfi17:
+; AVX2-NEXT:    .cfi_def_cfa_offset 8
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: load_sext_16i1_to_16i16:
@@ -4771,6 +4795,8 @@
 ; X32-SSE41-NEXT:    pmovsxbw %xmm0, %xmm0
 ; X32-SSE41-NEXT:    movd %xmm0, %eax
 ; X32-SSE41-NEXT:    popl %ecx
+; X32-SSE41-NEXT:  .Lcfi1:
+; X32-SSE41-NEXT:    .cfi_def_cfa_offset 4
 ; X32-SSE41-NEXT:    retl
 entry:
   %Shuf = shufflevector <16 x i8> %A, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
Index: test/CodeGen/X86/vector-shuffle-avx512.ll
===================================================================
--- test/CodeGen/X86/vector-shuffle-avx512.ll
+++ test/CodeGen/X86/vector-shuffle-avx512.ll
@@ -628,6 +628,8 @@
 ; KNL32-NEXT:    vpblendvb %ymm3, 8(%ebp), %ymm1, %ymm1
 ; KNL32-NEXT:    movl %ebp, %esp
 ; KNL32-NEXT:    popl %ebp
+; KNL32-NEXT:  .Lcfi3:
+; KNL32-NEXT:    .cfi_def_cfa %esp, 4
 ; KNL32-NEXT:    retl
 entry:
   %0 = shufflevector <64 x i8> %A, <64 x i8> %W, <64 x i32>  <i32 64, i32 1, i32 66, i32 3, i32 68, i32 5, i32 70, i32 7, i32 72, i32 9, i32 74, i32 11, i32 76, i32 13, i32 78, i32 15, i32 80, i32 17, i32 82, i32 19, i32 84, i32 21, i32 86, i32 23, i32 88, i32 25, i32 90, i32 27, i32 92, i32 29, i32 94, i32 31, i32 96, i32 33, i32 98, i32 35, i32 100, i32 37, i32 102, i32 39, i32 104, i32 41, i32 106, i32 43, i32 108, i32 45, i32 110, i32 47, i32 112, i32 49, i32 114, i32 51, i32 116, i32 53, i32 118, i32 55, i32 120, i32 57, i32 122, i32 59, i32 124, i32 61, i32 126, i32 63>
@@ -658,12 +660,12 @@
 ; KNL32-LABEL: test_mm512_mask_blend_epi16:
 ; KNL32:       # BB#0: # %entry
 ; KNL32-NEXT:    pushl %ebp
-; KNL32-NEXT:  .Lcfi3:
-; KNL32-NEXT:    .cfi_def_cfa_offset 8
 ; KNL32-NEXT:  .Lcfi4:
+; KNL32-NEXT:    .cfi_def_cfa_offset 8
+; KNL32-NEXT:  .Lcfi5:
 ; KNL32-NEXT:    .cfi_offset %ebp, -8
 ; KNL32-NEXT:    movl %esp, %ebp
-; KNL32-NEXT:  .Lcfi5:
+; KNL32-NEXT:  .Lcfi6:
 ; KNL32-NEXT:    .cfi_def_cfa_register %ebp
 ; KNL32-NEXT:    andl $-32, %esp
 ; KNL32-NEXT:    subl $32, %esp
@@ -671,6 +673,8 @@
 ; KNL32-NEXT:    vpblendw {{.*#+}} ymm1 = mem[0],ymm1[1],mem[2],ymm1[3],mem[4],ymm1[5],mem[6],ymm1[7],mem[8],ymm1[9],mem[10],ymm1[11],mem[12],ymm1[13],mem[14],ymm1[15]
 ; KNL32-NEXT:    movl %ebp, %esp
 ; KNL32-NEXT:    popl %ebp
+; KNL32-NEXT:  .Lcfi7:
+; KNL32-NEXT:    .cfi_def_cfa %esp, 4
 ; KNL32-NEXT:    retl
 entry:
   %0 = shufflevector <32 x i16> %A, <32 x i16> %W, <32 x i32>  <i32 32, i32 1, i32 34, i32 3, i32 36, i32 5, i32 38, i32 7, i32 40, i32 9, i32 42, i32 11, i32 44, i32 13, i32 46, i32 15, i32 48, i32 17, i32 50, i32 19, i32 52, i32 21, i32 54, i32 23, i32 56, i32 25, i32 58, i32 27, i32 60, i32 29, i32 62, i32 31>
Index: test/CodeGen/X86/vector-shuffle-v1.ll
===================================================================
--- test/CodeGen/X86/vector-shuffle-v1.ll
+++ test/CodeGen/X86/vector-shuffle-v1.ll
@@ -433,6 +433,8 @@
 ; AVX512F-NEXT:    orq %rcx, %rax
 ; AVX512F-NEXT:    movq %rbp, %rsp
 ; AVX512F-NEXT:    popq %rbp
+; AVX512F-NEXT:  .Lcfi3:
+; AVX512F-NEXT:    .cfi_def_cfa %rsp, 8
 ; AVX512F-NEXT:    vzeroupper
 ; AVX512F-NEXT:    retq
 ;
Index: test/CodeGen/X86/wide-integer-cmp.ll
===================================================================
--- test/CodeGen/X86/wide-integer-cmp.ll
+++ test/CodeGen/X86/wide-integer-cmp.ll
@@ -108,10 +108,16 @@
 ; CHECK-NEXT:  # BB#1: # %bb1
 ; CHECK-NEXT:    movl $1, %eax
 ; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:  .Lcfi2:
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-NEXT:    retl
 ; CHECK-NEXT:  .LBB4_2: # %bb2
+; CHECK-NEXT:  .Lcfi3:
+; CHECK-NEXT:  	 .cfi_def_cfa %esp, 8
 ; CHECK-NEXT:    movl $2, %eax
 ; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:  .Lcfi4:
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-NEXT:    retl
 entry:
   %cmp = icmp slt i128 %a, %b
Index: test/CodeGen/X86/x86-framelowering-trap.ll
===================================================================
--- test/CodeGen/X86/x86-framelowering-trap.ll
+++ test/CodeGen/X86/x86-framelowering-trap.ll
@@ -6,6 +6,8 @@
 ; CHECK: pushq
 ; CHECK: ud2
 ; CHECK-NEXT: popq
+; CHECK-NEXT: :
+; CHECK-NEXT: .cfi_def_cfa_offset 8
 ; CHECK-NEXT: retq
 define void @bar() {
 entry: