Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td +++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td @@ -901,6 +901,12 @@ opName#" $sdst, $src0", pattern >; +// 32-bit input, 64-bit output. +multiclass SOP1_64_32 pattern> : SOP1_m < + op, opName, (outs SReg_64:$sdst), (ins SSrc_32:$src0), + opName#" $sdst, $src0", pattern +>; + class SOP2_Pseudo pattern> : SOP2, SIMCInstr { @@ -964,19 +970,26 @@ opName#" $sdst, $src0, $src1", pattern >; +class SOPC_Base op, RegisterOperand rc0, RegisterOperand rc1, + string opName, list pattern = []> : SOPC < + op, (outs), (ins rc0:$src0, rc1:$src1), + opName#" $src0, $src1", pattern > { + let Defs = [SCC]; +} class SOPC_Helper op, RegisterOperand rc, ValueType vt, - string opName, PatLeaf cond> : SOPC < - op, (outs), (ins rc:$src0, rc:$src1), - opName#" $src0, $src1", + string opName, PatLeaf cond> : SOPC_Base < + op, rc, rc, opName, [(set SCC, (si_setcc_uniform vt:$src0, vt:$src1, cond))] > { - let Defs = [SCC]; } -class SOPC_32 op, string opName, PatLeaf cond = COND_NULL> +class SOPC_CMP_32 op, string opName, PatLeaf cond = COND_NULL> : SOPC_Helper; -class SOPC_64 op, string opName, PatLeaf cond = COND_NULL> - : SOPC_Helper; +class SOPC_32 op, string opName, list pattern = []> + : SOPC_Base; + +class SOPC_64_32 op, string opName, list pattern = []> + : SOPC_Base; class SOPK_Pseudo pattern> : SOPK , Index: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td @@ -168,13 +168,13 @@ >; defm S_BITSET0_B32 : SOP1_32 , "s_bitset0_b32", []>; -defm S_BITSET0_B64 : SOP1_64 , "s_bitset0_b64", []>; +defm S_BITSET0_B64 : SOP1_64_32 , "s_bitset0_b64", []>; defm S_BITSET1_B32 : SOP1_32 , "s_bitset1_b32", []>; -defm S_BITSET1_B64 : SOP1_64 , "s_bitset1_b64", []>; +defm S_BITSET1_B64 : SOP1_64_32 , "s_bitset1_b64", []>; defm S_GETPC_B64 : SOP1_64_0 , "s_getpc_b64", []>; defm S_SETPC_B64 : SOP1_1 , "s_setpc_b64", []>; defm S_SWAPPC_B64 : SOP1_64 , "s_swappc_b64", []>; -defm S_RFE_B64 : SOP1_64 , "s_rfe_b64", []>; +defm S_RFE_B64 : SOP1_1 , "s_rfe_b64", []>; let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in { @@ -344,23 +344,23 @@ // SOPC Instructions //===----------------------------------------------------------------------===// -def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "s_cmp_eq_i32", COND_EQ>; -def S_CMP_LG_I32 : SOPC_32 <0x00000001, "s_cmp_lg_i32", COND_NE>; -def S_CMP_GT_I32 : SOPC_32 <0x00000002, "s_cmp_gt_i32", COND_SGT>; -def S_CMP_GE_I32 : SOPC_32 <0x00000003, "s_cmp_ge_i32", COND_SGE>; -def S_CMP_LT_I32 : SOPC_32 <0x00000004, "s_cmp_lt_i32", COND_SLT>; -def S_CMP_LE_I32 : SOPC_32 <0x00000005, "s_cmp_le_i32", COND_SLE>; -def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "s_cmp_eq_u32", COND_EQ>; -def S_CMP_LG_U32 : SOPC_32 <0x00000007, "s_cmp_lg_u32", COND_NE >; -def S_CMP_GT_U32 : SOPC_32 <0x00000008, "s_cmp_gt_u32", COND_UGT>; -def S_CMP_GE_U32 : SOPC_32 <0x00000009, "s_cmp_ge_u32", COND_UGE>; -def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "s_cmp_lt_u32", COND_ULT>; -def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "s_cmp_le_u32", COND_ULE>; -////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "s_bitcmp0_b32", []>; -////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "s_bitcmp1_b32", []>; -////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "s_bitcmp0_b64", []>; -////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "s_bitcmp1_b64", []>; -//def S_SETVSKIP : SOPC_ <0x00000010, "s_setvskip", []>; +def S_CMP_EQ_I32 : SOPC_CMP_32 <0x00000000, "s_cmp_eq_i32", COND_EQ>; +def S_CMP_LG_I32 : SOPC_CMP_32 <0x00000001, "s_cmp_lg_i32", COND_NE>; +def S_CMP_GT_I32 : SOPC_CMP_32 <0x00000002, "s_cmp_gt_i32", COND_SGT>; +def S_CMP_GE_I32 : SOPC_CMP_32 <0x00000003, "s_cmp_ge_i32", COND_SGE>; +def S_CMP_LT_I32 : SOPC_CMP_32 <0x00000004, "s_cmp_lt_i32", COND_SLT>; +def S_CMP_LE_I32 : SOPC_CMP_32 <0x00000005, "s_cmp_le_i32", COND_SLE>; +def S_CMP_EQ_U32 : SOPC_CMP_32 <0x00000006, "s_cmp_eq_u32", COND_EQ>; +def S_CMP_LG_U32 : SOPC_CMP_32 <0x00000007, "s_cmp_lg_u32", COND_NE >; +def S_CMP_GT_U32 : SOPC_CMP_32 <0x00000008, "s_cmp_gt_u32", COND_UGT>; +def S_CMP_GE_U32 : SOPC_CMP_32 <0x00000009, "s_cmp_ge_u32", COND_UGE>; +def S_CMP_LT_U32 : SOPC_CMP_32 <0x0000000a, "s_cmp_lt_u32", COND_ULT>; +def S_CMP_LE_U32 : SOPC_CMP_32 <0x0000000b, "s_cmp_le_u32", COND_ULE>; +def S_BITCMP0_B32 : SOPC_32 <0x0000000c, "s_bitcmp0_b32">; +def S_BITCMP1_B32 : SOPC_32 <0x0000000d, "s_bitcmp1_b32">; +def S_BITCMP0_B64 : SOPC_64_32 <0x0000000e, "s_bitcmp0_b64">; +def S_BITCMP1_B64 : SOPC_64_32 <0x0000000f, "s_bitcmp1_b64">; +def S_SETVSKIP : SOPC_32 <0x00000010, "s_setvskip">; //===----------------------------------------------------------------------===// // SOPK Instructions Index: llvm/trunk/test/MC/AMDGPU/smem.s =================================================================== --- llvm/trunk/test/MC/AMDGPU/smem.s +++ llvm/trunk/test/MC/AMDGPU/smem.s @@ -3,9 +3,13 @@ // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefix=NOSI %s s_dcache_wb -; VI: s_dcache_wb ; encoding: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00] -; NOSI: error: instruction not supported on this GPU +// VI: s_dcache_wb ; encoding: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00] +// NOSI: error: instruction not supported on this GPU s_dcache_wb_vol -; VI: s_dcache_wb_vol ; encoding: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00] -; NOSI: error: instruction not supported on this GPU +// VI: s_dcache_wb_vol ; encoding: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00] +// NOSI: error: instruction not supported on this GPU + +s_memrealtime s[4:5] +// VI: s_memrealtime s[4:5] ; encoding: [0x00,0x01,0x94,0xc0,0x00,0x00,0x00,0x00] +// NOSI: error: instruction not supported on this GPU Index: llvm/trunk/test/MC/AMDGPU/smrd.s =================================================================== --- llvm/trunk/test/MC/AMDGPU/smrd.s +++ llvm/trunk/test/MC/AMDGPU/smrd.s @@ -80,6 +80,58 @@ // GCN: s_load_dwordx16 s[88:103], s[2:3], s4 ; encoding: [0x04,0x02,0x2c,0xc1] // NOVI: error: invalid operand for instruction +s_buffer_load_dword s1, s[4:7], 1 +// GCN: s_buffer_load_dword s1, s[4:7], 0x1 ; encoding: [0x01,0x85,0x00,0xc2] +// VI: s_buffer_load_dword s1, s[4:7], 0x1 ; encoding: [0x42,0x00,0x22,0xc0,0x01,0x00,0x00,0x00] + +s_buffer_load_dword s1, s[4:7], s4 +// GCN: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x04,0x84,0x00,0xc2] +// VI: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x42,0x00,0x20,0xc0,0x04,0x00,0x00,0x00] + +s_buffer_load_dwordx2 s[8:9], s[4:7], 1 +// GCN: s_buffer_load_dwordx2 s[8:9], s[4:7], 0x1 ; encoding: [0x01,0x05,0x44,0xc2] +// VI: s_buffer_load_dwordx2 s[8:9], s[4:7], 0x1 ; encoding: [0x02,0x02,0x26,0xc0,0x01,0x00,0x00,0x00] + +s_buffer_load_dwordx2 s[8:9], s[4:7], s4 +// GCN: s_buffer_load_dwordx2 s[8:9], s[4:7], s4 ; encoding: [0x04,0x04,0x44,0xc2] +// VI: s_buffer_load_dwordx2 s[8:9], s[4:7], s4 ; encoding: [0x02,0x02,0x24,0xc0,0x04,0x00,0x00,0x00] + +s_buffer_load_dwordx4 s[8:11], s[4:7], 1 +// GCN: s_buffer_load_dwordx4 s[8:11], s[4:7], 0x1 ; encoding: [0x01,0x05,0x84,0xc2] +// VI: s_buffer_load_dwordx4 s[8:11], s[4:7], 0x1 ; encoding: [0x02,0x02,0x2a,0xc0,0x01,0x00,0x00,0x00] + +s_buffer_load_dwordx4 s[8:11], s[4:7], s4 +// GCN: s_buffer_load_dwordx4 s[8:11], s[4:7], s4 ; encoding: [0x04,0x04,0x84,0xc2] +// VI: s_buffer_load_dwordx4 s[8:11], s[4:7], s4 ; encoding: [0x02,0x02,0x28,0xc0,0x04,0x00,0x00,0x00] + +s_buffer_load_dwordx4 s[100:103], s[4:7], s4 +// GCN: s_buffer_load_dwordx4 s[100:103], s[4:7], s4 ; encoding: [0x04,0x04,0xb2,0xc2] +// NOVI: error: invalid operand for instruction + +s_buffer_load_dwordx8 s[8:15], s[4:7], 1 +// GCN: s_buffer_load_dwordx8 s[8:15], s[4:7], 0x1 ; encoding: [0x01,0x05,0xc4,0xc2] +// VI: s_buffer_load_dwordx8 s[8:15], s[4:7], 0x1 ; encoding: [0x02,0x02,0x2e,0xc0,0x01,0x00,0x00,0x00] + +s_buffer_load_dwordx8 s[8:15], s[4:7], s4 +// GCN: s_buffer_load_dwordx8 s[8:15], s[4:7], s4 ; encoding: [0x04,0x04,0xc4,0xc2] +// VI: s_buffer_load_dwordx8 s[8:15], s[4:7], s4 ; encoding: [0x02,0x02,0x2c,0xc0,0x04,0x00,0x00,0x00] + +s_buffer_load_dwordx8 s[96:103], s[4:7], s4 +// GCN: s_buffer_load_dwordx8 s[96:103], s[4:7], s4 ; encoding: [0x04,0x04,0xf0,0xc2] +// NOVI: error: invalid operand for instruction + +s_buffer_load_dwordx16 s[16:31], s[4:7], 1 +// GCN: s_buffer_load_dwordx16 s[16:31], s[4:7], 0x1 ; encoding: [0x01,0x05,0x08,0xc3] +// VI: s_buffer_load_dwordx16 s[16:31], s[4:7], 0x1 ; encoding: [0x02,0x04,0x32,0xc0,0x01,0x00,0x00,0x00] + +s_buffer_load_dwordx16 s[16:31], s[4:7], s4 +// GCN: s_buffer_load_dwordx16 s[16:31], s[4:7], s4 ; encoding: [0x04,0x04,0x08,0xc3] +// VI: s_buffer_load_dwordx16 s[16:31], s[4:7], s4 ; encoding: [0x02,0x04,0x30,0xc0,0x04,0x00,0x00,0x00] + +s_buffer_load_dwordx16 s[88:103], s[4:7], s4 +// GCN: s_buffer_load_dwordx16 s[88:103], s[4:7], s4 ; encoding: [0x04,0x04,0x2c,0xc3] +// NOVI: error: invalid operand for instruction + s_dcache_inv // GCN: s_dcache_inv ; encoding: [0x00,0x00,0xc0,0xc7] // VI: s_dcache_inv ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00] @@ -89,6 +141,6 @@ // NOSI: error: instruction not supported on this GPU // VI: s_dcache_inv_vol ; encoding: [0x00,0x00,0x88,0xc0,0x00,0x00,0x00,0x00] -s_memtime s[0:1] -// GCN: s_memtime s[0:1] ; encoding: [0x00,0x00,0x80,0xc7] -// VI: s_memtime s[0:1] ; encoding: [0x00,0x00,0x90,0xc0,0x00,0x00,0x00,0x00] +s_memtime s[4:5] +// GCN: s_memtime s[4:5] ; encoding: [0x00,0x00,0x82,0xc7] +// VI: s_memtime s[4:5] ; encoding: [0x00,0x01,0x90,0xc0,0x00,0x00,0x00,0x00] Index: llvm/trunk/test/MC/AMDGPU/sop1.s =================================================================== --- llvm/trunk/test/MC/AMDGPU/sop1.s +++ llvm/trunk/test/MC/AMDGPU/sop1.s @@ -121,14 +121,14 @@ s_bitset0_b32 s1, s2 // CHECK: s_bitset0_b32 s1, s2 ; encoding: [0x02,0x1b,0x81,0xbe] -s_bitset0_b64 s[2:3], s[4:5] -// CHECK: s_bitset0_b64 s[2:3], s[4:5] ; encoding: [0x04,0x1c,0x82,0xbe] +s_bitset0_b64 s[2:3], s4 +// CHECK: s_bitset0_b64 s[2:3], s4 ; encoding: [0x04,0x1c,0x82,0xbe] s_bitset1_b32 s1, s2 // CHECK: s_bitset1_b32 s1, s2 ; encoding: [0x02,0x1d,0x81,0xbe] -s_bitset1_b64 s[2:3], s[4:5] -// CHECK: s_bitset1_b64 s[2:3], s[4:5] ; encoding: [0x04,0x1e,0x82,0xbe] +s_bitset1_b64 s[2:3], s4 +// CHECK: s_bitset1_b64 s[2:3], s4 ; encoding: [0x04,0x1e,0x82,0xbe] s_getpc_b64 s[2:3] // CHECK: s_getpc_b64 s[2:3] ; encoding: [0x00,0x1f,0x82,0xbe] @@ -139,8 +139,8 @@ s_swappc_b64 s[2:3], s[4:5] // CHECK: s_swappc_b64 s[2:3], s[4:5] ; encoding: [0x04,0x21,0x82,0xbe] -s_rfe_b64 s[2:3], s[4:5] -// CHECK: s_rfe_b64 s[2:3], s[4:5] ; encoding: [0x04,0x22,0x82,0xbe] +s_rfe_b64 s[4:5] +// CHECK: s_rfe_b64 s[4:5] ; encoding: [0x04,0x22,0x80,0xbe] s_and_saveexec_b64 s[2:3], s[4:5] // CHECK: s_and_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x24,0x82,0xbe] Index: llvm/trunk/test/MC/AMDGPU/sopc.s =================================================================== --- llvm/trunk/test/MC/AMDGPU/sopc.s +++ llvm/trunk/test/MC/AMDGPU/sopc.s @@ -1,9 +1,58 @@ // RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s -// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s //===----------------------------------------------------------------------===// -// Instructions +// SOPC Instructions //===----------------------------------------------------------------------===// s_cmp_eq_i32 s1, s2 // CHECK: s_cmp_eq_i32 s1, s2 ; encoding: [0x01,0x02,0x00,0xbf] + +s_cmp_lg_i32 s1, s2 +// CHECK: s_cmp_lg_i32 s1, s2 ; encoding: [0x01,0x02,0x01,0xbf] + +s_cmp_gt_i32 s1, s2 +// CHECK: s_cmp_gt_i32 s1, s2 ; encoding: [0x01,0x02,0x02,0xbf] + +s_cmp_ge_i32 s1, s2 +// CHECK: s_cmp_ge_i32 s1, s2 ; encoding: [0x01,0x02,0x03,0xbf] + +s_cmp_lt_i32 s1, s2 +// CHECK: s_cmp_lt_i32 s1, s2 ; encoding: [0x01,0x02,0x04,0xbf] + +s_cmp_le_i32 s1, s2 +// CHECK: s_cmp_le_i32 s1, s2 ; encoding: [0x01,0x02,0x05,0xbf] + +s_cmp_eq_u32 s1, s2 +// CHECK: s_cmp_eq_u32 s1, s2 ; encoding: [0x01,0x02,0x06,0xbf] + +s_cmp_lg_u32 s1, s2 +// CHECK: s_cmp_lg_u32 s1, s2 ; encoding: [0x01,0x02,0x07,0xbf] + +s_cmp_gt_u32 s1, s2 +// CHECK: s_cmp_gt_u32 s1, s2 ; encoding: [0x01,0x02,0x08,0xbf] + +s_cmp_ge_u32 s1, s2 +// CHECK: s_cmp_ge_u32 s1, s2 ; encoding: [0x01,0x02,0x09,0xbf] + +s_cmp_lt_u32 s1, s2 +// CHECK: s_cmp_lt_u32 s1, s2 ; encoding: [0x01,0x02,0x0a,0xbf] + +s_cmp_le_u32 s1, s2 +// CHECK: s_cmp_le_u32 s1, s2 ; encoding: [0x01,0x02,0x0b,0xbf] + +s_bitcmp0_b32 s1, s2 +// CHECK: s_bitcmp0_b32 s1, s2 ; encoding: [0x01,0x02,0x0c,0xbf] + +s_bitcmp1_b32 s1, s2 +// CHECK: s_bitcmp1_b32 s1, s2 ; encoding: [0x01,0x02,0x0d,0xbf] + +s_bitcmp0_b64 s[2:3], s4 +// CHECK: s_bitcmp0_b64 s[2:3], s4 ; encoding: [0x02,0x04,0x0e,0xbf] + +s_bitcmp1_b64 s[2:3], s4 +// CHECK: s_bitcmp1_b64 s[2:3], s4 ; encoding: [0x02,0x04,0x0f,0xbf] + +s_setvskip s3, s5 +// CHECK: s_setvskip s3, s5 ; encoding: [0x03,0x05,0x10,0xbf]