Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrInfo.td +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -945,18 +945,18 @@ MMR6Arch<"sll16">; class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>, MMR6Arch<"srl16">; -class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"srl16">, +class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"break16">, MicroMipsR6Inst16; class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, - MMR6Arch<"srl16">, MicroMipsR6Inst16, IsAsCheapAsAMove; -class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"srl16">, + MMR6Arch<"li16">, MicroMipsR6Inst16, IsAsCheapAsAMove; +class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">, MicroMipsR6Inst16; class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">, MicroMipsR6Inst16; class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>, - MMR6Arch<"sdbbp16">, MicroMipsR6Inst16; + MMR6Arch<"subu16">, MicroMipsR6Inst16; class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>, - MMR6Arch<"sdbbp16">; + MMR6Arch<"xor16">; class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst { dag OutOperandList = (outs GPR32Opnd:$rt); Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -972,11 +972,20 @@ (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>; def : MipsPat<(shl GPR32:$src, immZExt5:$imm), (SLL_MM GPR32:$src, immZExt5:$imm)>; +def : MipsPat<(shl GPR32:$lhs, GPR32:$rhs), + (SLLV_MM GPR32:$lhs, GPR32:$rhs)>; def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm), (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>; def : MipsPat<(srl GPR32:$src, immZExt5:$imm), (SRL_MM GPR32:$src, immZExt5:$imm)>; +def : MipsPat<(srl GPR32:$lhs, GPR32:$rhs), + (SRLV_MM GPR32:$lhs, GPR32:$rhs)>; + +def : MipsPat<(sra GPR32:$src, immZExt5:$imm), + (SRA_MM GPR32:$src, immZExt5:$imm)>; +def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs), + (SRAV_MM GPR32:$lhs, GPR32:$rhs)>; def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr), (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>; @@ -1023,4 +1032,22 @@ (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : MipsInstAlias<"tne $rs, $rt", (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; +def : MipsInstAlias<"sll $rd, $rt, $rs", + (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; +def : MipsInstAlias<"sra $rd, $rt, $rs", + (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; +def : MipsInstAlias<"srl $rd, $rt, $rs", + (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; +def : MipsInstAlias<"sll $rd, $rt", + (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; +def : MipsInstAlias<"sra $rd, $rt", + (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; +def : MipsInstAlias<"srl $rd, $rt", + (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; +def : MipsInstAlias<"sll $rd, $shamt", + (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; +def : MipsInstAlias<"sra $rd, $shamt", + (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; +def : MipsInstAlias<"srl $rd, $shamt", + (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; } Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1694,7 +1694,6 @@ immZExt5>, SRA_FM<0, 0>; def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl, immZExt5>, SRA_FM<2, 0>; -} def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra, immZExt5>, SRA_FM<3, 0>; def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>, @@ -1703,6 +1702,7 @@ SRLV_FM<6, 0>; def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, SRLV_FM<7, 0>; +} // Rotate Instructions def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, @@ -2245,8 +2245,6 @@ def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; } -def : MipsInstAlias<"sll $rd, $rt, $rs", - (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; def : MipsInstAlias<"sub, $rd, $rs, $imm", (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6; @@ -2258,10 +2256,14 @@ InvertedImOperand:$imm), 0>; def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm), 0>; -def : MipsInstAlias<"sra $rd, $rt, $rs", - (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; -def : MipsInstAlias<"srl $rd, $rt, $rs", - (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; +let AdditionalPredicates = [NotInMicroMips] in { + def : MipsInstAlias<"sll $rd, $rt, $rs", + (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; + def : MipsInstAlias<"sra $rd, $rt, $rs", + (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; + def : MipsInstAlias<"srl $rd, $rt, $rs", + (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; +} def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6; def : MipsInstAlias<"sync", (SYNC 0), 1>, ISA_MIPS2; Index: test/CodeGen/Mips/llvm-ir/ashr.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/ashr.ll +++ test/CodeGen/Mips/llvm-ir/ashr.ll @@ -37,6 +37,10 @@ ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=GP64 \ ; RUN: -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) { entry: @@ -53,7 +57,9 @@ ; ALL-LABEL: ashr_i8: ; FIXME: The andi instruction is redundant. - ; ALL: andi $[[T0:[0-9]+]], $5, 255 + ; GP32: andi $[[T0:[0-9]+]], $5, 255 + ; GP64: andi $[[T0:[0-9]+]], $5, 255 + ; MM: andi16 $[[T0:[0-9]+]], $5, 255 ; ALL: srav $2, $4, $[[T0]] %r = ashr i8 %a, %b @@ -65,7 +71,9 @@ ; ALL-LABEL: ashr_i16: ; FIXME: The andi instruction is redundant. - ; ALL: andi $[[T0:[0-9]+]], $5, 65535 + ; GP32: andi $[[T0:[0-9]+]], $5, 65535 + ; GP64: andi $[[T0:[0-9]+]], $5, 65535 + ; MM: andi16 $[[T0:[0-9]+]], $5, 65535 ; ALL: srav $2, $4, $[[T0]] %r = ashr i16 %a, %b @@ -133,6 +141,32 @@ ; GP64: dsrav $2, $4, $5 + ; MMR3: srlv $[[T0:[0-9]+]], $5, $7 + ; MMR3: sll16 $[[T1:[0-9]+]], $4, 1 + ; MMR3: not16 $[[T2:[0-9]+]], $7 + ; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR3: srav $[[T5:[0-9]+]], $4, $7 + ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 + ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; MMR3: sra $[[T8:[0-9]+]], $4, 31 + ; MMR3: movn $2, $[[T8]], $[[T6]] + + ; MMR6: srav $[[T0:[0-9]+]], $4, $7 + ; MMR6: andi16 $[[T1:[0-9]+]], $7, 32 + ; MMR6: seleqz $[[T2:[0-9]+]], $[[T0]], $[[T1]] + ; MMR6: sra $[[T3:[0-9]+]], $4, 31 + ; MMR6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]] + ; MMR6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]] + ; MMR6: srlv $[[T6:[0-9]+]], $5, $7 + ; MMR6: not $[[T7:[0-9]+]], $7 + ; MMR6: sll16 $[[T8:[0-9]+]], $4, 1 + ; MMR6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]] + ; MMR6: or16 $[[T10:[0-9]+]], $[[T6]] + ; MMR6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]] + ; MMR6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]] + ; MMR6: or $3, $[[T12]], $[[T11]] + %r = ashr i64 %a, %b ret i64 %r } @@ -192,6 +226,8 @@ ; 64R6: jr $ra ; 64R6: or $3, $[[T13]], $[[T12]] + ; MM: lw $25, %call16(__ashrti3)($2) + %r = ashr i128 %a, %b ret i128 %r } Index: test/CodeGen/Mips/llvm-ir/lshr.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/lshr.ll +++ test/CodeGen/Mips/llvm-ir/lshr.ll @@ -37,6 +37,10 @@ ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=GP64 \ ; RUN: -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6 define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) { entry: @@ -53,7 +57,9 @@ ; ALL-LABEL: lshr_i8: ; ALL: srlv $[[T0:[0-9]+]], $4, $5 - ; ALL: andi $2, $[[T0]], 255 + ; GP32: andi $2, $[[T0]], 255 + ; GP64: andi $2, $[[T0]], 255 + ; MM: andi16 $2, $[[T0]], 255 %r = lshr i8 %a, %b ret i8 %r @@ -64,7 +70,9 @@ ; ALL-LABEL: lshr_i16: ; ALL: srlv $[[T0:[0-9]+]], $4, $5 - ; ALL: andi $2, $[[T0]], 65535 + ; GP32: andi $2, $[[T0]], 65535 + ; GP64: andi $2, $[[T0]], 65535 + ; MM: andi16 $2, $[[T0]], 65535 %r = lshr i16 %a, %b ret i16 %r @@ -127,6 +135,29 @@ ; GP64: dsrlv $2, $4, $5 + ; MMR3: srlv $[[T0:[0-9]+]], $5, $7 + ; MMR3: sll16 $[[T1:[0-9]+]], $4, 1 + ; MMR3: not16 $[[T2:[0-9]+]], $7 + ; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR3: srlv $[[T5:[0-9]+]], $4, $7 + ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 + ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; MMR3: lui $[[T8:[0-9]+]], 0 + ; MMR3: movn $2, $[[T8]], $[[T6]] + + ; MMR6: srlv $[[T0:[0-9]+]], $5, $7 + ; MMR6: not $[[T1:[0-9]+]], $7 + ; MMR6: sll16 $[[T2:[0-9]+]], $4, 1 + ; MMR6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32 + ; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]] + ; MMR6: srlv $[[T7:[0-9]+]], $4, $7 + ; MMR6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] + ; MMR6: or $3, $[[T8]], $[[T6]] + ; MMR6: seleqz $2, $[[T7]], $[[T5]] + %r = lshr i64 %a, %b ret i64 %r } @@ -182,6 +213,8 @@ ; 64R6: jr $ra ; 64R6: seleqz $2, $[[T9]], $[[T7]] + ; MM: lw $25, %call16(__lshrti3)($2) + %r = lshr i128 %a, %b ret i128 %r } Index: test/CodeGen/Mips/llvm-ir/shl.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/shl.ll +++ test/CodeGen/Mips/llvm-ir/shl.ll @@ -37,6 +37,10 @@ ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=GP64 \ ; RUN: -check-prefix=64R6 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6 define signext i1 @shl_i1(i1 signext %a, i1 signext %b) { entry: @@ -61,6 +65,10 @@ ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] ; R2-R6: seb $2, $[[T1]] + ; MM: andi16 $[[T0:[0-9]+]], $5, 255 + ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]] + ; MM: seb $2, $[[T1]] + %r = shl i8 %a, %b ret i8 %r } @@ -78,6 +86,10 @@ ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] ; R2-R6: seh $2, $[[T1]] + ; MM: andi16 $[[T0:[0-9]+]], $5, 65535 + ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]] + ; MM: seh $2, $[[T1]] + %r = shl i16 %a, %b ret i16 %r } @@ -139,6 +151,29 @@ ; GP64: dsllv $2, $4, $5 + ; MMR3: sllv $[[T0:[0-9]+]], $4, $7 + ; MMR3: srl16 $[[T1:[0-9]+]], $5, 1 + ; MMR3: not16 $[[T2:[0-9]+]], $7 + ; MMR3: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR3: sllv $[[T5:[0-9]+]], $5, $7 + ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 + ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; MMR3: lui $[[T8:[0-9]+]], 0 + ; MMR3: movn $3, $[[T8]], $[[T6]] + + ; MMR6: sllv $[[T0:[0-9]+]], $4, $7 + ; MMR6: not $[[T1:[0-9]+]], $7 + ; MMR6: srl16 $[[T2:[0-9]+]], $5, 1 + ; MMR6: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32 + ; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]] + ; MMR6: sllv $[[T7:[0-9]+]], $5, $7 + ; MMR6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] + ; MMR6: or $2, $[[T8]], $[[T6]] + ; MMR6: seleqz $3, $[[T7]], $[[T5]] + %r = shl i64 %a, %b ret i64 %r } @@ -194,6 +229,8 @@ ; 64R6: jr $ra ; 64R6: seleqz $3, $[[T9]], $[[T7]] + ; MM: lw $25, %call16(__ashlti3)($2) + %r = shl i128 %a, %b ret i128 %r } Index: test/CodeGen/Mips/micromips-shift.ll =================================================================== --- test/CodeGen/Mips/micromips-shift.ll +++ test/CodeGen/Mips/micromips-shift.ll @@ -1,5 +1,7 @@ ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s +; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s | FileCheck %s @a = global i32 10, align 4 @b = global i32 0, align 4 Index: test/MC/Disassembler/Mips/micromips32r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -276,3 +276,8 @@ 0x00 0x22 0x08 0xf4 # CHECK: mfhc0 $1, $2, 1 0x54 0x06 0x30 0x3b # CHECK: mfhc1 $zero, $f6 0x02 0xf0 0x8d 0x3c # CHECK: mfhc2 $23, $16 +0x00 0x65 0x10 0x10 # CHECK: sllv $2, $3, $5 +0x00 0x83 0x38 0x80 # CHECK: sra $4, $3, 7 +0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5 +0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7 +0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5 Index: test/MC/Disassembler/Mips/micromips64r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -215,3 +215,9 @@ 0x5f 0x02 0x46 0x9f # CHECK: daddiu $24, $2, 18079 0x5c 0x63 0xff 0xfb # CHECK: daddiu $3, $3, -5 0x5c 0x64 0xff 0xfb # CHECK: daddiu $3, $4, -5 +0x00 0x83 0x38 0x00 # CHECK: sll $4, $3, 7 +0x00 0x65 0x10 0x10 # CHECK: sllv $2, $3, $5 +0x00 0x83 0x38 0x80 # CHECK: sra $4, $3, 7 +0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5 +0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7 +0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5 Index: test/MC/Mips/micromips-shift-instructions.s =================================================================== --- test/MC/Mips/micromips-shift-instructions.s +++ test/MC/Mips/micromips-shift-instructions.s @@ -15,6 +15,15 @@ # CHECK-EL: srlv $2, $3, $5 # encoding: [0x65,0x00,0x50,0x10] # CHECK-EL: rotr $9, $6, 7 # encoding: [0x26,0x01,0xc0,0x38] # CHECK-EL: rotrv $9, $6, $7 # encoding: [0xc7,0x00,0xd0,0x48] +# CHECK-EL: sllv $2, $3, $5 # encoding: [0x65,0x00,0x10,0x10] +# CHECK-EL: srav $2, $3, $5 # encoding: [0x65,0x00,0x90,0x10] +# CHECK-EL: srlv $2, $3, $5 # encoding: [0x65,0x00,0x50,0x10] +# CHECK-EL: sllv $2, $2, $3 # encoding: [0x43,0x00,0x10,0x10] +# CHECK-EL: srav $2, $2, $3 # encoding: [0x43,0x00,0x90,0x10] +# CHECK-EL: srlv $2, $2, $3 # encoding: [0x43,0x00,0x50,0x10] +# CHECK-EL: sll $3, $3, 7 # encoding: [0x63,0x00,0x00,0x38] +# CHECK-EL: sra $3, $3, 7 # encoding: [0x63,0x00,0x80,0x38] +# CHECK-EL: srl $3, $3, 7 # encoding: [0x63,0x00,0x40,0x38] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -26,6 +35,15 @@ # CHECK-EB: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50] # CHECK-EB: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0] # CHECK-EB: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0] +# CHECK-EB: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10] +# CHECK-EB: srav $2, $3, $5 # encoding: [0x00,0x65,0x10,0x90] +# CHECK-EB: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50] +# CHECK-EB: sllv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x10] +# CHECK-EB: srav $2, $2, $3 # encoding: [0x00,0x43,0x10,0x90] +# CHECK-EB: srlv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x50] +# CHECK-EB: sll $3, $3, 7 # encoding: [0x00,0x63,0x38,0x00] +# CHECK-EB: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80] +# CHECK-EB: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40] sll $4, $3, 7 sllv $2, $3, $5 sra $4, $3, 7 @@ -34,3 +52,12 @@ srlv $2, $3, $5 rotr $9, $6, 7 rotrv $9, $6, $7 + sll $2, $3, $5 + sra $2, $3, $5 + srl $2, $3, $5 + sll $2, $3 + sra $2, $3 + srl $2, $3 + sll $3, 7 + sra $3, 7 + srl $3, 7 Index: test/MC/Mips/micromips/invalid.s =================================================================== --- test/MC/Mips/micromips/invalid.s +++ test/MC/Mips/micromips/invalid.s @@ -52,3 +52,8 @@ sync 32 # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate swe $2, -513($gp) # CHECK: :[[@LINE]]:11: error: expected memory with $gp and 9-bit signed offset swe $2, 512($gp) # CHECK: :[[@LINE]]:11: error: expected memory with $gp and 9-bit signed offset + sll $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + sll $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + sra $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + sra $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + srl $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate Index: test/MC/Mips/micromips32r6/invalid.s =================================================================== --- test/MC/Mips/micromips32r6/invalid.s +++ test/MC/Mips/micromips32r6/invalid.s @@ -113,11 +113,23 @@ swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate - mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate - mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate - mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate - mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate - mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate - mfhc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate - mfhc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mfhc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mfhc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + sll $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + sll $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + sra $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + sra $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + srl $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + srl $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + sll $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + sll $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + sra $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + sra $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + srl $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + srl $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate Index: test/MC/Mips/micromips32r6/valid.s =================================================================== --- test/MC/Mips/micromips32r6/valid.s +++ test/MC/Mips/micromips32r6/valid.s @@ -275,3 +275,17 @@ mfhc0 $1, $2, 1 # CHECK: mfhc0 $1, $2, 1 # encoding: [0x00,0x22,0x08,0xf4] mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b] mfhc2 $23, $16 # CHECK: mfhc2 $23, $16 # encoding: [0x02,0xf0,0x8d,0x3c] + sllv $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10] + sra $4, $3, 7 # CHECK: sra $4, $3, 7 # encoding: [0x00,0x83,0x38,0x80] + srav $2, $3, $5 # CHECK: srav $2, $3, $5 # encoding: [0x00,0x65,0x10,0x90] + srl $4, $3, 7 # CHECK: srl $4, $3, 7 # encoding: [0x00,0x83,0x38,0x40] + srlv $2, $3, $5 # CHECK: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50] + sll $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10] + sra $2, $3, $5 # CHECK: srav $2, $3, $5 # encoding: [0x00,0x65,0x10,0x90] + srl $2, $3, $5 # CHECK: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50] + sll $2, $3 # CHECK: sllv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x10] + sra $2, $3 # CHECK: srav $2, $2, $3 # encoding: [0x00,0x43,0x10,0x90] + srl $2, $3 # CHECK: srlv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x50] + sll $3, 7 # CHECK: sll $3, $3, 7 # encoding: [0x00,0x63,0x38,0x00] + sra $3, 7 # CHECK: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80] + srl $3, 7 # CHECK: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40] Index: test/MC/Mips/micromips64r6/invalid.s =================================================================== --- test/MC/Mips/micromips64r6/invalid.s +++ test/MC/Mips/micromips64r6/invalid.s @@ -146,3 +146,15 @@ dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate + sll $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + sll $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + sra $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + sra $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + srl $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + srl $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + sll $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + sll $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + sra $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + sra $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + srl $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + srl $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate Index: test/MC/Mips/micromips64r6/valid.s =================================================================== --- test/MC/Mips/micromips64r6/valid.s +++ test/MC/Mips/micromips64r6/valid.s @@ -198,5 +198,19 @@ daddu $24, $2, 18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x5f,0x02,0x46,0x9f] dsubu $3, 5 # CHECK: daddiu $3, $3, -5 # encoding: [0x5c,0x63,0xff,0xfb] dsubu $3, $4, 5 # CHECK: daddiu $3, $4, -5 # encoding: [0x5c,0x64,0xff,0xfb] + sllv $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10] + sra $4, $3, 7 # CHECK: sra $4, $3, 7 # encoding: [0x00,0x83,0x38,0x80] + srav $2, $3, $5 # CHECK: srav $2, $3, $5 # encoding: [0x00,0x65,0x10,0x90] + srl $4, $3, 7 # CHECK: srl $4, $3, 7 # encoding: [0x00,0x83,0x38,0x40] + srlv $2, $3, $5 # CHECK: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50] + sll $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10] + sra $2, $3, $5 # CHECK: srav $2, $3, $5 # encoding: [0x00,0x65,0x10,0x90] + srl $2, $3, $5 # CHECK: srlv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x50] + sll $2, $3 # CHECK: sllv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x10] + sra $2, $3 # CHECK: srav $2, $2, $3 # encoding: [0x00,0x43,0x10,0x90] + srl $2, $3 # CHECK: srlv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x50] + sll $3, 7 # CHECK: sll $3, $3, 7 # encoding: [0x00,0x63,0x38,0x00] + sra $3, 7 # CHECK: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80] + srl $3, 7 # CHECK: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40] 1: