Index: lib/Target/Sparc/AsmParser/SparcAsmParser.cpp =================================================================== --- lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -636,8 +636,12 @@ return Error(Loc, "unexpected token"); } - while (getLexer().is(AsmToken::Comma)) { - Parser.Lex(); // Eat the comma. + while (getLexer().is(AsmToken::Comma) || getLexer().is(AsmToken::Plus)) { + if (getLexer().is(AsmToken::Plus)) { + // Plus tokens are significant in software_traps (p83, sparcv8.pdf). We must capture them. + Operands.push_back(SparcOperand::CreateToken("+", Parser.getTok().getLoc())); + } + Parser.Lex(); // Eat the comma or plus. // Parse and remember the operand. if (parseOperand(Operands, Name) != MatchOperand_Success) { SMLoc Loc = getLexer().getLoc(); Index: lib/Target/Sparc/Disassembler/SparcDisassembler.cpp =================================================================== --- lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -311,6 +311,8 @@ const void *Decoder); static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeTRAP(MCInst &Inst, unsigned insn, uint64_t Address, + const void *Decoder); #include "SparcGenDisassemblerTables.inc" @@ -346,6 +348,18 @@ return MCDisassembler::Fail; // Calling the auto-generated decoder function. + + if (STI.getFeatureBits()[Sparc::FeatureV9]) + { + Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI); + } + else + { + Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI); + } + if (Result != MCDisassembler::Fail) + return Result; + Result = decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI); @@ -619,3 +633,36 @@ return MCDisassembler::Success; } + +static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address, + const void *Decoder) { + + unsigned rs1 = fieldFromInstruction(insn, 14, 5); + unsigned isImm = fieldFromInstruction(insn, 13, 1); + unsigned cc =fieldFromInstruction(insn, 25, 4); + unsigned rs2 = 0; + unsigned imm7 = 0; + if (isImm) + imm7 = fieldFromInstruction(insn, 0, 7); + else + rs2 = fieldFromInstruction(insn, 0, 5); + + // Decode RS1. + DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + + // Decode RS1 | IMM7. + if (isImm) + MI.addOperand(MCOperand::createImm(imm7)); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + } + + // Decode CC + MI.addOperand(MCOperand::createImm(cc)); + + return MCDisassembler::Success; +} Index: lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp =================================================================== --- lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp +++ lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp @@ -115,8 +115,21 @@ } if (MO.isImm()) { - O << (int)MO.getImm(); - return; + switch (MI->getOpcode()) { + default: + O << (int)MO.getImm(); + return; + + case SP::TICCri: // Fall through + case SP::TICCrr: // Fall through + case SP::TRAPri: // Fall through + case SP::TRAPrr: // Fall through + case SP::TXCCri: // Fall through + case SP::TXCCrr: // Fall through + // Only seven-bit values up to 127. + O << ((int) MO.getImm() & 0x7f); + return; + } } assert(MO.isExpr() && "Unknown operand kind in printOperand"); @@ -166,6 +179,11 @@ // Make sure CC is a fp conditional flag. CC = (CC < 16) ? (CC + 16) : CC; break; + case SP::CBCOND: + case SP::CBCONDA: + // Make sure CC is a cp conditional flag. + CC = (CC < 32) ? (CC + 32) : CC; + break; } O << SPARCCondCodeToString((SPCC::CondCodes)CC); } Index: lib/Target/Sparc/Sparc.h =================================================================== --- lib/Target/Sparc/Sparc.h +++ lib/Target/Sparc/Sparc.h @@ -72,7 +72,24 @@ FCC_UGE = 12+16, // Unordered or Greater or Equal FCC_LE = 13+16, // Less or Equal FCC_ULE = 14+16, // Unordered or Less or Equal - FCC_O = 15+16 // Ordered + FCC_O = 15+16, // Ordered + + CPCC_A = 8+32, // Always + CPCC_N = 0+32, // Never + CPCC_3 = 7+32, + CPCC_2 = 6+32, + CPCC_23 = 5+32, + CPCC_1 = 4+32, + CPCC_13 = 3+32, + CPCC_12 = 2+32, + CPCC_123 = 1+32, + CPCC_0 = 9+32, + CPCC_03 = 10+32, + CPCC_02 = 11+32, + CPCC_023 = 12+32, + CPCC_01 = 13+32, + CPCC_013 = 14+32, + CPCC_012 = 15+32 }; } @@ -110,6 +127,22 @@ case SPCC::FCC_LE: return "le"; case SPCC::FCC_ULE: return "ule"; case SPCC::FCC_O: return "o"; + case SPCC::CPCC_A: return "a"; + case SPCC::CPCC_N: return "n"; + case SPCC::CPCC_3: return "3"; + case SPCC::CPCC_2: return "2"; + case SPCC::CPCC_23: return "23"; + case SPCC::CPCC_1: return "1"; + case SPCC::CPCC_13: return "13"; + case SPCC::CPCC_12: return "12"; + case SPCC::CPCC_123: return "123"; + case SPCC::CPCC_0: return "0"; + case SPCC::CPCC_03: return "03"; + case SPCC::CPCC_02: return "02"; + case SPCC::CPCC_023: return "023"; + case SPCC::CPCC_01: return "01"; + case SPCC::CPCC_013: return "013"; + case SPCC::CPCC_012: return "012"; } llvm_unreachable("Invalid cond code"); } Index: lib/Target/Sparc/SparcInstrAliases.td =================================================================== --- lib/Target/Sparc/SparcInstrAliases.td +++ lib/Target/Sparc/SparcInstrAliases.td @@ -136,59 +136,68 @@ (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, Requires<[Is64Bit, HasHardQuad]>; - // t %icc, rs1 + rs2 - def : InstAlias, - Requires<[HasV9]>; - // t %icc, rs => t %icc, G0 + rs def : InstAlias, Requires<[HasV9]>; - - // t %xcc, rs1 + rs2 - def : InstAlias, + // t %icc, rs1 + rs2 + def : InstAlias, Requires<[HasV9]>; + // t %xcc, rs => t %xcc, G0 + rs def : InstAlias, Requires<[HasV9]>; + // t %xcc, rs1 + rs2 + def : InstAlias, + Requires<[HasV9]>; - // t rs1 + rs2 => t %icc, rs1 + rs2 - def : InstAlias; // t rs=> t %icc, G0 + rs2 - def : InstAlias; + //def : InstAlias, + // Requires<[HasV9]>; + + // t rs1 + rs2 => t %icc, rs1 + rs2 + //def : InstAlias, + // Requires<[HasV9]>; - // t %icc, rs1 + imm - def : InstAlias, - Requires<[HasV9]>; // t %icc, imm => t %icc, G0 + imm def : InstAlias, Requires<[HasV9]>; - // t %xcc, rs1 + imm - def : InstAlias, + // t %icc, rs1 + imm + def : InstAlias, Requires<[HasV9]>; // t %xcc, imm => t %xcc, G0 + imm def : InstAlias, Requires<[HasV9]>; + // t %xcc, rs1 + imm + def : InstAlias, + Requires<[HasV9]>; - // t rs1 + imm => t %icc, rs1 + imm + // t imm => t G0 + imm + def : InstAlias; + + // t rs1 + imm => t rs1 + imm def : InstAlias; + (TRAPri IntRegs:$rs1, i32imm:$imm, condVal)>; - // t imm => t %icc, G0 + imm - def : InstAlias; + // t rs1 => t G0 + rs1 + def : InstAlias; + // t rs1 + rs2 + def : InstAlias; } @@ -244,14 +253,23 @@ Requires<[HasV9, HasHardQuad]>; } + +// Instruction aliases for co-processor conditional branches. +multiclass cp_cond_alias { + + // cb $imm + def : InstAlias; + + // cb,a $imm + def : InstAlias; +} + defm : int_cond_alias<"a", 0b1000>; -defm : int_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual defm : int_cond_alias<"n", 0b0000>; defm : int_cond_alias<"ne", 0b1001>; -defm : int_cond_alias<"nz", 0b1001>; // same as ne defm : int_cond_alias<"e", 0b0001>; -defm : int_cond_alias<"eq", 0b0001>; // same as e -defm : int_cond_alias<"z", 0b0001>; // same as e defm : int_cond_alias<"g", 0b1010>; defm : int_cond_alias<"le", 0b0010>; defm : int_cond_alias<"ge", 0b1011>; @@ -259,16 +277,21 @@ defm : int_cond_alias<"gu", 0b1100>; defm : int_cond_alias<"leu", 0b0100>; defm : int_cond_alias<"cc", 0b1101>; -defm : int_cond_alias<"geu", 0b1101>; // same as cc defm : int_cond_alias<"cs", 0b0101>; -defm : int_cond_alias<"lu", 0b0101>; // same as cs defm : int_cond_alias<"pos", 0b1110>; defm : int_cond_alias<"neg", 0b0110>; defm : int_cond_alias<"vc", 0b1111>; defm : int_cond_alias<"vs", 0b0111>; - +let EmitPriority = 0 in +{ + defm : int_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual + defm : int_cond_alias<"nz", 0b1001>; // same as ne + defm : int_cond_alias<"eq", 0b0001>; // same as e + defm : int_cond_alias<"z", 0b0001>; // same as e + defm : int_cond_alias<"geu", 0b1101>; // same as cc + defm : int_cond_alias<"lu", 0b0101>; // same as cs +} defm : fp_cond_alias<"a", 0b1000>; -defm : fp_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual defm : fp_cond_alias<"n", 0b0000>; defm : fp_cond_alias<"u", 0b0111>; defm : fp_cond_alias<"g", 0b0110>; @@ -277,15 +300,37 @@ defm : fp_cond_alias<"ul", 0b0011>; defm : fp_cond_alias<"lg", 0b0010>; defm : fp_cond_alias<"ne", 0b0001>; -defm : fp_cond_alias<"nz", 0b0001>; // same as ne defm : fp_cond_alias<"e", 0b1001>; -defm : fp_cond_alias<"z", 0b1001>; // same as e defm : fp_cond_alias<"ue", 0b1010>; defm : fp_cond_alias<"ge", 0b1011>; defm : fp_cond_alias<"uge", 0b1100>; defm : fp_cond_alias<"le", 0b1101>; defm : fp_cond_alias<"ule", 0b1110>; defm : fp_cond_alias<"o", 0b1111>; +let EmitPriority = 0 in +{ + defm : fp_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual + defm : fp_cond_alias<"nz", 0b0001>; // same as ne + defm : fp_cond_alias<"z", 0b1001>; // same as e +} + +defm : cp_cond_alias<"a", 0b1000>; +defm : cp_cond_alias<"n", 0b0000>; +defm : cp_cond_alias<"3", 0b0111>; +defm : cp_cond_alias<"2", 0b0110>; +defm : cp_cond_alias<"23", 0b0101>; +defm : cp_cond_alias<"1", 0b0100>; +defm : cp_cond_alias<"13", 0b0011>; +defm : cp_cond_alias<"12", 0b0010>; +defm : cp_cond_alias<"123", 0b0001>; +defm : cp_cond_alias<"0", 0b1001>; +defm : cp_cond_alias<"03", 0b1010>; +defm : cp_cond_alias<"02", 0b1011>; +defm : cp_cond_alias<"023", 0b1100>; +defm : cp_cond_alias<"01", 0b1101>; +defm : cp_cond_alias<"013", 0b1110>; +defm : cp_cond_alias<"012", 0b1111>; +let EmitPriority = 0 in defm : cp_cond_alias<"", 0b1000>; // same as a; gnu asm, not in manual // Section A.3 Synthetic Instructions Index: lib/Target/Sparc/SparcInstrInfo.cpp =================================================================== --- lib/Target/Sparc/SparcInstrInfo.cpp +++ lib/Target/Sparc/SparcInstrInfo.cpp @@ -119,6 +119,28 @@ case SPCC::FCC_UE: return SPCC::FCC_LG; case SPCC::FCC_NE: return SPCC::FCC_E; case SPCC::FCC_E: return SPCC::FCC_NE; + + case SPCC::CPCC_A: return SPCC::CPCC_N; + case SPCC::CPCC_N: return SPCC::CPCC_A; + case SPCC::CPCC_3: // Fall through + case SPCC::CPCC_2: // Fall through + case SPCC::CPCC_23: // Fall through + case SPCC::CPCC_1: // Fall through + case SPCC::CPCC_13: // Fall through + case SPCC::CPCC_12: // Fall through + case SPCC::CPCC_123: // Fall through + case SPCC::CPCC_0: // Fall through + case SPCC::CPCC_03: // Fall through + case SPCC::CPCC_02: // Fall through + case SPCC::CPCC_023: // Fall through + case SPCC::CPCC_01: // Fall through + case SPCC::CPCC_013: // Fall through + case SPCC::CPCC_012: + // "Opposite" code is not meaningful, as we don't know + // what the CoProc condition means here. The cond-code will + // only be used in inline assembler, so this code should + // not be reached in a normal compilation pass. + llvm_unreachable("Meaningless inversion of co-processor cond code"); } llvm_unreachable("Invalid cond code"); } Index: lib/Target/Sparc/SparcInstrInfo.td =================================================================== --- lib/Target/Sparc/SparcInstrInfo.td +++ lib/Target/Sparc/SparcInstrInfo.td @@ -891,6 +891,17 @@ // Section B.27 - Trap on Integer Condition Codes Instruction +// conditional branch class: +let DecoderNamespace = "SparcV8", DecoderMethod = "DecodeTRAP", hasSideEffects = 1, Uses = [ICC], cc = 0b00 in +{ + def TRAPrr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2, + CCOp:$cond), + "t$cond $rs1 + $rs2", []>; + def TRAPri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm, + CCOp:$cond), + "t$cond $rs1 + $imm", []>; +} + multiclass TRAP { def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond), @@ -900,9 +911,10 @@ !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), []>; } -let hasSideEffects = 1, Uses = [ICC], cc = 0b00 in +let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in defm TICC : TRAP<"%icc">; + let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>; Index: test/MC/Disassembler/Sparc/sparc-v9.txt =================================================================== --- test/MC/Disassembler/Sparc/sparc-v9.txt +++ test/MC/Disassembler/Sparc/sparc-v9.txt @@ -2,3 +2,117 @@ # CHECK: popc %g1, %g2 0x85 0x70 0x00 0x01 + +# CHECK: ta %icc, %i5 +0x91 0xd0 0x00 0x1d + +# CHECK: ta %icc, 82 +0x91 0xd0 0x20 0x52 + +# CHECK: ta %icc, %g1 + %i2 +0x91 0xd0 0x40 0x1a + +# CHECK: ta %icc, %i5 + 41 +0x91 0xd7 0x60 0x29 + +# CHECK: tn %icc, %i5 +0x81 0xd0 0x00 0x1d + +# CHECK: tne %icc, 82 +0x93 0xd0 0x20 0x52 + +# CHECK: te %icc, %g1 + %i2 +0x83 0xd0 0x40 0x1a + +# CHECK: tg %icc, %i5 + 41 +0x95 0xd7 0x60 0x29 + +# CHECK: tle %icc, %i5 +0x85 0xd0 0x00 0x1d + +# CHECK: tge %icc, 82 +0x97 0xd0 0x20 0x52 + +# CHECK: tl %icc, %g1 + %i2 +0x87 0xd0 0x40 0x1a + +# CHECK: tgu %icc, %i5 + 41 +0x99 0xd7 0x60 0x29 + +# CHECK: tleu %icc, %i5 +0x89 0xd0 0x00 0x1d + +# CHECK: tcc %icc, 82 +0x9b 0xd0 0x20 0x52 + +# CHECK: tcs %icc, %g1 + %i2 +0x8b 0xd0 0x40 0x1a + +# CHECK: tpos %icc, %i5 + 41 +0x9d 0xd7 0x60 0x29 + +# CHECK: tneg %icc, %i5 +0x8d 0xd0 0x00 0x1d + +# CHECK: tvc %icc, 82 +0x9f 0xd0 0x20 0x52 + +# CHECK: tvs %icc, %g1 + %i2 +0x8f 0xd0 0x40 0x1a + +# CHECK: ta %xcc, %i5 +0x91 0xd0 0x10 0x1d + +# CHECK: ta %xcc, 82 +0x91 0xd0 0x30 0x52 + +# CHECK: ta %xcc, %g1 + %i2 +0x91 0xd0 0x50 0x1a + +# CHECK: ta %xcc, %i5 + 41 +0x91 0xd7 0x70 0x29 + +# CHECK: tn %xcc, %i5 +0x81 0xd0 0x10 0x1d + +# CHECK: tne %xcc, 82 +0x93 0xd0 0x30 0x52 + +# CHECK: te %xcc, %g1 + %i2 +0x83 0xd0 0x50 0x1a + +# CHECK: tg %xcc, %i5 + 41 +0x95 0xd7 0x70 0x29 + +# CHECK: tle %xcc, %i5 +0x85 0xd0 0x10 0x1d + +# CHECK: tge %xcc, 82 +0x97 0xd0 0x30 0x52 + +# CHECK: tl %xcc, %g1 + %i2 +0x87 0xd0 0x50 0x1a + +# CHECK: tgu %xcc, %i5 + 41 +0x99 0xd7 0x70 0x29 + +# CHECK: tleu %xcc, %i5 +0x89 0xd0 0x10 0x1d + +# CHECK: tcc %xcc, 82 +0x9b 0xd0 0x30 0x52 + +# CHECK: tcs %xcc, %g1 + %i2 +0x8b 0xd0 0x50 0x1a + +# CHECK: tpos %xcc, %i5 + 41 +0x9d 0xd7 0x70 0x29 + +# CHECK: tneg %xcc, %i5 +0x8d 0xd0 0x10 0x1d + +# CHECK: tvc %xcc, 82 +0x9f 0xd0 0x30 0x52 + +# CHECK: tvs %xcc, %g1 + %i2 +0x8f 0xd0 0x50 0x1a \ No newline at end of file Index: test/MC/Disassembler/Sparc/sparc.txt =================================================================== --- test/MC/Disassembler/Sparc/sparc.txt +++ test/MC/Disassembler/Sparc/sparc.txt @@ -168,6 +168,51 @@ # CHECK: fbo 4194303 0x1f 0xbf 0xff 0xff +# CHECK: cba 4194303 +0x11 0xff 0xff 0xff + +# CHECK: cbn 4194303 +0x01 0xff 0xff 0xff + +# CHECK: cb3 4194303 +0x0f 0xff 0xff 0xff + +# CHECK: cb2 4194303 +0x0d 0xff 0xff 0xff + +# CHECK: cb23 4194303 +0x0b 0xff 0xff 0xff + +# CHECK: cb1 4194303 +0x09 0xff 0xff 0xff + +# CHECK: cb13 4194303 +0x07 0xff 0xff 0xff + +# CHECK: cb12 4194303 +0x05 0xff 0xff 0xff + +# CHECK: cb123 4194303 +0x03 0xff 0xff 0xff + +# CHECK: cb03 4194303 +0x15 0xff 0xff 0xff + +# CHECK: cb02 4194303 +0x17 0xff 0xff 0xff + +# CHECK: cb023 4194303 +0x19 0xff 0xff 0xff + +# CHECK: cb01 4194303 +0x1b 0xff 0xff 0xff + +# CHECK: cb013 4194303 +0x1d 0xff 0xff 0xff + +# CHECK: cb012 4194303 +0x1f 0xff 0xff 0xff + # CHECK: restore 0x81 0xe8 0x00 0x00 @@ -187,16 +232,73 @@ 0x00 0x00 0x00 0x0c # CHECK: jmp %g1+12 -0x81,0xc0,0x60,0x0c +0x81 0xc0 0x60 0x0c # CHECK: retl 0x81 0xc3 0xe0 0x08 # CHECK: ret -0x81,0xc7,0xe0,0x08 +0x81 0xc7 0xe0 0x08 # CHECK: rett %i7+8 0x81 0xcf 0xe0 0x08 # CHECK: stbar 0x81 0x43 0xc0 0x00 + +# CHECK: ta %i5 +0x91 0xd0 0x00 0x1d + +# CHECK: ta 82 +0x91 0xd0 0x20 0x52 + +# CHECK: ta %g1 + %i2 +0x91 0xd0 0x40 0x1a + +# CHECK: ta %i5 + 41 +0x91 0xd7 0x60 0x29 + +# CHECK: tn %i5 +0x81 0xd0 0x00 0x1d + +# CHECK: tne 82 +0x93 0xd0 0x20 0x52 + +# CHECK: te %g1 + %i2 +0x83 0xd0 0x40 0x1a + +# CHECK: tg %i5 + 41 +0x95 0xd7 0x60 0x29 + +# CHECK: tle %i5 +0x85 0xd0 0x00 0x1d + +# CHECK: tge 82 +0x97 0xd0 0x20 0x52 + +# CHECK: tl %g1 + %i2 +0x87 0xd0 0x40 0x1a + +# CHECK: tgu %i5 + 41 +0x99 0xd7 0x60 0x29 + +# CHECK: tleu %i5 +0x89 0xd0 0x00 0x1d + +# CHECK: tcc 82 +0x9b 0xd0 0x20 0x52 + +# CHECK: tcs %g1 + %i2 +0x8b 0xd0 0x40 0x1a + +# CHECK: tpos %i5 + 41 +0x9d 0xd7 0x60 0x29 + +# CHECK: tneg %i5 +0x8d 0xd0 0x00 0x1d + +# CHECK: tvc 82 +0x9f 0xd0 0x20 0x52 + +# CHECK: tvs %g1 + %i2 +0x8f 0xd0 0x40 0x1a Index: test/MC/Sparc/sparc-ctrl-instructions.s =================================================================== --- test/MC/Sparc/sparc-ctrl-instructions.s +++ test/MC/Sparc/sparc-ctrl-instructions.s @@ -199,6 +199,74 @@ ! CHECK: fbo .BB0 ! encoding: [0x1f,0b10AAAAAA,A,A] ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 fbo .BB0 + + ! CHECK: cba .BB0 ! encoding: [0x11,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb .BB0 + + ! CHECK: cba .BB0 ! encoding: [0x11,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cba .BB0 + + ! CHECK: cbn .BB0 ! encoding: [0x01,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cbn .BB0 + + ! CHECK: cb3 .BB0 ! encoding: [0x0f,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb3 .BB0 + + ! CHECK: cb2 .BB0 ! encoding: [0x0d,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb2 .BB0 + + ! CHECK: cb23 .BB0 ! encoding: [0x0b,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb23 .BB0 + + ! CHECK: cb1 .BB0 ! encoding: [0x09,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb1 .BB0 + + ! CHECK: cb13 .BB0 ! encoding: [0x07,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb13 .BB0 + + ! CHECK: cb12 .BB0 ! encoding: [0x05,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb12 .BB0 + + ! CHECK: cb123 .BB0 ! encoding: [0x03,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb123 .BB0 + + ! CHECK: cb0 .BB0 ! encoding: [0x13,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb0 .BB0 + + ! CHECK: cb03 .BB0 ! encoding: [0x15,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb03 .BB0 + + ! CHECK: cb02 .BB0 ! encoding: [0x17,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb02 .BB0 + + ! CHECK: cb023 .BB0 ! encoding: [0x19,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb023 .BB0 + + ! CHECK: cb01 .BB0 ! encoding: [0x1b,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb01 .BB0 + + ! CHECK: cb013 .BB0 ! encoding: [0x1d,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb013 .BB0 + + ! CHECK: cb012 .BB0 ! encoding: [0x1f,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb012 .BB0 ! CHECK: ba,a .BB0 ! encoding: [0x30,0b10AAAAAA,A,A] ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 @@ -317,3 +385,119 @@ ! CHECK: rett %i7+8 ! encoding: [0x81,0xcf,0xe0,0x08] rett %i7 + 8 + + ! CHECK: cb3,a .BB0 ! encoding: [0x2f,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb3,a .BB0 + + ! CHECK: cb2,a .BB0 ! encoding: [0x2d,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb2,a .BB0 + + ! CHECK: cb23,a .BB0 ! encoding: [0x2b,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb23,a .BB0 + + ! CHECK: cb1,a .BB0 ! encoding: [0x29,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb1,a .BB0 + + ! CHECK: cb13,a .BB0 ! encoding: [0x27,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb13,a .BB0 + + ! CHECK: cb12,a .BB0 ! encoding: [0x25,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb12,a .BB0 + + ! CHECK: cb123,a .BB0 ! encoding: [0x23,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb123,a .BB0 + + ! CHECK: cb0,a .BB0 ! encoding: [0x33,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb0,a .BB0 + + ! CHECK: cb03,a .BB0 ! encoding: [0x35,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb03,a .BB0 + + ! CHECK: cb02,a .BB0 ! encoding: [0x37,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb02,a .BB0 + + ! CHECK: cb023,a .BB0 ! encoding: [0x39,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb023,a .BB0 + + ! CHECK: cb01,a .BB0 ! encoding: [0x3b,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb01,a .BB0 + + ! CHECK: cb013,a .BB0 ! encoding: [0x3d,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb013,a .BB0 + + ! CHECK: cb012,a .BB0 ! encoding: [0x3f,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb012,a .BB0 + + ! CHECK: cb3,a .BB0 ! encoding: [0x2f,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb3,a .BB0 + + ! CHECK: cb2,a .BB0 ! encoding: [0x2d,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb2,a .BB0 + + ! CHECK: cb23,a .BB0 ! encoding: [0x2b,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb23,a .BB0 + + ! CHECK: cb1,a .BB0 ! encoding: [0x29,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb1,a .BB0 + + ! CHECK: cb13,a .BB0 ! encoding: [0x27,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb13,a .BB0 + + ! CHECK: cb12,a .BB0 ! encoding: [0x25,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb12,a .BB0 + + ! CHECK: cb123,a .BB0 ! encoding: [0x23,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb123,a .BB0 + + ! CHECK: cb0,a .BB0 ! encoding: [0x33,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb0,a .BB0 + + ! CHECK: cb03,a .BB0 ! encoding: [0x35,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb03,a .BB0 + + ! CHECK: cb02,a .BB0 ! encoding: [0x37,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb02,a .BB0 + + ! CHECK: cb023,a .BB0 ! encoding: [0x39,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb023,a .BB0 + + ! CHECK: cb01,a .BB0 ! encoding: [0x3b,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb01,a .BB0 + + ! CHECK: cb013,a .BB0 ! encoding: [0x3d,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb013,a .BB0 + + ! CHECK: cb012,a .BB0 ! encoding: [0x3f,0b11AAAAAA,A,A] + ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 + cb012,a .BB0 + + ! CHECK: rett %i7+8 ! encoding: [0x81,0xcf,0xe0,0x08] + rett %i7 + 8 + Index: test/MC/Sparc/sparc-traps.s =================================================================== --- test/MC/Sparc/sparc-traps.s +++ test/MC/Sparc/sparc-traps.s @@ -0,0 +1,151 @@ +! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s + + ! CHECK: ta %i5 ! encoding: [0x91,0xd0,0x00,0x1d] + ! CHECK: ta 82 ! encoding: [0x91,0xd0,0x20,0x52] + ! CHECK: ta %g1 + %i2 ! encoding: [0x91,0xd0,0x40,0x1a] + ! CHECK: ta %i5 + 41 ! encoding: [0x91,0xd7,0x60,0x29] + ta %i5 + ta 82 + ta %g1 + %i2 + ta %i5 + 41 + + ! CHECK: tn %i5 ! encoding: [0x81,0xd0,0x00,0x1d] + ! CHECK: tn 82 ! encoding: [0x81,0xd0,0x20,0x52] + ! CHECK: tn %g1 + %i2 ! encoding: [0x81,0xd0,0x40,0x1a] + ! CHECK: tn %i5 + 41 ! encoding: [0x81,0xd7,0x60,0x29] + tn %i5 + tn 82 + tn %g1 + %i2 + tn %i5 + 41 + + ! CHECK: tne %i5 ! encoding: [0x93,0xd0,0x00,0x1d] + !! tnz should be a synonym for tne + ! CHECK: tne %i5 ! encoding: [0x93,0xd0,0x00,0x1d] + ! CHECK: tne 82 ! encoding: [0x93,0xd0,0x20,0x52] + ! CHECK: tne %g1 + %i2 ! encoding: [0x93,0xd0,0x40,0x1a] + ! CHECK: tne %i5 + 41 ! encoding: [0x93,0xd7,0x60,0x29] + tne %i5 + tnz %i5 + tne 82 + tne %g1 + %i2 + tne %i5 + 41 + + ! CHECK: te %i5 ! encoding: [0x83,0xd0,0x00,0x1d] + !! tz should be a synonym for te + ! CHECK: te %i5 ! encoding: [0x83,0xd0,0x00,0x1d] + ! CHECK: te 82 ! encoding: [0x83,0xd0,0x20,0x52] + ! CHECK: te %g1 + %i2 ! encoding: [0x83,0xd0,0x40,0x1a] + ! CHECK: te %i5 + 41 ! encoding: [0x83,0xd7,0x60,0x29] + te %i5 + tz %i5 + te 82 + te %g1 + %i2 + te %i5 + 41 + + ! CHECK: tg %i5 ! encoding: [0x95,0xd0,0x00,0x1d] + ! CHECK: tg 82 ! encoding: [0x95,0xd0,0x20,0x52] + ! CHECK: tg %g1 + %i2 ! encoding: [0x95,0xd0,0x40,0x1a] + ! CHECK: tg %i5 + 41 ! encoding: [0x95,0xd7,0x60,0x29] + tg %i5 + tg 82 + tg %g1 + %i2 + tg %i5 + 41 + + ! CHECK: tle %i5 ! encoding: [0x85,0xd0,0x00,0x1d] + ! CHECK: tle 82 ! encoding: [0x85,0xd0,0x20,0x52] + ! CHECK: tle %g1 + %i2 ! encoding: [0x85,0xd0,0x40,0x1a] + ! CHECK: tle %i5 + 41 ! encoding: [0x85,0xd7,0x60,0x29] + tle %i5 + tle 82 + tle %g1 + %i2 + tle %i5 + 41 + + ! CHECK: tge %i5 ! encoding: [0x97,0xd0,0x00,0x1d] + ! CHECK: tge 82 ! encoding: [0x97,0xd0,0x20,0x52] + ! CHECK: tge %g1 + %i2 ! encoding: [0x97,0xd0,0x40,0x1a] + ! CHECK: tge %i5 + 41 ! encoding: [0x97,0xd7,0x60,0x29] + tge %i5 + tge 82 + tge %g1 + %i2 + tge %i5 + 41 + + ! CHECK: tl %i5 ! encoding: [0x87,0xd0,0x00,0x1d] + ! CHECK: tl 82 ! encoding: [0x87,0xd0,0x20,0x52] + ! CHECK: tl %g1 + %i2 ! encoding: [0x87,0xd0,0x40,0x1a] + ! CHECK: tl %i5 + 41 ! encoding: [0x87,0xd7,0x60,0x29] + tl %i5 + tl 82 + tl %g1 + %i2 + tl %i5 + 41 + + ! CHECK: tgu %i5 ! encoding: [0x99,0xd0,0x00,0x1d] + ! CHECK: tgu 82 ! encoding: [0x99,0xd0,0x20,0x52] + ! CHECK: tgu %g1 + %i2 ! encoding: [0x99,0xd0,0x40,0x1a] + ! CHECK: tgu %i5 + 41 ! encoding: [0x99,0xd7,0x60,0x29] + tgu %i5 + tgu 82 + tgu %g1 + %i2 + tgu %i5 + 41 + + ! CHECK: tleu %i5 ! encoding: [0x89,0xd0,0x00,0x1d] + ! CHECK: tleu 82 ! encoding: [0x89,0xd0,0x20,0x52] + ! CHECK: tleu %g1 + %i2 ! encoding: [0x89,0xd0,0x40,0x1a] + ! CHECK: tleu %i5 + 41 ! encoding: [0x89,0xd7,0x60,0x29] + tleu %i5 + tleu 82 + tleu %g1 + %i2 + tleu %i5 + 41 + + ! CHECK: tcc %i5 ! encoding: [0x9b,0xd0,0x00,0x1d] + ! CHECK: tcc 82 ! encoding: [0x9b,0xd0,0x20,0x52] + ! CHECK: tcc %g1 + %i2 ! encoding: [0x9b,0xd0,0x40,0x1a] + ! CHECK: tcc %i5 + 41 ! encoding: [0x9b,0xd7,0x60,0x29] + tcc %i5 + tcc 82 + tcc %g1 + %i2 + tcc %i5 + 41 + + ! CHECK: tcs %i5 ! encoding: [0x8b,0xd0,0x00,0x1d] + ! CHECK: tcs 82 ! encoding: [0x8b,0xd0,0x20,0x52] + ! CHECK: tcs %g1 + %i2 ! encoding: [0x8b,0xd0,0x40,0x1a] + ! CHECK: tcs %i5 + 41 ! encoding: [0x8b,0xd7,0x60,0x29] + tcs %i5 + tcs 82 + tcs %g1 + %i2 + tcs %i5 + 41 + + ! CHECK: tpos %i5 ! encoding: [0x9d,0xd0,0x00,0x1d] + ! CHECK: tpos 82 ! encoding: [0x9d,0xd0,0x20,0x52] + ! CHECK: tpos %g1 + %i2 ! encoding: [0x9d,0xd0,0x40,0x1a] + ! CHECK: tpos %i5 + 41 ! encoding: [0x9d,0xd7,0x60,0x29] + tpos %i5 + tpos 82 + tpos %g1 + %i2 + tpos %i5 + 41 + + ! CHECK: tneg %i5 ! encoding: [0x8d,0xd0,0x00,0x1d] + ! CHECK: tneg 82 ! encoding: [0x8d,0xd0,0x20,0x52] + ! CHECK: tneg %g1 + %i2 ! encoding: [0x8d,0xd0,0x40,0x1a] + ! CHECK: tneg %i5 + 41 ! encoding: [0x8d,0xd7,0x60,0x29] + tneg %i5 + tneg 82 + tneg %g1 + %i2 + tneg %i5 + 41 + + ! CHECK: tvc %i5 ! encoding: [0x9f,0xd0,0x00,0x1d] + ! CHECK: tvc 82 ! encoding: [0x9f,0xd0,0x20,0x52] + ! CHECK: tvc %g1 + %i2 ! encoding: [0x9f,0xd0,0x40,0x1a] + ! CHECK: tvc %i5 + 41 ! encoding: [0x9f,0xd7,0x60,0x29] + tvc %i5 + tvc 82 + tvc %g1 + %i2 + tvc %i5 + 41 + + ! CHECK: tvs %i5 ! encoding: [0x8f,0xd0,0x00,0x1d] + ! CHECK: tvs 82 ! encoding: [0x8f,0xd0,0x20,0x52] + ! CHECK: tvs %g1 + %i2 ! encoding: [0x8f,0xd0,0x40,0x1a] + ! CHECK: tvs %i5 + 41 ! encoding: [0x8f,0xd7,0x60,0x29] + tvs %i5 + tvs 82 + tvs %g1 + %i2 + tvs %i5 + 41 Index: test/MC/Sparc/sparc-v9-traps.s =================================================================== --- test/MC/Sparc/sparc-v9-traps.s +++ test/MC/Sparc/sparc-v9-traps.s @@ -0,0 +1,303 @@ +! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s + + ! CHECK: ta %icc, %i5 ! encoding: [0x91,0xd0,0x00,0x1d] + ! CHECK: ta %icc, 82 ! encoding: [0x91,0xd0,0x20,0x52] + ! CHECK: ta %icc, %g1 + %i2 ! encoding: [0x91,0xd0,0x40,0x1a] + ! CHECK: ta %icc, %i5 + 41 ! encoding: [0x91,0xd7,0x60,0x29] + ta %icc, %i5 + ta %icc, 82 + ta %icc, %g1 + %i2 + ta %icc, %i5 + 41 + + ! CHECK: tn %icc, %i5 ! encoding: [0x81,0xd0,0x00,0x1d] + ! CHECK: tn %icc, 82 ! encoding: [0x81,0xd0,0x20,0x52] + ! CHECK: tn %icc, %g1 + %i2 ! encoding: [0x81,0xd0,0x40,0x1a] + ! CHECK: tn %icc, %i5 + 41 ! encoding: [0x81,0xd7,0x60,0x29] + tn %icc, %i5 + tn %icc, 82 + tn %icc, %g1 + %i2 + tn %icc, %i5 + 41 + + ! CHECK: tne %icc, %i5 ! encoding: [0x93,0xd0,0x00,0x1d] + !! tnz should be a synonym for tne + ! CHECK: tne %icc, %i5 ! encoding: [0x93,0xd0,0x00,0x1d] + ! CHECK: tne %icc, 82 ! encoding: [0x93,0xd0,0x20,0x52] + ! CHECK: tne %icc, %g1 + %i2 ! encoding: [0x93,0xd0,0x40,0x1a] + ! CHECK: tne %icc, %i5 + 41 ! encoding: [0x93,0xd7,0x60,0x29] + tne %icc, %i5 + tnz %icc, %i5 + tne %icc, 82 + tne %icc, %g1 + %i2 + tne %icc, %i5 + 41 + + ! CHECK: te %icc, %i5 ! encoding: [0x83,0xd0,0x00,0x1d] + !! tz should be a synonym for te + ! CHECK: te %icc, %i5 ! encoding: [0x83,0xd0,0x00,0x1d] + ! CHECK: te %icc, 82 ! encoding: [0x83,0xd0,0x20,0x52] + ! CHECK: te %icc, %g1 + %i2 ! encoding: [0x83,0xd0,0x40,0x1a] + ! CHECK: te %icc, %i5 + 41 ! encoding: [0x83,0xd7,0x60,0x29] + te %icc, %i5 + tz %icc, %i5 + te %icc, 82 + te %icc, %g1 + %i2 + te %icc, %i5 + 41 + + ! CHECK: tg %icc, %i5 ! encoding: [0x95,0xd0,0x00,0x1d] + ! CHECK: tg %icc, 82 ! encoding: [0x95,0xd0,0x20,0x52] + ! CHECK: tg %icc, %g1 + %i2 ! encoding: [0x95,0xd0,0x40,0x1a] + ! CHECK: tg %icc, %i5 + 41 ! encoding: [0x95,0xd7,0x60,0x29] + tg %icc, %i5 + tg %icc, 82 + tg %icc, %g1 + %i2 + tg %icc, %i5 + 41 + + ! CHECK: tle %icc, %i5 ! encoding: [0x85,0xd0,0x00,0x1d] + ! CHECK: tle %icc, 82 ! encoding: [0x85,0xd0,0x20,0x52] + ! CHECK: tle %icc, %g1 + %i2 ! encoding: [0x85,0xd0,0x40,0x1a] + ! CHECK: tle %icc, %i5 + 41 ! encoding: [0x85,0xd7,0x60,0x29] + tle %icc, %i5 + tle %icc, 82 + tle %icc, %g1 + %i2 + tle %icc, %i5 + 41 + + ! CHECK: tge %icc, %i5 ! encoding: [0x97,0xd0,0x00,0x1d] + ! CHECK: tge %icc, 82 ! encoding: [0x97,0xd0,0x20,0x52] + ! CHECK: tge %icc, %g1 + %i2 ! encoding: [0x97,0xd0,0x40,0x1a] + ! CHECK: tge %icc, %i5 + 41 ! encoding: [0x97,0xd7,0x60,0x29] + tge %icc, %i5 + tge %icc, 82 + tge %icc, %g1 + %i2 + tge %icc, %i5 + 41 + + ! CHECK: tl %icc, %i5 ! encoding: [0x87,0xd0,0x00,0x1d] + ! CHECK: tl %icc, 82 ! encoding: [0x87,0xd0,0x20,0x52] + ! CHECK: tl %icc, %g1 + %i2 ! encoding: [0x87,0xd0,0x40,0x1a] + ! CHECK: tl %icc, %i5 + 41 ! encoding: [0x87,0xd7,0x60,0x29] + tl %icc, %i5 + tl %icc, 82 + tl %icc, %g1 + %i2 + tl %icc, %i5 + 41 + + ! CHECK: tgu %icc, %i5 ! encoding: [0x99,0xd0,0x00,0x1d] + ! CHECK: tgu %icc, 82 ! encoding: [0x99,0xd0,0x20,0x52] + ! CHECK: tgu %icc, %g1 + %i2 ! encoding: [0x99,0xd0,0x40,0x1a] + ! CHECK: tgu %icc, %i5 + 41 ! encoding: [0x99,0xd7,0x60,0x29] + tgu %icc, %i5 + tgu %icc, 82 + tgu %icc, %g1 + %i2 + tgu %icc, %i5 + 41 + + ! CHECK: tleu %icc, %i5 ! encoding: [0x89,0xd0,0x00,0x1d] + ! CHECK: tleu %icc, 82 ! encoding: [0x89,0xd0,0x20,0x52] + ! CHECK: tleu %icc, %g1 + %i2 ! encoding: [0x89,0xd0,0x40,0x1a] + ! CHECK: tleu %icc, %i5 + 41 ! encoding: [0x89,0xd7,0x60,0x29] + tleu %icc, %i5 + tleu %icc, 82 + tleu %icc, %g1 + %i2 + tleu %icc, %i5 + 41 + + ! CHECK: tcc %icc, %i5 ! encoding: [0x9b,0xd0,0x00,0x1d] + ! CHECK: tcc %icc, 82 ! encoding: [0x9b,0xd0,0x20,0x52] + ! CHECK: tcc %icc, %g1 + %i2 ! encoding: [0x9b,0xd0,0x40,0x1a] + ! CHECK: tcc %icc, %i5 + 41 ! encoding: [0x9b,0xd7,0x60,0x29] + tcc %icc, %i5 + tcc %icc, 82 + tcc %icc, %g1 + %i2 + tcc %icc, %i5 + 41 + + ! CHECK: tcs %icc, %i5 ! encoding: [0x8b,0xd0,0x00,0x1d] + ! CHECK: tcs %icc, 82 ! encoding: [0x8b,0xd0,0x20,0x52] + ! CHECK: tcs %icc, %g1 + %i2 ! encoding: [0x8b,0xd0,0x40,0x1a] + ! CHECK: tcs %icc, %i5 + 41 ! encoding: [0x8b,0xd7,0x60,0x29] + tcs %icc, %i5 + tcs %icc, 82 + tcs %icc, %g1 + %i2 + tcs %icc, %i5 + 41 + + ! CHECK: tpos %icc, %i5 ! encoding: [0x9d,0xd0,0x00,0x1d] + ! CHECK: tpos %icc, 82 ! encoding: [0x9d,0xd0,0x20,0x52] + ! CHECK: tpos %icc, %g1 + %i2 ! encoding: [0x9d,0xd0,0x40,0x1a] + ! CHECK: tpos %icc, %i5 + 41 ! encoding: [0x9d,0xd7,0x60,0x29] + tpos %icc, %i5 + tpos %icc, 82 + tpos %icc, %g1 + %i2 + tpos %icc, %i5 + 41 + + ! CHECK: tneg %icc, %i5 ! encoding: [0x8d,0xd0,0x00,0x1d] + ! CHECK: tneg %icc, 82 ! encoding: [0x8d,0xd0,0x20,0x52] + ! CHECK: tneg %icc, %g1 + %i2 ! encoding: [0x8d,0xd0,0x40,0x1a] + ! CHECK: tneg %icc, %i5 + 41 ! encoding: [0x8d,0xd7,0x60,0x29] + tneg %icc, %i5 + tneg %icc, 82 + tneg %icc, %g1 + %i2 + tneg %icc, %i5 + 41 + + ! CHECK: tvc %icc, %i5 ! encoding: [0x9f,0xd0,0x00,0x1d] + ! CHECK: tvc %icc, 82 ! encoding: [0x9f,0xd0,0x20,0x52] + ! CHECK: tvc %icc, %g1 + %i2 ! encoding: [0x9f,0xd0,0x40,0x1a] + ! CHECK: tvc %icc, %i5 + 41 ! encoding: [0x9f,0xd7,0x60,0x29] + tvc %icc, %i5 + tvc %icc, 82 + tvc %icc, %g1 + %i2 + tvc %icc, %i5 + 41 + + ! CHECK: tvs %icc, %i5 ! encoding: [0x8f,0xd0,0x00,0x1d] + ! CHECK: tvs %icc, 82 ! encoding: [0x8f,0xd0,0x20,0x52] + ! CHECK: tvs %icc, %g1 + %i2 ! encoding: [0x8f,0xd0,0x40,0x1a] + ! CHECK: tvs %icc, %i5 + 41 ! encoding: [0x8f,0xd7,0x60,0x29] + tvs %icc, %i5 + tvs %icc, 82 + tvs %icc, %g1 + %i2 + tvs %icc, %i5 + 41 + + + ! CHECK: ta %xcc, %i5 ! encoding: [0x91,0xd0,0x10,0x1d] + ! CHECK: ta %xcc, 82 ! encoding: [0x91,0xd0,0x30,0x52] + ! CHECK: ta %xcc, %g1 + %i2 ! encoding: [0x91,0xd0,0x50,0x1a] + ! CHECK: ta %xcc, %i5 + 41 ! encoding: [0x91,0xd7,0x70,0x29] + ta %xcc, %i5 + ta %xcc, 82 + ta %xcc, %g1 + %i2 + ta %xcc, %i5 + 41 + + ! CHECK: tn %xcc, %i5 ! encoding: [0x81,0xd0,0x10,0x1d] + ! CHECK: tn %xcc, 82 ! encoding: [0x81,0xd0,0x30,0x52] + ! CHECK: tn %xcc, %g1 + %i2 ! encoding: [0x81,0xd0,0x50,0x1a] + ! CHECK: tn %xcc, %i5 + 41 ! encoding: [0x81,0xd7,0x70,0x29] + tn %xcc, %i5 + tn %xcc, 82 + tn %xcc, %g1 + %i2 + tn %xcc, %i5 + 41 + + ! CHECK: tne %xcc, %i5 ! encoding: [0x93,0xd0,0x10,0x1d] + !! tnz should be a synonym for tne + ! CHECK: tne %xcc, %i5 ! encoding: [0x93,0xd0,0x10,0x1d] + ! CHECK: tne %xcc, 82 ! encoding: [0x93,0xd0,0x30,0x52] + ! CHECK: tne %xcc, %g1 + %i2 ! encoding: [0x93,0xd0,0x50,0x1a] + ! CHECK: tne %xcc, %i5 + 41 ! encoding: [0x93,0xd7,0x70,0x29] + tne %xcc, %i5 + tnz %xcc, %i5 + tne %xcc, 82 + tne %xcc, %g1 + %i2 + tne %xcc, %i5 + 41 + + ! CHECK: te %xcc, %i5 ! encoding: [0x83,0xd0,0x10,0x1d] + !! tz should be a synonym for te + ! CHECK: te %xcc, %i5 ! encoding: [0x83,0xd0,0x10,0x1d] + ! CHECK: te %xcc, 82 ! encoding: [0x83,0xd0,0x30,0x52] + ! CHECK: te %xcc, %g1 + %i2 ! encoding: [0x83,0xd0,0x50,0x1a] + ! CHECK: te %xcc, %i5 + 41 ! encoding: [0x83,0xd7,0x70,0x29] + te %xcc, %i5 + tz %xcc, %i5 + te %xcc, 82 + te %xcc, %g1 + %i2 + te %xcc, %i5 + 41 + + ! CHECK: tg %xcc, %i5 ! encoding: [0x95,0xd0,0x10,0x1d] + ! CHECK: tg %xcc, 82 ! encoding: [0x95,0xd0,0x30,0x52] + ! CHECK: tg %xcc, %g1 + %i2 ! encoding: [0x95,0xd0,0x50,0x1a] + ! CHECK: tg %xcc, %i5 + 41 ! encoding: [0x95,0xd7,0x70,0x29] + tg %xcc, %i5 + tg %xcc, 82 + tg %xcc, %g1 + %i2 + tg %xcc, %i5 + 41 + + ! CHECK: tle %xcc, %i5 ! encoding: [0x85,0xd0,0x10,0x1d] + ! CHECK: tle %xcc, 82 ! encoding: [0x85,0xd0,0x30,0x52] + ! CHECK: tle %xcc, %g1 + %i2 ! encoding: [0x85,0xd0,0x50,0x1a] + ! CHECK: tle %xcc, %i5 + 41 ! encoding: [0x85,0xd7,0x70,0x29] + tle %xcc, %i5 + tle %xcc, 82 + tle %xcc, %g1 + %i2 + tle %xcc, %i5 + 41 + + ! CHECK: tge %xcc, %i5 ! encoding: [0x97,0xd0,0x10,0x1d] + ! CHECK: tge %xcc, 82 ! encoding: [0x97,0xd0,0x30,0x52] + ! CHECK: tge %xcc, %g1 + %i2 ! encoding: [0x97,0xd0,0x50,0x1a] + ! CHECK: tge %xcc, %i5 + 41 ! encoding: [0x97,0xd7,0x70,0x29] + tge %xcc, %i5 + tge %xcc, 82 + tge %xcc, %g1 + %i2 + tge %xcc, %i5 + 41 + + ! CHECK: tl %xcc, %i5 ! encoding: [0x87,0xd0,0x10,0x1d] + ! CHECK: tl %xcc, 82 ! encoding: [0x87,0xd0,0x30,0x52] + ! CHECK: tl %xcc, %g1 + %i2 ! encoding: [0x87,0xd0,0x50,0x1a] + ! CHECK: tl %xcc, %i5 + 41 ! encoding: [0x87,0xd7,0x70,0x29] + tl %xcc, %i5 + tl %xcc, 82 + tl %xcc, %g1 + %i2 + tl %xcc, %i5 + 41 + + ! CHECK: tgu %xcc, %i5 ! encoding: [0x99,0xd0,0x10,0x1d] + ! CHECK: tgu %xcc, 82 ! encoding: [0x99,0xd0,0x30,0x52] + ! CHECK: tgu %xcc, %g1 + %i2 ! encoding: [0x99,0xd0,0x50,0x1a] + ! CHECK: tgu %xcc, %i5 + 41 ! encoding: [0x99,0xd7,0x70,0x29] + tgu %xcc, %i5 + tgu %xcc, 82 + tgu %xcc, %g1 + %i2 + tgu %xcc, %i5 + 41 + + ! CHECK: tleu %xcc, %i5 ! encoding: [0x89,0xd0,0x10,0x1d] + ! CHECK: tleu %xcc, 82 ! encoding: [0x89,0xd0,0x30,0x52] + ! CHECK: tleu %xcc, %g1 + %i2 ! encoding: [0x89,0xd0,0x50,0x1a] + ! CHECK: tleu %xcc, %i5 + 41 ! encoding: [0x89,0xd7,0x70,0x29] + tleu %xcc, %i5 + tleu %xcc, 82 + tleu %xcc, %g1 + %i2 + tleu %xcc, %i5 + 41 + + ! CHECK: tcc %xcc, %i5 ! encoding: [0x9b,0xd0,0x10,0x1d] + ! CHECK: tcc %xcc, 82 ! encoding: [0x9b,0xd0,0x30,0x52] + ! CHECK: tcc %xcc, %g1 + %i2 ! encoding: [0x9b,0xd0,0x50,0x1a] + ! CHECK: tcc %xcc, %i5 + 41 ! encoding: [0x9b,0xd7,0x70,0x29] + tcc %xcc, %i5 + tcc %xcc, 82 + tcc %xcc, %g1 + %i2 + tcc %xcc, %i5 + 41 + + ! CHECK: tcs %xcc, %i5 ! encoding: [0x8b,0xd0,0x10,0x1d] + ! CHECK: tcs %xcc, 82 ! encoding: [0x8b,0xd0,0x30,0x52] + ! CHECK: tcs %xcc, %g1 + %i2 ! encoding: [0x8b,0xd0,0x50,0x1a] + ! CHECK: tcs %xcc, %i5 + 41 ! encoding: [0x8b,0xd7,0x70,0x29] + tcs %xcc, %i5 + tcs %xcc, 82 + tcs %xcc, %g1 + %i2 + tcs %xcc, %i5 + 41 + + ! CHECK: tpos %xcc, %i5 ! encoding: [0x9d,0xd0,0x10,0x1d] + ! CHECK: tpos %xcc, 82 ! encoding: [0x9d,0xd0,0x30,0x52] + ! CHECK: tpos %xcc, %g1 + %i2 ! encoding: [0x9d,0xd0,0x50,0x1a] + ! CHECK: tpos %xcc, %i5 + 41 ! encoding: [0x9d,0xd7,0x70,0x29] + tpos %xcc, %i5 + tpos %xcc, 82 + tpos %xcc, %g1 + %i2 + tpos %xcc, %i5 + 41 + + ! CHECK: tneg %xcc, %i5 ! encoding: [0x8d,0xd0,0x10,0x1d] + ! CHECK: tneg %xcc, 82 ! encoding: [0x8d,0xd0,0x30,0x52] + ! CHECK: tneg %xcc, %g1 + %i2 ! encoding: [0x8d,0xd0,0x50,0x1a] + ! CHECK: tneg %xcc, %i5 + 41 ! encoding: [0x8d,0xd7,0x70,0x29] + tneg %xcc, %i5 + tneg %xcc, 82 + tneg %xcc, %g1 + %i2 + tneg %xcc, %i5 + 41 + + ! CHECK: tvc %xcc, %i5 ! encoding: [0x9f,0xd0,0x10,0x1d] + ! CHECK: tvc %xcc, 82 ! encoding: [0x9f,0xd0,0x30,0x52] + ! CHECK: tvc %xcc, %g1 + %i2 ! encoding: [0x9f,0xd0,0x50,0x1a] + ! CHECK: tvc %xcc, %i5 + 41 ! encoding: [0x9f,0xd7,0x70,0x29] + tvc %xcc, %i5 + tvc %xcc, 82 + tvc %xcc, %g1 + %i2 + tvc %xcc, %i5 + 41 + + ! CHECK: tvs %xcc, %i5 ! encoding: [0x8f,0xd0,0x10,0x1d] + ! CHECK: tvs %xcc, 82 ! encoding: [0x8f,0xd0,0x30,0x52] + ! CHECK: tvs %xcc, %g1 + %i2 ! encoding: [0x8f,0xd0,0x50,0x1a] + ! CHECK: tvs %xcc, %i5 + 41 ! encoding: [0x8f,0xd7,0x70,0x29] + tvs %xcc, %i5 + tvs %xcc, 82 + tvs %xcc, %g1 + %i2 + tvs %xcc, %i5 + 41 + \ No newline at end of file Index: test/MC/Sparc/sparc64-ctrl-instructions.s =================================================================== --- test/MC/Sparc/sparc64-ctrl-instructions.s +++ test/MC/Sparc/sparc64-ctrl-instructions.s @@ -1230,9 +1230,3 @@ ! CHECK: rett %i7+8 ! encoding: [0x81,0xcf,0xe0,0x08] return %i7 + 8 - ! CHECK: ta %icc, %g0 + 5 ! encoding: [0x91,0xd0,0x20,0x05] - ta 5 - - ! CHECK: te %xcc, %g0 + 3 ! encoding: [0x83,0xd0,0x30,0x03] - te %xcc, 3 -