Index: lib/Target/X86/X86InstrAVX512.td =================================================================== --- lib/Target/X86/X86InstrAVX512.td +++ lib/Target/X86/X86InstrAVX512.td @@ -2512,6 +2512,14 @@ defm : operation_subvector_mask_lowering; +def : Pat<(v2i1 (extract_subvector (v4i1 VK4:$src), (iPTR 2))), + (v2i1 (COPY_TO_REGCLASS + (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16), (i8 2)), + VK2))>; +def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 4))), + (v4i1 (COPY_TO_REGCLASS + (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (i8 4)), + VK4))>; def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))), (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>; def : Pat<(v16i1 (extract_subvector (v32i1 VK32:$src), (iPTR 16))), Index: test/CodeGen/X86/avx512-skx-insert-subvec.ll =================================================================== --- test/CodeGen/X86/avx512-skx-insert-subvec.ll +++ test/CodeGen/X86/avx512-skx-insert-subvec.ll @@ -145,3 +145,26 @@ ret <64 x i1> %res } +define <4 x i1> @test9(<8 x i1> %a, <8 x i1> %b) { +; CHECK-LABEL: test9: +; CHECK: # BB#0: +; CHECK-NEXT: vpsllw $15, %xmm0, %xmm0 +; CHECK-NEXT: vpmovw2m %xmm0, %k0 +; CHECK-NEXT: kshiftrw $4, %k0, %k0 +; CHECK-NEXT: vpmovm2d %k0, %xmm0 +; CHECK-NEXT: retq + %res = shufflevector <8 x i1> %a, <8 x i1> %b, <4 x i32> + ret <4 x i1> %res +} + +define <2 x i1> @test10(<4 x i1> %a, <4 x i1> %b) { +; CHECK-LABEL: test10: +; CHECK: # BB#0: +; CHECK-NEXT: vpslld $31, %xmm0, %xmm0 +; CHECK-NEXT: vptestmd %xmm0, %xmm0, %k0 +; CHECK-NEXT: kshiftrw $2, %k0, %k0 +; CHECK-NEXT: vpmovm2q %k0, %xmm0 +; CHECK-NEXT: retq + %res = shufflevector <4 x i1> %a, <4 x i1> %b, <2 x i32> + ret <2 x i1> %res +}