Index: lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp =================================================================== --- lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -1190,6 +1190,15 @@ } break; } + // Power9 Instructions: + case PPC::SUBPCIS: { + MCInst TmpInst; + TmpInst.setOpcode(PPC::ADDPCIS); + TmpInst.addOperand(Inst.getOperand(0)); + addNegOperand(TmpInst, Inst.getOperand(1), getContext()); + Inst = TmpInst; + break; + } } } Index: lib/Target/PowerPC/PPCInstr64Bit.td =================================================================== --- lib/Target/PowerPC/PPCInstr64Bit.td +++ lib/Target/PowerPC/PPCInstr64Bit.td @@ -1246,3 +1246,58 @@ def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>; def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>; + +// [PO RT RA RB RC XO] +class VA_RT5_RA5_RB5_RC5 xo, string opc, InstrItinClass itin, + list pattern> + : VAForm_1a; + +// 64-bit Fixed-Point Multiply-Add High-DWord/High-DWord-Unsigned/Low-DWord +def MADDHD : VA_RT5_RA5_RB5_RC5<48, "maddhd" , IIC_IntGeneral, []>; +def MADDHDU : VA_RT5_RA5_RB5_RC5<49, "maddhdu", IIC_IntGeneral, []>; +def MADDLD : VA_RT5_RA5_RB5_RC5<51, "maddld ", IIC_IntGeneral, []>; + +// [PO RT RA RB XO /] +class X_RT5_RA5_RB5 xo, string opc, RegisterOperand type, + InstrItinClass itin, list pattern> + : XForm_base_r3xo<31, xo, (outs type:$rD), (ins type:$rA, type:$rB), + !strconcat(opc, " $rD, $rA, $rB"), itin, pattern>; + +let Interpretation64Bit = 1, isCodeGenOnly = 1 in { +// Add PC Immediate Shifted +def ADDPCIS8 : DX_RD5_IM16<19, 2, (outs g8rc:$rD), (ins s16imm:$IMM), + "addpcis $rD, $IMM", IIC_IntSimple, []>; + +// Modulo {Signed/Unsigned}-Word +def MODSW8 : X_RT5_RA5_RB5<779, "modsw", g8rc, IIC_IntDivW, []>; +def MODUW8 : X_RT5_RA5_RB5<267, "moduw", g8rc, IIC_IntDivW, []>; +} + +// Modulo {Signed/Unsigned}-DWord +def MODSD : X_RT5_RA5_RB5<777, "modsd", g8rc, IIC_IntDivW, []>; +def MODUD : X_RT5_RA5_RB5<265, "modud", g8rc, IIC_IntDivW, []>; + +class XS_RS5_RA5_SH5 opcode, bits<9> xo, string opc, + InstrItinClass itin, list pattern> + : XSForm_1; + +class XS_RS5_RA5_SH5o opcode, bits<9> xo, string opc, + InstrItinClass itin, list pattern> + : XS_RS5_RA5_SH5 { + let Defs = [CR0]; + let RC = 1; +} + +// Deliver A Random Number +def DARN : X_RD5_L2<31, 755, (outs g8rc:$rD), (ins u2imm:$L), "darn $rD, $L", + IIC_IntGeneral, []>; + +// Extend-Sign Word and Shift Left Immediate +def EXTSWSLI : XS_RS5_RA5_SH5 <31, 445, "extswsli" , IIC_IntShift, []>; +def EXTSWSLIo : XS_RS5_RA5_SH5o<31, 445, "extswsli.", IIC_IntShift, []>; + +// Set Boolean +def SETB : X_RD5_BFA3<31, 128, (outs g8rc:$rD), (ins u3imm:$BFA), + "setb $rD, $BFA", IIC_IntGeneral, []>; Index: lib/Target/PowerPC/PPCInstrFormats.td =================================================================== --- lib/Target/PowerPC/PPCInstrFormats.td +++ lib/Target/PowerPC/PPCInstrFormats.td @@ -360,6 +360,22 @@ let Inst{30-31} = xo; } +// DX-Form: [PO RT d1 d0 XO d2] +class DX_RD5_IM16 opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list pattern> + : I { + bits<5> RD; + bits<16> IMM; + + let Pattern = pattern; + + let Inst{6-10} = RD; + // IMM = d0 || d1 || d2 + let Inst{11-15} = IMM{5-1}; // d1 + let Inst{16-25} = IMM{15-6}; // d0 + let Inst{26-30} = xo; + let Inst{31} = IMM{0}; // d2 +} // 1.7.6 X-Form class XForm_base_r3xo opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, @@ -754,6 +770,57 @@ let A = xo2; } +// [PO RT /// L /// XO /] +class X_RD5_L2 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list pattern> + : I { + bits<5> RD; + bits<2> L; + + let Pattern = pattern; + + let Inst{6-10} = RD; + let Inst{11-13} = 0; + let Inst{14-15} = L; + let Inst{16-20} = 0; + let Inst{21-30} = xo; + let Inst{31} = 0; +} + +// [PO RT BFA // /// XO /] +class X_RD5_BFA3 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list pattern> + : I { + bits<5> RD; + bits<3> BFA; + + let Pattern = pattern; + + let Inst{6-10} = RD; + let Inst{11-13} = BFA; + let Inst{14-20} = 0; + let Inst{21-30} = xo; + let Inst{31} = 0; +} + +// [PO BF / UIM FRB XO /] or [PO BF / UIM FRBp XO /] +class X_BF3_IM6_RS5 opcode, bits<10> xo, dag OOL, dag IOL, + string asmstr, InstrItinClass itin, list pattern> + : I { + bits<3> BF; + bits<6> UIM; + bits<5> FRB; + + let Pattern = pattern; + + let Inst{6-8} = BF; + let Inst{9} = 0; + let Inst{10-15} = UIM; + let Inst{16-20} = FRB; + let Inst{21-30} = xo; + let Inst{31} = 0; +} + // XX*-Form (VSX) class XX1Form opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> Index: lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- lib/Target/PowerPC/PPCInstrInfo.td +++ lib/Target/PowerPC/PPCInstrInfo.td @@ -4138,3 +4138,20 @@ def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>; def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>; def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>; + +// Add PC Immediate Shifted +def ADDPCIS : DX_RD5_IM16<19, 2, (outs gprc:$rD), (ins s16imm:$IMM), + "addpcis $rD, $IMM", IIC_IntSimple, []>; +def SUBPCIS : PPCAsmPseudo<"subpcis $rD, $IMM", (ins gprc:$rD, s16imm:$IMM)>; + +// Modulo {Signed/Unsigned}-Word +def MODSW : X_RT5_RA5_RB5<779, "modsw", gprc, IIC_IntDivW, []>; +def MODUW : X_RT5_RA5_RB5<267, "moduw", gprc, IIC_IntDivW, []>; + +// DFP Test Significance Immediate [Quad] +def DTSTSFI : X_BF3_IM6_RS5<59, 675, + (outs crbitrc:$BF), (ins u6imm:$UIM, f8rc:$FRB), + "dtstsfi $BF, $UIM, $FRB", IIC_FPGeneral, []>; +def DTSTSFIQ : X_BF3_IM6_RS5<63, 675, + (outs crbitrc:$BF), (ins u6imm:$UIM, f8rc:$FRB), + "dtstsfiq $BF, $UIM, $FRB", IIC_FPGeneral, []>; Index: lib/Target/PowerPC/README_P9.txt =================================================================== --- lib/Target/PowerPC/README_P9.txt +++ lib/Target/PowerPC/README_P9.txt @@ -116,3 +116,81 @@ . Provide builtin? (set f128:$vT, (int_ppc_vsx_xsrqpxp f128:$vB)) +Fixed Point Facility: +- Add PC Immediate Shifted: addpcis subpcis + . Thinking to use it on PC relative addressing mode? + +- 64-bit Fixed-Point Multiply-Add Low DWord: maddld + . SDAG: + (set i64:$rD, (add (mul $rA, $rB), $rC)) + +- 64-bit Fixed-Point Multiply-Add High-DWord/High-DWord-Unsigned: maddhd maddhdu + . Use intrinsic: + (set i64:$rD, (int_ppc_maddhd i64:$rA, i64:$rB), i64:$rC)) + (set i64:$rD, (int_ppc_maddhdu i64:$rA, i64:$rB), i64:$rC)) + +- Modulo {Signed/Unsigned}-{Word/DWord}: modsw moduw modsd modud + . Map modulo signed to llvm srem, modulo unsigned to urem because each pair + has same semantics, as follows: + + llvm srem: + 1. This instruction returns the remainder of a division (where the result is + either zero or has the same sign as the dividend, op1) + 2. Undefined behavior: + - % 0 + - Overflow: e.g. -2147483648 % -1 + In this case, the remainder doesn’t actually overflow, but this rule + lets srem be implemented using instructions that return both the result + of the division and the remainder. + + Modulo Signed: + 1. remainder = dividend - (quotient × divisor) + where + 0 ≤ remainder < |divisor|, if the dividend ≥ 0 + -|divisor| < remainder ≤ 0 , if the dividend < 0 + + 2. Undefined behavior: + - % 0 + - 0x8000_0000 % -1 + + . SDAG: + (set i32:$rD, (srem i32:$rA, i32:$rB)) // modsw + (set i32:$rD, (urem i32:$rA, i32:$rB)) // moduw + (set i64:$rD, (srem i64:$rA, i64:$rB)) // modsd + (set i64:$rD, (urem i64:$rA, i64:$rB)) // modud + + . Note: + The quotient is not supplied as a result in modulo word (32-bit) + instructions + +- Deliver A Random Number: darn + . Intrinsic? + (set i64:$rD, (int_ppc_darn i2:$L)) + + . Thinking for using it on c/c++ rand() implementation + +- Extend-Sign Word and Shift Left Immediate: extswsli extswsli. + . SDAG: + (set i64:$rA, shl((sext i32:$rS, i64), i6$SH)) + +- Set Boolean: setb + . Thinking to use it on: + + if (cond) + return true; + return false; + + . Need Intrinsic? + (set i64:rD, (int_ppc_setb i3:$BFA)) + +- DFP Test Significance Immediate [Quad]: dtstsfi dtstsfiq + . Do we need to implement DFP instructions?? + + . If we need: + - dtstsfiq requires paired register, we need to describe it, something like + this: + (outs crrc:$BF), (ins u6imm:$UIM, f8rc:$FRB, f8rc:$FRBp), + + RegConstraint<$FRBp = $FRB + 1>, NoEncode<"$FRBp">; + ^^^^^^^^^^^^^^^^ + Find correct way to implement this concept Index: test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt =================================================================== --- test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt +++ test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt @@ -2295,3 +2295,9 @@ # CHECK: attn 0x00 0x00 0x02 0x00 +# CHECK: dtstsfi 7, 63, 1 +0xef 0xbf 0x0d 0x46 + +# CHECK: dtstsfiq 4, 63, 4 +0xfe 0x3f 0x25 0x46 + Index: test/MC/Disassembler/PowerPC/ppc64-encoding.txt =================================================================== --- test/MC/Disassembler/PowerPC/ppc64-encoding.txt +++ test/MC/Disassembler/PowerPC/ppc64-encoding.txt @@ -662,3 +662,41 @@ 0x7d 0x40 0x61 0xe4 # CHECK: mfsrin 10, 12 0x7d 0x40 0x65 0x26 + +# Power9 Instructions: + +# CHECK: addpcis 1, -12345 +0x4c 0x23 0xcf 0xc5 + +# CHECK: maddhd 30, 27, 7, 2 +0x13 0xdb 0x38 0xb0 + +# CHECK: maddhdu 15, 12, 1, 3 +0x11 0xec 0x08 0xf1 + +# CHECK: maddld 13, 10, 6, 4 +0x11 0xaa 0x31 0x33 + +# CHECK: modsw 2, 3, 4 +0x7c 0x43 0x26 0x16 + +# CHECK: moduw 3, 7, 5 +0x7c 0x67 0x2a 0x16 + +# CHECK: modsd 10, 13, 14 +0x7d 0x4d 0x76 0x12 + +# CHECK: modud 21, 15, 27 +0x7e 0xaf 0xda 0x12 + +# CHECK: darn 31, 2 +0x7f 0xe2 0x05 0xe6 + +# CHECK: extswsli 15, 18, 63 +0x7e 0x4f 0xfe 0xf6 + +# CHECK: extswsli. 11, 27, 31 +0x7f 0x6b 0xfe 0xf5 + +# CHECK: setb 2, 7 +0x7c 0x5c 0x01 0x00 Index: test/MC/PowerPC/ppc64-encoding-ext.s =================================================================== --- test/MC/PowerPC/ppc64-encoding-ext.s +++ test/MC/PowerPC/ppc64-encoding-ext.s @@ -3666,3 +3666,14 @@ # CHECK-LE: attn # encoding: [0x00,0x02,0x00,0x00] attn +# Power9 Instructions: +# CHECK-BE: addpcis 1, -12345 # encoding: [0x4c,0x23,0xcf,0xc5] +# CHECK-LE: addpcis 1, -12345 # encoding: [0xc5,0xcf,0x23,0x4c] + subpcis 1, 12345 + +# CHECK-BE: dtstsfi 7, 63, 1 # encoding: [0xef,0xbf,0x0d,0x46] +# CHECK-LE: dtstsfi 7, 63, 1 # encoding: [0x46,0x0d,0xbf,0xef] + dtstsfi 7, 63, 1 +# CHECK-BE: dtstsfiq 4, 63, 4 # encoding: [0xfe,0x3f,0x25,0x46] +# CHECK-LE: dtstsfiq 4, 63, 4 # encoding: [0x46,0x25,0x3f,0xfe] + dtstsfiq 4, 63, 4 Index: test/MC/PowerPC/ppc64-encoding.s =================================================================== --- test/MC/PowerPC/ppc64-encoding.s +++ test/MC/PowerPC/ppc64-encoding.s @@ -848,3 +848,53 @@ # CHECK-BE: mfsrin 10, 12 # encoding: [0x7d,0x40,0x65,0x26] # CHECK-LE: mfsrin 10, 12 # encoding: [0x26,0x65,0x40,0x7d] mfsrin %r10,%r12 + +# Power9 Instructions: + +# Add PC Immediate Shifted +# CHECK-BE: addpcis 1, -12345 # encoding: [0x4c,0x23,0xcf,0xc5] +# CHECK-LE: addpcis 1, -12345 # encoding: [0xc5,0xcf,0x23,0x4c] + addpcis 1, -12345 + +# 64-bit Fixed-Point Multiply-Add High-DWord/High-DWord-Unsigned/Low-DWord +# CHECK-BE: maddhd 30, 27, 7, 2 # encoding: [0x13,0xdb,0x38,0xb0] +# CHECK-LE: maddhd 30, 27, 7, 2 # encoding: [0xb0,0x38,0xdb,0x13] + maddhd 30, 27, 7, 2 +# CHECK-BE: maddhdu 15, 12, 1, 3 # encoding: [0x11,0xec,0x08,0xf1] +# CHECK-LE: maddhdu 15, 12, 1, 3 # encoding: [0xf1,0x08,0xec,0x11] + maddhdu 15, 12, 1, 3 +# CHECK-BE: maddld 13, 10, 6, 4 # encoding: [0x11,0xaa,0x31,0x33] +# CHECK-LE: maddld 13, 10, 6, 4 # encoding: [0x33,0x31,0xaa,0x11] + maddld 13, 10, 6, 4 + +# Modulo {Signed/Unsigned}-{Word/DWord} +# CHECK-BE: modsw 2, 3, 4 # encoding: [0x7c,0x43,0x26,0x16] +# CHECK-LE: modsw 2, 3, 4 # encoding: [0x16,0x26,0x43,0x7c] + modsw 2, 3, 4 +# CHECK-BE: moduw 3, 7, 5 # encoding: [0x7c,0x67,0x2a,0x16] +# CHECK-LE: moduw 3, 7, 5 # encoding: [0x16,0x2a,0x67,0x7c] + moduw 3, 7, 5 +# CHECK-BE: modsd 10, 13, 14 # encoding: [0x7d,0x4d,0x76,0x12] +# CHECK-LE: modsd 10, 13, 14 # encoding: [0x12,0x76,0x4d,0x7d] + modsd 10, 13, 14 +# CHECK-BE: modud 21, 15, 27 # encoding: [0x7e,0xaf,0xda,0x12] +# CHECK-LE: modud 21, 15, 27 # encoding: [0x12,0xda,0xaf,0x7e] + modud 21, 15, 27 + +# Deliver A Random Number +# CHECK-BE: darn 31, 2 # encoding: [0x7f,0xe2,0x05,0xe6] +# CHECK-LE: darn 31, 2 # encoding: [0xe6,0x05,0xe2,0x7f] + darn 31, 2 + +# Extend-Sign Word and Shift Left Immediate +# CHECK-BE: extswsli 15, 18, 63 # encoding: [0x7e,0x4f,0xfe,0xf6] +# CHECK-LE: extswsli 15, 18, 63 # encoding: [0xf6,0xfe,0x4f,0x7e] + extswsli 15, 18, 63 +# CHECK-BE: extswsli. 11, 27, 31 # encoding: [0x7f,0x6b,0xfe,0xf5] +# CHECK-LE: extswsli. 11, 27, 31 # encoding: [0xf5,0xfe,0x6b,0x7f] + extswsli. 11, 27, 31 + +# Set Boolean +# CHECK-BE: setb 2, 7 # encoding: [0x7c,0x5c,0x01,0x00] +# CHECK-LE: setb 2, 7 # encoding: [0x00,0x01,0x5c,0x7c] + setb 2, 7