Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -275,7 +275,7 @@
   if (isSMRD(*LdSt)) {
     const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
                                                       AMDGPU::OpName::offset);
-    if (!OffsetImm)
+    if (!OffsetImm || !OffsetImm->isImm()) // there might be SReg offset
       return false;
 
     const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
Index: lib/Target/AMDGPU/SIInstrInfo.td
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.td
+++ lib/Target/AMDGPU/SIInstrInfo.td
@@ -1087,7 +1087,7 @@
         def _si : SMRD_Real_si <op.SI, opName, 0, (outs), (ins), opName>;
       }
 
-      let glc = 0, sdata = 0 in {
+      let glc = 0, sdst = 0 in {
         def _vi : SMRD_Real_vi <op.VI, opName, 0, (outs), (ins), opName>;
       }
     }
@@ -1099,7 +1099,7 @@
   let hasSideEffects = 1;
   let mayStore = 1;
   let sbase = 0;
-  let sdata = 0;
+  let sdst = 0;
   let glc = 0;
   let offset = 0;
 }
@@ -1107,22 +1107,22 @@
 multiclass SMRD_Helper <smrd op, string opName, RegisterClass baseClass,
                         RegisterClass dstClass> {
   defm _IMM : SMRD_m <
-    op, opName#"_IMM", 1, (outs dstClass:$dst),
+    op, opName#"_IMM", 1, (outs dstClass:$sdst),
     (ins baseClass:$sbase, smrd_offset:$offset),
-    opName#" $dst, $sbase, $offset", []
+    opName#" $sdst, $sbase, $offset", []
   >;
 
   def _IMM_ci : SMRD <
-    (outs dstClass:$dst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
-    opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
+    (outs dstClass:$sdst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
+    opName#" $sdst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
     let AssemblerPredicates = [isCIOnly];
     let DecoderNamespace = "CI";
   }
 
   defm _SGPR : SMRD_m <
-    op, opName#"_SGPR", 0, (outs dstClass:$dst),
-    (ins baseClass:$sbase, SReg_32:$soff),
-    opName#" $dst, $sbase, $soff", []
+    op, opName#"_SGPR", 0, (outs dstClass:$sdst),
+    (ins baseClass:$sbase, SReg_32:$offset),
+    opName#" $sdst, $sbase, $offset", [] 
   >;
 }
 
Index: lib/Target/AMDGPU/VIInstrFormats.td
===================================================================
--- lib/Target/AMDGPU/VIInstrFormats.td
+++ lib/Target/AMDGPU/VIInstrFormats.td
@@ -91,12 +91,12 @@
 
 class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
   bits<7>  sbase;
-  bits<7>  sdata;
+  bits<7>  sdst;
   bits<1>  glc;
   bits<20> offset;
 
   let Inst{5-0}   = sbase{6-1};
-  let Inst{12-6}  = sdata;
+  let Inst{12-6}  = sdst;
   let Inst{16}    = glc;
   let Inst{17}    = imm;
   let Inst{25-18} = op;