Index: include/llvm/Support/TargetRegistry.h =================================================================== --- include/llvm/Support/TargetRegistry.h +++ include/llvm/Support/TargetRegistry.h @@ -113,8 +113,8 @@ typedef AsmPrinter *(*AsmPrinterCtorTy)( TargetMachine &TM, std::unique_ptr &&Streamer); typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); typedef MCTargetAsmParser *(*MCAsmParserCtorTy)( const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII, const MCTargetOptions &Options); @@ -370,13 +370,11 @@ } /// createMCAsmBackend - Create a target specific assembly parser. - /// - /// \param TheTriple The target triple string. - MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI, - StringRef TheTriple, StringRef CPU) const { + MCAsmBackend *createMCAsmBackend(const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) const { if (!MCAsmBackendCtorFn) return nullptr; - return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU); + return MCAsmBackendCtorFn(*this, STI, MRI); } /// createMCAsmParser - Create a target specific assembly parser. Index: lib/CodeGen/LLVMTargetMachine.cpp =================================================================== --- lib/CodeGen/LLVMTargetMachine.cpp +++ lib/CodeGen/LLVMTargetMachine.cpp @@ -213,8 +213,7 @@ if (Options.MCOptions.ShowMCEncoding) MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context); - MCAsmBackend *MAB = - getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU); + MCAsmBackend *MAB = getTarget().createMCAsmBackend(STI, MRI); auto FOut = llvm::make_unique(Out); MCStreamer *S = getTarget().createAsmStreamer( *Context, std::move(FOut), Options.MCOptions.AsmVerbose, @@ -227,8 +226,7 @@ // Create the code emitter for the target if it exists. If not, .o file // emission fails. MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context); - MCAsmBackend *MAB = - getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU); + MCAsmBackend *MAB = getTarget().createMCAsmBackend(STI, MRI); if (!MCE || !MAB) return true; @@ -283,7 +281,7 @@ MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx); MCAsmBackend *MAB = - getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU); + getTarget().createMCAsmBackend(*getMCSubtargetInfo(), MRI); if (!MCE || !MAB) return true; Index: lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp +++ lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp @@ -570,9 +570,10 @@ } MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TheTriple, - StringRef CPU) { + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + const Triple &TheTriple = STI.getTargetTriple(); + if (TheTriple.isOSBinFormatMachO()) return new DarwinAArch64AsmBackend(T, MRI); @@ -582,9 +583,10 @@ } MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TheTriple, - StringRef CPU) { + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + const Triple &TheTriple = STI.getTargetTriple(); + assert(TheTriple.isOSBinFormatELF() && "Big endian is only supported for ELF targets!"); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); Index: lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h +++ lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h @@ -42,11 +42,11 @@ const MCRegisterInfo &MRI, MCContext &Ctx); MCAsmBackend *createAArch64leAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const MCSubtargetInfo &MST, + const MCRegisterInfo &MRI); MCAsmBackend *createAArch64beAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const MCSubtargetInfo &MST, + const MCRegisterInfo &MRI); MCObjectWriter *createAArch64ELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -188,8 +188,9 @@ } // end anonymous namespace MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { // Use 64-bit ELF for amdgcn - return new ELFAMDGPUAsmBackend(T, TT.getArch() == Triple::amdgcn); + return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple().getArch() == + Triple::amdgcn); } Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h @@ -43,8 +43,9 @@ const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); +MCAsmBackend *createAMDGPUAsmBackend(const Target &T, + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit, raw_pwrite_stream &OS); Index: lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -1108,7 +1108,7 @@ MCAsmBackend *llvm::createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TheTriple, StringRef CPU, + const Triple &TheTriple, bool isLittle) { switch (TheTriple.getObjectFormat()) { default: @@ -1128,25 +1128,25 @@ } MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { - return createARMAsmBackend(T, MRI, TT, CPU, true); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + return createARMAsmBackend(T, MRI, Triple(STI.getTargetTriple()), true); } MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { - return createARMAsmBackend(T, MRI, TT, CPU, false); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + return createARMAsmBackend(T, MRI, Triple(STI.getTargetTriple()), false); } MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { - return createARMAsmBackend(T, MRI, TT, CPU, true); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + return createARMAsmBackend(T, MRI, Triple(STI.getTargetTriple()), true); } MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { - return createARMAsmBackend(T, MRI, TT, CPU, false); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + return createARMAsmBackend(T, MRI, Triple(STI.getTargetTriple()), false); } Index: lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h +++ lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h @@ -65,22 +65,21 @@ MCContext &Ctx); MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU, - bool IsLittleEndian); + const Triple &TT, bool IsLittleEndian); -MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); +MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); -MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); +MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); MCAsmBackend *createThumbLEAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); MCAsmBackend *createThumbBEAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); // Construct a PE/COFF machine code streamer which will generate a PE/COFF // object file. Index: lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h =================================================================== --- lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h +++ lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h @@ -37,8 +37,8 @@ MCContext &Ctx); /// Creates an assembly backend for AVR. -MCAsmBackend *createAVRAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); +MCAsmBackend *createAVRAsmBackend(const Target &T, const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); /// Creates an ELF object writer for AVR. MCObjectWriter *createAVRELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI); Index: lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp =================================================================== --- lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp +++ lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp @@ -94,13 +94,13 @@ } MCAsmBackend *llvm::createBPFAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { return new BPFAsmBackend(/*IsLittleEndian=*/true); } MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { return new BPFAsmBackend(/*IsLittleEndian=*/false); } Index: lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h =================================================================== --- lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h +++ lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h @@ -42,10 +42,10 @@ const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); -MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); +MCAsmBackend *createBPFAsmBackend(const Target &T, const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); +MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); MCObjectWriter *createBPFELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool IsLittleEndian); Index: lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -743,9 +743,10 @@ namespace llvm { MCAsmBackend *createHexagonAsmBackend(Target const &T, - MCRegisterInfo const & /*MRI*/, - const Triple &TT, StringRef CPU) { - uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); - return new HexagonAsmBackend(T, OSABI, CPU); + const MCSubtargetInfo &STI, + MCRegisterInfo const & /*MRI*/) { + uint8_t OSABI = + MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS()); + return new HexagonAsmBackend(T, OSABI, STI.getCPU()); } } Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -46,8 +46,8 @@ MCContext &MCT); MCAsmBackend *createHexagonAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, StringRef CPU); Index: lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp =================================================================== --- lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp +++ lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp @@ -158,9 +158,10 @@ } // namespace MCAsmBackend *llvm::createLanaiAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TheTriple, - StringRef CPU) { + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + const Triple &TheTriple = STI.getTargetTriple(); + if (!TheTriple.isOSBinFormatELF()) llvm_unreachable("OS not supported"); Index: lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h =================================================================== --- lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h +++ lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h @@ -37,8 +37,8 @@ const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TheTriple, StringRef CPU); +MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); MCObjectWriter *createLanaiELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI); Index: lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -481,28 +481,31 @@ // MCAsmBackend MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { - return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + return new MipsAsmBackend(T, STI.getTargetTriple().getOS(), /*IsLittle*/ true, /*Is64Bit*/ false); } MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { - return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + return new MipsAsmBackend(T, STI.getTargetTriple().getOS(), + /*IsLittle*/ false, /*Is64Bit*/ false); } MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { - return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + return new MipsAsmBackend(T, STI.getTargetTriple().getOS(), /*IsLittle*/ true, + /*Is64Bit*/ true); } MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { - return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + return new MipsAsmBackend(T, STI.getTargetTriple().getOS(), + /*IsLittle*/ false, /*Is64Bit*/ true); } Index: lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -43,17 +43,17 @@ MCContext &Ctx); MCAsmBackend *createMipsAsmBackendEB32(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); MCAsmBackend *createMipsAsmBackendEL32(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); MCAsmBackend *createMipsAsmBackendEB64(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); MCAsmBackend *createMipsAsmBackendEL64(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool IsLittleEndian, bool Is64Bit); Index: lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -229,8 +229,10 @@ } // end anonymous namespace MCAsmBackend *llvm::createPPCAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + const Triple &TT = STI.getTargetTriple(); + if (TT.isOSDarwin()) return new DarwinPPCAsmBackend(T); Index: lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h +++ lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h @@ -42,8 +42,8 @@ const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); +MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); /// Construct an PPC ELF object writer. MCObjectWriter *createPPCELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, Index: lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp =================================================================== --- lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -298,7 +298,7 @@ } // end anonymous namespace MCAsmBackend *llvm::createSparcAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { - return new ELFSparcAsmBackend(T, TT.getOS()); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS()); } Index: lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h =================================================================== --- lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h +++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h @@ -37,8 +37,8 @@ MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); +MCAsmBackend *createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, bool IsLIttleEndian, uint8_t OSABI); } // End llvm namespace Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp =================================================================== --- lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp @@ -110,8 +110,9 @@ } MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { - uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + uint8_t OSABI = + MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS()); return new SystemZMCAsmBackend(OSABI); } Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h =================================================================== --- lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h @@ -84,8 +84,8 @@ MCContext &Ctx); MCAsmBackend *createSystemZMCAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); MCObjectWriter *createSystemZObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI); } // end namespace llvm Index: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp =================================================================== --- lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp +++ lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp @@ -82,9 +82,9 @@ } static MCAsmBackend *createAsmBackend(const Target & /*T*/, - const MCRegisterInfo & /*MRI*/, - const Triple &TT, StringRef /*CPU*/) { - return createWebAssemblyAsmBackend(TT); + const MCSubtargetInfo &STI, + const MCRegisterInfo & /*MRI*/) { + return createWebAssemblyAsmBackend(Triple(STI.getTargetTriple())); } static MCSubtargetInfo *createMCSubtargetInfo(const Triple &TT, StringRef CPU, Index: lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp =================================================================== --- lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp +++ lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp @@ -58,6 +58,18 @@ } } +static unsigned getMaxNopLength(const MCSubtargetInfo &STI, bool HasNopl) { + if (!HasNopl) { + // If true long nops are not supported we're going to use alternative nops, + // however not all of them are correct in 64 bit mode. Ideally we should + // never be here in 64 bit mode since only 32-bit-only CPUs don't support + // true long nops, but if we are here nevertheless we will generate only + // those nops which are correct. + return STI.getFeatureBits()[X86::Mode64Bit] ? 2 : 7; + } else + return STI.getFeatureBits()[X86::FeatureFastNop7] ? 7 : 15; +} + namespace { class X86ELFObjectWriter : public MCELFObjectTargetWriter { @@ -68,24 +80,13 @@ }; class X86AsmBackend : public MCAsmBackend { - const StringRef CPU; - bool HasNopl; - uint64_t MaxNopLength; + const bool HasNopl; + const uint64_t MaxNopLength; public: - X86AsmBackend(const Target &T, StringRef CPU) : MCAsmBackend(), CPU(CPU) { - HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" && - CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" && - CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" && - CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" && - CPU != "c3" && CPU != "c3-2"; - - // Max length of true long nop instruction is 15 bytes. - // Max length of long nop replacement instruction is 7 bytes. - // Taking into account Silvermont and Lakemont architecture features max - // length of nops is reduced for them to achieve a better performance. - MaxNopLength = (!HasNopl || CPU == "slm" || CPU == "lakemont") ? 7 : 15; - } + X86AsmBackend(const Target &T, const MCSubtargetInfo &STI) + : MCAsmBackend(), HasNopl(STI.getFeatureBits()[X86::FeatureLongNop]), + MaxNopLength(getMaxNopLength(STI, HasNopl)) {} unsigned getNumFixupKinds() const override { return X86::NumTargetFixupKinds; @@ -374,14 +375,15 @@ class ELFX86AsmBackend : public X86AsmBackend { public: uint8_t OSABI; - ELFX86AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) - : X86AsmBackend(T, CPU), OSABI(OSABI) {} + ELFX86AsmBackend(const Target &T, const MCSubtargetInfo &STI, uint8_t OSABI) + : X86AsmBackend(T, STI), OSABI(OSABI) {} }; class ELFX86_32AsmBackend : public ELFX86AsmBackend { public: - ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) - : ELFX86AsmBackend(T, OSABI, CPU) {} + ELFX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, + uint8_t OSABI) + : ELFX86AsmBackend(T, STI, OSABI) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386); @@ -390,8 +392,9 @@ class ELFX86_X32AsmBackend : public ELFX86AsmBackend { public: - ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) - : ELFX86AsmBackend(T, OSABI, CPU) {} + ELFX86_X32AsmBackend(const Target &T, const MCSubtargetInfo &STI, + uint8_t OSABI) + : ELFX86AsmBackend(T, STI, OSABI) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, @@ -401,8 +404,9 @@ class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend { public: - ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) - : ELFX86AsmBackend(T, OSABI, CPU) {} + ELFX86_IAMCUAsmBackend(const Target &T, const MCSubtargetInfo &STI, + uint8_t OSABI) + : ELFX86AsmBackend(T, STI, OSABI) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, @@ -412,11 +416,13 @@ class ELFX86_64AsmBackend : public ELFX86AsmBackend { public: - ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) - : ELFX86AsmBackend(T, OSABI, CPU) {} + ELFX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, + uint8_t OSABI) + : ELFX86AsmBackend(T, STI, OSABI) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { - return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64); + return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, + ELF::EM_X86_64); } }; @@ -424,10 +430,9 @@ bool Is64Bit; public: - WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU) - : X86AsmBackend(T, CPU) - , Is64Bit(is64Bit) { - } + WindowsX86AsmBackend(const Target &T, const MCSubtargetInfo &STI, + bool is64Bit) + : X86AsmBackend(T, STI), Is64Bit(is64Bit) {} Optional getFixupKind(StringRef Name) const override { return StringSwitch>(Name) @@ -778,9 +783,9 @@ } public: - DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU, - bool Is64Bit) - : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) { + DarwinX86AsmBackend(const Target &T, const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI, bool Is64Bit) + : X86AsmBackend(T, STI), MRI(MRI), Is64Bit(Is64Bit) { memset(SavedRegs, 0, sizeof(SavedRegs)); OffsetSize = Is64Bit ? 8 : 4; MoveInstrSize = Is64Bit ? 3 : 2; @@ -790,9 +795,9 @@ class DarwinX86_32AsmBackend : public DarwinX86AsmBackend { public: - DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef CPU) - : DarwinX86AsmBackend(T, MRI, CPU, false) {} + DarwinX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) + : DarwinX86AsmBackend(T, STI, MRI, false) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createX86MachObjectWriter(OS, /*Is64Bit=*/false, @@ -802,17 +807,18 @@ /// \brief Generate the compact unwind encoding for the CFI instructions. uint32_t generateCompactUnwindEncoding( - ArrayRef Instrs) const override { + ArrayRef Instrs) const override { return generateCompactUnwindEncodingImpl(Instrs); } }; class DarwinX86_64AsmBackend : public DarwinX86AsmBackend { const MachO::CPUSubTypeX86 Subtype; + public: - DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef CPU, MachO::CPUSubTypeX86 st) - : DarwinX86AsmBackend(T, MRI, CPU, true), Subtype(st) {} + DarwinX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI, MachO::CPUSubTypeX86 st) + : DarwinX86AsmBackend(T, STI, MRI, true), Subtype(st) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createX86MachObjectWriter(OS, /*Is64Bit=*/true, @@ -821,7 +827,7 @@ /// \brief Generate the compact unwind encoding for the CFI instructions. uint32_t generateCompactUnwindEncoding( - ArrayRef Instrs) const override { + ArrayRef Instrs) const override { return generateCompactUnwindEncodingImpl(Instrs); } }; @@ -829,41 +835,43 @@ } // end anonymous namespace MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TheTriple, - StringRef CPU) { + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + const Triple &TheTriple = STI.getTargetTriple(); + if (TheTriple.isOSBinFormatMachO()) - return new DarwinX86_32AsmBackend(T, MRI, CPU); + return new DarwinX86_32AsmBackend(T, STI, MRI); if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF()) - return new WindowsX86AsmBackend(T, false, CPU); + return new WindowsX86AsmBackend(T, STI, false); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); if (TheTriple.isOSIAMCU()) - return new ELFX86_IAMCUAsmBackend(T, OSABI, CPU); + return new ELFX86_IAMCUAsmBackend(T, STI, OSABI); - return new ELFX86_32AsmBackend(T, OSABI, CPU); + return new ELFX86_32AsmBackend(T, STI, OSABI); } MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, - const MCRegisterInfo &MRI, - const Triple &TheTriple, - StringRef CPU) { + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI) { + const Triple &TheTriple = STI.getTargetTriple(); + if (TheTriple.isOSBinFormatMachO()) { MachO::CPUSubTypeX86 CS = StringSwitch(TheTriple.getArchName()) .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H) .Default(MachO::CPU_SUBTYPE_X86_64_ALL); - return new DarwinX86_64AsmBackend(T, MRI, CPU, CS); + return new DarwinX86_64AsmBackend(T, STI, MRI, CS); } if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF()) - return new WindowsX86AsmBackend(T, true, CPU); + return new WindowsX86AsmBackend(T, STI, true); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); if (TheTriple.getEnvironment() == Triple::GNUX32) - return new ELFX86_X32AsmBackend(T, OSABI, CPU); - return new ELFX86_64AsmBackend(T, OSABI, CPU); + return new ELFX86_X32AsmBackend(T, STI, OSABI); + return new ELFX86_64AsmBackend(T, STI, OSABI); } Index: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h =================================================================== --- lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h +++ lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h @@ -68,10 +68,12 @@ const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); -MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); +MCAsmBackend *createX86_32AsmBackend(const Target &T, + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); +MCAsmBackend *createX86_64AsmBackend(const Target &T, + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI); /// Construct an X86 Windows COFF machine code streamer which will generate /// PE/COFF format object files. Index: lib/Target/X86/X86.td =================================================================== --- lib/Target/X86/X86.td +++ lib/Target/X86/X86.td @@ -34,6 +34,12 @@ def FeatureX87 : SubtargetFeature<"x87","HasX87", "true", "Enable X87 float instructions">; +def FeatureLongNop : SubtargetFeature<"long-nop", "HasLongNop", "true", + "Support long nop instructions">; + +def FeatureFastNop7 : SubtargetFeature<"fast-nop-7", "HasFastNop7", "true", + "Long nops larger than 7 are slow">; + def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", "Enable conditional move instructions">; @@ -91,7 +97,7 @@ // without disabling 64-bit mode. def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", "Support 64-bit instructions", - [FeatureCMOV]>; + [FeatureLongNop, FeatureCMOV]>; def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true", "64-bit with cmpxchg16b", [Feature64Bit]>; @@ -271,13 +277,15 @@ def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16]>; def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16]>; -def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>; +def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV, + FeatureLongNop]>; def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, - FeatureCMOV, FeatureFXSR]>; + FeatureCMOV, FeatureFXSR, FeatureLongNop]>; def : Proc<"pentium3", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, - FeatureSSE1, FeatureFXSR]>; + FeatureSSE1, FeatureFXSR, FeatureLongNop]>; def : Proc<"pentium3m", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, - FeatureSSE1, FeatureFXSR, FeatureSlowBTMem]>; + FeatureSSE1, FeatureFXSR, FeatureSlowBTMem, + FeatureLongNop]>; // Enable the PostRAScheduler for SSE2 and SSE3 class cpus. // The intent is to enable it for pentium4 which is the current default @@ -291,28 +299,30 @@ def : ProcessorModel<"pentium-m", GenericPostRAModel, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, - FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>; + FeatureSSE2, FeatureFXSR, FeatureSlowBTMem, + FeatureLongNop]>; def : ProcessorModel<"pentium4", GenericPostRAModel, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, - FeatureSSE2, FeatureFXSR]>; + FeatureSSE2, FeatureFXSR, FeatureLongNop]>; def : ProcessorModel<"pentium4m", GenericPostRAModel, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, - FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>; + FeatureSSE2, FeatureFXSR, FeatureSlowBTMem, + FeatureLongNop]>; // Intel Quark. -def : Proc<"lakemont", []>; +def : Proc<"lakemont", [FeatureLongNop, FeatureFastNop7]>; // Intel Core Duo. def : ProcessorModel<"yonah", SandyBridgeModel, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, - FeatureFXSR, FeatureSlowBTMem]>; + FeatureFXSR, FeatureSlowBTMem, FeatureLongNop]>; // NetBurst. def : ProcessorModel<"prescott", GenericPostRAModel, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, - FeatureFXSR, FeatureSlowBTMem]>; + FeatureFXSR, FeatureSlowBTMem, FeatureLongNop]>; def : ProcessorModel<"nocona", GenericPostRAModel, [ FeatureX87, FeatureSlowUAMem16, @@ -320,7 +330,8 @@ FeatureSSE3, FeatureFXSR, FeatureCMPXCHG16B, - FeatureSlowBTMem + FeatureSlowBTMem, + FeatureLongNop ]>; // Intel Core 2 Solo/Duo. @@ -332,7 +343,8 @@ FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem, - FeatureLAHFSAHF + FeatureLAHFSAHF, + FeatureLongNop ]>; def : ProcessorModel<"penryn", SandyBridgeModel, [ FeatureX87, @@ -342,7 +354,8 @@ FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem, - FeatureLAHFSAHF + FeatureLAHFSAHF, + FeatureLongNop ]>; // Atom CPUs. @@ -362,7 +375,8 @@ FeatureCallRegIndirect, FeatureLEAUsesAG, FeaturePadShortFunctions, - FeatureLAHFSAHF + FeatureLAHFSAHF, + FeatureLongNop ]>; def : BonnellProc<"bonnell">; def : BonnellProc<"atom">; // Pin the generic name to the baseline. @@ -384,7 +398,9 @@ FeatureSlowLEA, FeatureSlowIncDec, FeatureSlowBTMem, - FeatureLAHFSAHF + FeatureLAHFSAHF, + FeatureLongNop, + FeatureFastNop7 ]>; def : SilvermontProc<"silvermont">; def : SilvermontProc<"slm">; // Legacy alias. @@ -398,7 +414,8 @@ FeatureCMPXCHG16B, FeatureSlowBTMem, FeaturePOPCNT, - FeatureLAHFSAHF + FeatureLAHFSAHF, + FeatureLongNop ]>; def : NehalemProc<"nehalem">; def : NehalemProc<"corei7">; @@ -415,7 +432,8 @@ FeaturePOPCNT, FeatureAES, FeaturePCLMUL, - FeatureLAHFSAHF + FeatureLAHFSAHF, + FeatureLongNop ]>; def : WestmereProc<"westmere">; @@ -442,7 +460,8 @@ FeaturePCLMUL, FeatureXSAVE, FeatureXSAVEOPT, - FeatureLAHFSAHF + FeatureLAHFSAHF, + FeatureLongNop ]>; class SandyBridgeProc : ProcModel; def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; def : Proc<"athlon", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA, - FeatureSlowBTMem, FeatureSlowSHLD]>; + FeatureSlowBTMem, FeatureSlowSHLD, + FeatureLongNop]>; def : Proc<"athlon-tbird", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA, - FeatureSlowBTMem, FeatureSlowSHLD]>; + FeatureSlowBTMem, FeatureSlowSHLD, + FeatureLongNop]>; def : Proc<"athlon-4", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureSlowBTMem, - FeatureSlowSHLD]>; + FeatureSlowSHLD, FeatureLongNop]>; def : Proc<"athlon-xp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureSlowBTMem, - FeatureSlowSHLD]>; + FeatureSlowSHLD, FeatureLongNop]>; def : Proc<"athlon-mp", [FeatureX87, FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureSlowBTMem, - FeatureSlowSHLD]>; + FeatureSlowSHLD, FeatureLongNop]>; def : Proc<"k8", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA, FeatureFXSR, Feature64Bit, - FeatureSlowBTMem, FeatureSlowSHLD]>; + FeatureSlowBTMem, FeatureSlowSHLD, + FeatureLongNop]>; def : Proc<"opteron", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA, FeatureFXSR, Feature64Bit, - FeatureSlowBTMem, FeatureSlowSHLD]>; + FeatureSlowBTMem, FeatureSlowSHLD, + FeatureLongNop]>; def : Proc<"athlon64", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA, FeatureFXSR, Feature64Bit, - FeatureSlowBTMem, FeatureSlowSHLD]>; + FeatureSlowBTMem, FeatureSlowSHLD, + FeatureLongNop]>; def : Proc<"athlon-fx", [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA, FeatureFXSR, Feature64Bit, - FeatureSlowBTMem, FeatureSlowSHLD]>; + FeatureSlowBTMem, FeatureSlowSHLD, + FeatureLongNop]>; def : Proc<"k8-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B, - FeatureSlowBTMem, FeatureSlowSHLD]>; + FeatureSlowBTMem, FeatureSlowSHLD, + FeatureLongNop]>; def : Proc<"opteron-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B, - FeatureSlowBTMem, FeatureSlowSHLD]>; + FeatureSlowBTMem, FeatureSlowSHLD, + FeatureLongNop]>; def : Proc<"athlon64-sse3", [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B, - FeatureSlowBTMem, FeatureSlowSHLD]>; + FeatureSlowBTMem, FeatureSlowSHLD, + FeatureLongNop]>; def : Proc<"amdfam10", [FeatureX87, FeatureSSE4A, Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD, - FeatureLAHFSAHF]>; + FeatureLAHFSAHF, FeatureLongNop]>; def : Proc<"barcelona", [FeatureX87, FeatureSSE4A, Feature3DNowA, FeatureFXSR, FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT, FeatureSlowBTMem, FeatureSlowSHLD, - FeatureLAHFSAHF]>; + FeatureLAHFSAHF, FeatureLongNop]>; // Bobcat def : Proc<"btver1", [ @@ -613,7 +641,8 @@ FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD, - FeatureLAHFSAHF + FeatureLAHFSAHF, + FeatureLongNop ]>; // Jaguar @@ -636,7 +665,8 @@ FeatureXSAVEOPT, FeatureSlowSHLD, FeatureLAHFSAHF, - FeatureFastPartialYMMWrite + FeatureFastPartialYMMWrite, + FeatureLongNop ]>; // Bulldozer @@ -656,7 +686,8 @@ FeaturePOPCNT, FeatureXSAVE, FeatureSlowSHLD, - FeatureLAHFSAHF + FeatureLAHFSAHF, + FeatureLongNop ]>; // Piledriver def : Proc<"bdver2", [ @@ -679,7 +710,8 @@ FeatureTBM, FeatureFMA, FeatureSlowSHLD, - FeatureLAHFSAHF + FeatureLAHFSAHF, + FeatureLongNop ]>; // Steamroller @@ -705,7 +737,8 @@ FeatureXSAVEOPT, FeatureSlowSHLD, FeatureFSGSBase, - FeatureLAHFSAHF + FeatureLAHFSAHF, + FeatureLongNop ]>; // Excavator @@ -731,7 +764,8 @@ FeatureXSAVEOPT, FeatureFSGSBase, FeatureLAHFSAHF, - FeatureMWAITX + FeatureMWAITX, + FeatureLongNop ]>; def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>; @@ -754,7 +788,7 @@ // forming a common base for them. def : ProcessorModel<"x86-64", SandyBridgeModel, [FeatureX87, FeatureMMX, FeatureSSE2, FeatureFXSR, - Feature64Bit, FeatureSlowBTMem ]>; + Feature64Bit, FeatureSlowBTMem, FeatureLongNop]>; //===----------------------------------------------------------------------===// // Register File Description Index: lib/Target/X86/X86Subtarget.h =================================================================== --- lib/Target/X86/X86Subtarget.h +++ lib/Target/X86/X86Subtarget.h @@ -75,6 +75,12 @@ /// True if the processor supports X87 instructions. bool HasX87; + /// True if the processor supports long nop instructions. + bool HasLongNop; + + /// True if the processor is better to use long nops shorter or equal to 7. + bool HasFastNop7; + /// True if this processor has conditional move instructions /// (generally pentium pro+). bool HasCMov; @@ -455,6 +461,9 @@ bool isSLM() const { return X86ProcFamily == IntelSLM; } bool useSoftFloat() const { return UseSoftFloat; } + bool hasLongNop() const { return HasLongNop; } + bool hasFastNop7() const { return HasFastNop7; } + /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for /// no-sse2). There isn't any reason to disable it if the target processor /// supports it. Index: lib/Target/X86/X86Subtarget.cpp =================================================================== --- lib/Target/X86/X86Subtarget.cpp +++ lib/Target/X86/X86Subtarget.cpp @@ -243,6 +243,8 @@ X86SSELevel = NoSSE; X863DNowLevel = NoThreeDNow; HasX87 = false; + HasLongNop = false; + HasFastNop7 = false; HasCMov = false; HasX86_64 = false; HasPOPCNT = false; Index: test/MC/COFF/align-nops.s =================================================================== --- test/MC/COFF/align-nops.s +++ test/MC/COFF/align-nops.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | llvm-readobj -s -sd | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 -mcpu=pentium4 %s | llvm-readobj -s -sd | FileCheck %s // Test that we get optimal nops in text .text Index: test/MC/ELF/align-nops.s =================================================================== --- test/MC/ELF/align-nops.s +++ test/MC/ELF/align-nops.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 %s -o - | llvm-readobj -s -sd | FileCheck %s // Test that we get optimal nops in text .text Index: test/MC/MachO/x86_32-optimal_nop.s =================================================================== --- test/MC/MachO/x86_32-optimal_nop.s +++ test/MC/MachO/x86_32-optimal_nop.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | llvm-readobj -file-headers -s -sd -r -t -macho-segment -macho-dysymtab -macho-indirect-symbols | FileCheck %s +// RUN: llvm-mc -triple i386-apple-darwin9 -mcpu=pentium4 %s -filetype=obj -o - | llvm-readobj -file-headers -s -sd -r -t -macho-segment -macho-dysymtab -macho-indirect-symbols | FileCheck %s # 1 byte nop test .align 4, 0 # start with 16 byte alignment filled with zeros Index: test/MC/X86/AlignedBundling/autogen-inst-offset-align-to-end.s =================================================================== --- test/MC/X86/AlignedBundling/autogen-inst-offset-align-to-end.s +++ test/MC/X86/AlignedBundling/autogen-inst-offset-align-to-end.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -o - \ +# RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu -mcpu=pentium4 %s -o - \ # RUN: | llvm-objdump -triple i386 -disassemble -no-show-raw-insn - | FileCheck %s # !!! This test is auto-generated from utils/testgen/mc-bundling-x86-gen.py !!! Index: test/MC/X86/AlignedBundling/autogen-inst-offset-padding.s =================================================================== --- test/MC/X86/AlignedBundling/autogen-inst-offset-padding.s +++ test/MC/X86/AlignedBundling/autogen-inst-offset-padding.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -o - \ +# RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu -mcpu=pentium4 %s -o - \ # RUN: | llvm-objdump -triple i386 -disassemble -no-show-raw-insn - | FileCheck %s # !!! This test is auto-generated from utils/testgen/mc-bundling-x86-gen.py !!! Index: test/MC/X86/AlignedBundling/long-nop-pad.s =================================================================== --- test/MC/X86/AlignedBundling/long-nop-pad.s +++ test/MC/X86/AlignedBundling/long-nop-pad.s @@ -1,6 +1,6 @@ -# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \ +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s -# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s # Test that long nops are generated for padding where possible. Index: test/MC/X86/AlignedBundling/misaligned-bundle-group.s =================================================================== --- test/MC/X86/AlignedBundling/misaligned-bundle-group.s +++ test/MC/X86/AlignedBundling/misaligned-bundle-group.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - \ +# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mcpu=pentium4 %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - \ # RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-OPT %s -# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - \ # RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-RELAX %s Index: test/MC/X86/AlignedBundling/misaligned-bundle.s =================================================================== --- test/MC/X86/AlignedBundling/misaligned-bundle.s +++ test/MC/X86/AlignedBundling/misaligned-bundle.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - \ +# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mcpu=pentium4 %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - \ # RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-OPT %s -# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - \ # RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-RELAX %s Index: test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s =================================================================== --- test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s +++ test/MC/X86/AlignedBundling/pad-align-to-bundle-end.s @@ -1,6 +1,6 @@ -# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \ +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s -# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s # Test some variations of padding to the end of a bundle. Index: test/MC/X86/AlignedBundling/pad-bundle-groups.s =================================================================== --- test/MC/X86/AlignedBundling/pad-bundle-groups.s +++ test/MC/X86/AlignedBundling/pad-bundle-groups.s @@ -1,6 +1,6 @@ -# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \ +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s -# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s # Test some variations of padding for bundle-locked groups. Index: test/MC/X86/AlignedBundling/relax-at-bundle-end.s =================================================================== --- test/MC/X86/AlignedBundling/relax-at-bundle-end.s +++ test/MC/X86/AlignedBundling/relax-at-bundle-end.s @@ -1,6 +1,6 @@ -# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \ +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s -# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck %s # Test that an instruction near a bundle end gets properly padded Index: test/MC/X86/AlignedBundling/relax-in-bundle-group.s =================================================================== --- test/MC/X86/AlignedBundling/relax-in-bundle-group.s +++ test/MC/X86/AlignedBundling/relax-in-bundle-group.s @@ -1,6 +1,6 @@ -# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \ +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 %s -o - \ # RUN: | llvm-objdump -disassemble - | FileCheck %s -# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \ # RUN: | llvm-objdump -disassemble - | FileCheck %s # Test that instructions inside bundle-locked groups are relaxed even if their Index: test/MC/X86/AlignedBundling/single-inst-bundling.s =================================================================== --- test/MC/X86/AlignedBundling/single-inst-bundling.s +++ test/MC/X86/AlignedBundling/single-inst-bundling.s @@ -1,6 +1,6 @@ -# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - \ +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck -check-prefix=CHECK -check-prefix=CHECK-OPT %s -# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - \ +# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentium4 -mc-relax-all %s -o - \ # RUN: | llvm-objdump -disassemble -no-show-raw-insn - | FileCheck -check-prefix=CHECK -check-prefix=CHECK-RELAX %s # Test simple NOP insertion for single instructions. Index: test/MC/X86/x86_long_nop.s =================================================================== --- test/MC/X86/x86_long_nop.s +++ test/MC/X86/x86_long_nop.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s -# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s -# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-apple-darwin10.0 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s -# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-apple-darwin8 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s +# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=core2 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s +# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=atom %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s +# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-apple-darwin10.0 -mcpu=corei7 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s +# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-apple-darwin8 -mcpu=k8-sse3 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=slm %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP7 %s # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=lakemont %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP7 %s Index: test/MC/X86/x86_nop.s =================================================================== --- test/MC/X86/x86_nop.s +++ test/MC/X86/x86_nop.s @@ -15,17 +15,24 @@ # RUN: llvm-mc -filetype=obj -triple=i686-pc-linux -mcpu=c3-2 %s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -filetype=obj -triple=i686-pc-linux -mcpu=core2 %s | llvm-objdump -d - | FileCheck --check-prefix=NOPL %s # RUN: llvm-mc -filetype=obj -triple=i686-pc-linux -mcpu=slm %s | llvm-objdump -d - | FileCheck --check-prefix=NOPL %s - +# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux-gnu -mcpu=i386 %s | llvm-objdump -d - | FileCheck --check-prefix=64BIT %s inc %eax .align 8 inc %eax -// CHECK: 0: 40 incl %eax -// CHECK: 1: 8d b4 26 00 00 00 00 leal (%esi), %esi -// CHECK: 8: 40 incl %eax - +// CHECK: 0: 40 incl %eax +// CHECK: 1: 8d b4 26 00 00 00 00 leal (%esi), %esi +// CHECK: 8: 40 incl %eax // NOPL: 0: 40 incl %eax // NOPL: 1: 0f 1f 80 00 00 00 00 nopl (%eax) // NOPL: 8: 40 incl %eax + +// Make sure the max length of alternative long nops is restricted to 2 in 64 +// bit mode for CPUs which don't support true long nops. +// 64BIT: 0: ff c0 incl %eax +// 64BIT: 2: 66 90 nop +// 64BIT: 4: 66 90 nop +// 64BIT: 6: 66 90 nop +// 64BIT: 8: ff c0 incl %eax Index: tools/dsymutil/DwarfLinker.cpp =================================================================== --- tools/dsymutil/DwarfLinker.cpp +++ tools/dsymutil/DwarfLinker.cpp @@ -597,10 +597,6 @@ MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get())); MOFI->InitMCObjectFileInfo(TheTriple, /*PIC*/ false, CodeModel::Default, *MC); - MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, ""); - if (!MAB) - return error("no asm backend for target " + TripleName, Context); - MII.reset(TheTarget->createMCInstrInfo()); if (!MII) return error("no instr info info for target " + TripleName, Context); @@ -609,6 +605,10 @@ if (!MSTI) return error("no subtarget info for target " + TripleName, Context); + MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI); + if (!MAB) + return error("no asm backend for target " + TripleName, Context); + MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC); if (!MCE) return error("no code emitter for target " + TripleName, Context); Index: tools/llvm-dwp/llvm-dwp.cpp =================================================================== --- tools/llvm-dwp/llvm-dwp.cpp +++ tools/llvm-dwp/llvm-dwp.cpp @@ -643,10 +643,6 @@ MCContext MC(MAI.get(), MRI.get(), &MOFI); MOFI.InitMCObjectFileInfo(TheTriple, /*PIC*/ false, CodeModel::Default, MC); - auto MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, ""); - if (!MAB) - return error("no asm backend for target " + TripleName, Context); - std::unique_ptr MII(TheTarget->createMCInstrInfo()); if (!MII) return error("no instr info info for target " + TripleName, Context); @@ -656,6 +652,10 @@ if (!MSTI) return error("no subtarget info for target " + TripleName, Context); + auto MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI); + if (!MAB) + return error("no asm backend for target " + TripleName, Context); + MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, MC); if (!MCE) return error("no code emitter for target " + TripleName, Context); Index: tools/llvm-mc/llvm-mc.cpp =================================================================== --- tools/llvm-mc/llvm-mc.cpp +++ tools/llvm-mc/llvm-mc.cpp @@ -498,7 +498,7 @@ MCAsmBackend *MAB = nullptr; if (ShowEncoding) { CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx); - MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU); + MAB = TheTarget->createMCAsmBackend(*STI, *MRI); } auto FOut = llvm::make_unique(*OS); Str.reset(TheTarget->createAsmStreamer( @@ -519,7 +519,8 @@ } MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx); - MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU); + MCAsmBackend *MAB = + TheTarget->createMCAsmBackend(*STI, *MRI); Str.reset(TheTarget->createMCObjectStreamer( TheTriple, Ctx, *MAB, *OS, CE, *STI, MCOptions.MCRelaxAll, MCOptions.MCIncrementalLinkerCompatible,