Index: include/llvm/IR/IntrinsicsX86.td =================================================================== --- include/llvm/IR/IntrinsicsX86.td +++ include/llvm/IR/IntrinsicsX86.td @@ -2594,6 +2594,72 @@ } //===----------------------------------------------------------------------===// +// TBM + +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_tbm_bextri_u32 : GCCBuiltin<"__builtin_ia32_bextri_u32">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty, + llvm_i32_ty], [IntrNoMem]>; + def int_x86_tbm_bextri_u64 : GCCBuiltin<"__builtin_ia32_bextri_u64">, + Intrinsic<[llvm_i64_ty], [llvm_i64_ty, + llvm_i32_ty], [IntrNoMem]>; + def int_x86_tbm_blcfill_u32 : GCCBuiltin<"__builtin_ia32_blcfill_u32">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], + [IntrNoMem]>; + def int_x86_tbm_blcfill_u64 : GCCBuiltin<"__builtin_ia32_blcfill_u64">, + Intrinsic<[llvm_i64_ty], [llvm_i64_ty], + [IntrNoMem]>; + def int_x86_tbm_blci_u32 : GCCBuiltin<"__builtin_ia32_blci_u32">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], + [IntrNoMem]>; + def int_x86_tbm_blci_u64 : GCCBuiltin<"__builtin_ia32_blci_u64">, + Intrinsic<[llvm_i64_ty], [llvm_i64_ty], + [IntrNoMem]>; + def int_x86_tbm_blcic_u32 : GCCBuiltin<"__builtin_ia32_blcic_u32">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], + [IntrNoMem]>; + def int_x86_tbm_blcic_u64 : GCCBuiltin<"__builtin_ia32_blcic_u64">, + Intrinsic<[llvm_i64_ty], [llvm_i64_ty], + [IntrNoMem]>; + def int_x86_tbm_blcmsk_u32 : GCCBuiltin<"__builtin_ia32_blcmsk_u32">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], + [IntrNoMem]>; + def int_x86_tbm_blcmsk_u64 : GCCBuiltin<"__builtin_ia32_blcmsk_u64">, + Intrinsic<[llvm_i64_ty], [llvm_i64_ty], + [IntrNoMem]>; + def int_x86_tbm_blcs_u32 : GCCBuiltin<"__builtin_ia32_blcs_u32">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], + [IntrNoMem]>; + def int_x86_tbm_blcs_u64 : GCCBuiltin<"__builtin_ia32_blcs_u64">, + Intrinsic<[llvm_i64_ty], [llvm_i64_ty], + [IntrNoMem]>; + def int_x86_tbm_blsfill_u32 : GCCBuiltin<"__builtin_ia32_blsfill_u32">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], + [IntrNoMem]>; + def int_x86_tbm_blsfill_u64 : GCCBuiltin<"__builtin_ia32_blsfill_u64">, + Intrinsic<[llvm_i64_ty], [llvm_i64_ty], + [IntrNoMem]>; + def int_x86_tbm_blsic_u32 : GCCBuiltin<"__builtin_ia32_blsic_u32">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], + [IntrNoMem]>; + def int_x86_tbm_blsic_u64 : GCCBuiltin<"__builtin_ia32_blsic_u64">, + Intrinsic<[llvm_i64_ty], [llvm_i64_ty], + [IntrNoMem]>; + def int_x86_tbm_t1mskc_u32 : GCCBuiltin<"__builtin_ia32_t1mskc_u32">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], + [IntrNoMem]>; + def int_x86_tbm_t1mskc_u64 : GCCBuiltin<"__builtin_ia32_t1mskc_u64">, + Intrinsic<[llvm_i64_ty], [llvm_i64_ty], + [IntrNoMem]>; + def int_x86_tbm_tzmsk_u32 : GCCBuiltin<"__builtin_ia32_tzmsk_u32">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], + [IntrNoMem]>; + def int_x86_tbm_tzmsk_u64 : GCCBuiltin<"__builtin_ia32_tzmsk_u64">, + Intrinsic<[llvm_i64_ty], [llvm_i64_ty], + [IntrNoMem]>; +} + +//===----------------------------------------------------------------------===// // RDRAND intrinsics - Return a random value and whether it is valid. // RDSEED intrinsics - Return a NIST SP800-90B & C compliant random value and // whether it is valid. Index: lib/Target/X86/MCTargetDesc/X86BaseInfo.h =================================================================== --- lib/Target/X86/MCTargetDesc/X86BaseInfo.h +++ lib/Target/X86/MCTargetDesc/X86BaseInfo.h @@ -354,6 +354,9 @@ // XOP9 - Prefix to exclude use of imm byte. XOP9 = 21 << Op0Shift, + // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions. + XOPA = 22 << Op0Shift, + //===------------------------------------------------------------------===// // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. // They are used to specify GPRs and SSE registers, 64-bit operand size, Index: lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp =================================================================== --- lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -665,6 +665,9 @@ case X86II::XOP9: VEX_5M = 0x9; break; + case X86II::XOPA: + VEX_5M = 0xA; + break; case X86II::A6: // Bypass: Not used by VEX case X86II::A7: // Bypass: Not used by VEX case X86II::TB: // Bypass: Not used by VEX Index: lib/Target/X86/X86InstrFormats.td =================================================================== --- lib/Target/X86/X86InstrFormats.td +++ lib/Target/X86/X86InstrFormats.td @@ -139,6 +139,7 @@ class TAXD { bits<5> Prefix = 19; } class XOP8 { bits<5> Prefix = 20; } class XOP9 { bits<5> Prefix = 21; } +class XOPA { bits<5> Prefix = 22; } class VEX { bit hasVEXPrefix = 1; } class VEX_W { bit hasVEX_WPrefix = 1; } class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; } Index: lib/Target/X86/X86InstrInfo.td =================================================================== --- lib/Target/X86/X86InstrInfo.td +++ lib/Target/X86/X86InstrInfo.td @@ -664,6 +664,7 @@ def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">; def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; def HasXOP : Predicate<"Subtarget->hasXOP()">; +def HasTBM : Predicate<"Subtarget->hasTBM()">; def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; def HasF16C : Predicate<"Subtarget->hasF16C()">; @@ -1907,6 +1908,84 @@ } //===----------------------------------------------------------------------===// +// TBM Instructions +// +let isAsmParserOnly = 1, Predicates = [HasTBM], Defs = [EFLAGS] in { + +multiclass tbm_ternary_imm_intr opc, RegisterClass RC, string OpcodeStr, + X86MemOperand x86memop, PatFrag ld_frag, + Intrinsic Int> { + def rr : Ii32, + XOP, XOPA, VEX; + def mr : Ii32, + XOP, XOPA, VEX; +} + +defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32, + int_x86_tbm_bextri_u32>; +defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64, + int_x86_tbm_bextri_u64>, VEX_W; + +multiclass tbm_binary_rm opc, Format FormReg, Format FormMem, + RegisterClass RC, string OpcodeStr, + X86MemOperand x86memop, PatFrag ld_frag, + Intrinsic Int> { + def rr : I, + XOP, XOP9, VEX_4V; + def rm : I, + XOP, XOP9, VEX_4V; +} + +multiclass tbm_binary_intr opc, string OpcodeStr, + Format FormReg, Format FormMem, + Intrinsic Int32, Intrinsic Int64> { + defm _32 : tbm_binary_rm; + defm _64 : tbm_binary_rm, VEX_W; +} + +defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m, + int_x86_tbm_blcfill_u32, + int_x86_tbm_blcfill_u64>; +defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m, + int_x86_tbm_blci_u32, + int_x86_tbm_blci_u64>; +defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m, + int_x86_tbm_blcic_u32, + int_x86_tbm_blcic_u64>; +defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m, + int_x86_tbm_blcmsk_u32, + int_x86_tbm_blcmsk_u64>; +defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m, + int_x86_tbm_blcs_u32, + int_x86_tbm_blcs_u64>; +defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m, + int_x86_tbm_blsfill_u32, + int_x86_tbm_blsfill_u64>; +defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m, + int_x86_tbm_blsic_u32, + int_x86_tbm_blsic_u64>; +defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m, + int_x86_tbm_t1mskc_u32, + int_x86_tbm_t1mskc_u64>; +defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m, + int_x86_tbm_tzmsk_u32, + int_x86_tbm_tzmsk_u64>; +} // isAsmParserOnly, HasTBM, EFLAGS + +//===----------------------------------------------------------------------===// // Subsystems. //===----------------------------------------------------------------------===// Index: test/CodeGen/X86/tbm-intrinsics-x86_64.ll =================================================================== --- test/CodeGen/X86/tbm-intrinsics-x86_64.ll +++ test/CodeGen/X86/tbm-intrinsics-x86_64.ll @@ -0,0 +1,422 @@ +; RUN: llc -mtriple=x86_64-unknown-unknown -march=x86-64 -mattr=+tbm < %s | FileCheck %s + +define i32 @test_x86_tbm_bextri_u32(i32 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_bextri_u32: + ; CHECK-NOT: mov + ; CHECK: bextr $ + %0 = tail call i32 @llvm.x86.tbm.bextri.u32(i32 %a, i32 2814) + ret i32 %0 +} + +declare i32 @llvm.x86.tbm.bextri.u32(i32, i32) nounwind readnone + +define i32 @test_x86_tbm_bextri_u32_m(i32* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_bextri_u32_m: + ; CHECK-NOT: mov + ; CHECK: bextr $ + %tmp1 = load i32* %a, align 4 + %0 = tail call i32 @llvm.x86.tbm.bextri.u32(i32 %tmp1, i32 2814) + ret i32 %0 +} + +define i64 @test_x86_tbm_bextri_u64(i64 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_bextri_u64: + ; CHECK-NOT: mov + ; CHECK: bextr $ + %0 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %a, i32 2814) + ret i64 %0 +} + +declare i64 @llvm.x86.tbm.bextri.u64(i64, i32) nounwind readnone + +define i64 @test_x86_tbm_bextri_u64_m(i64* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEl: test_x86_tbm_bextri_u64_m: + ; CHECK-NOT: mov + ; CHECK: bextr $ + %tmp1 = load i64* %a, align 8 + %0 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %tmp1, i32 2814) + ret i64 %0 +} + +define i32 @test_x86_tbm_blcfill_u32(i32 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_blcfill_u32: + ; CHECK-NOT: mov + ; CHECK: blcfill % + %0 = tail call i32 @llvm.x86.tbm.blcfill.u32(i32 %a) + ret i32 %0 +} + +declare i32 @llvm.x86.tbm.blcfill.u32(i32) nounwind readnone + +define i32 @test_x86_tbm_blcfill_u32_m(i32* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_blcfill_u32_m: + ; CHECK-NOT: mov + ; CHECK: blcfill (% + %tmp1 = load i32* %a, align 4 + %0 = tail call i32 @llvm.x86.tbm.blcfill.u32(i32 %tmp1) + ret i32 %0 +} + +define i64 @test_x86_tbm_blcfill_u64(i64 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_blcfill_u64: + ; CHECK-NOT: mov + ; CHECK: blcfill % + %0 = tail call i64 @llvm.x86.tbm.blcfill.u64(i64 %a) + ret i64 %0 +} + +declare i64 @llvm.x86.tbm.blcfill.u64(i64) nounwind readnone + +define i64 @test_x86_tbm_blcfill_u64_m(i64* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_blcfill_u64_m: + ; CHECK-NOT: mov + ; CHECK: blcfill (% + %tmp1 = load i64* %a, align 8 + %0 = tail call i64 @llvm.x86.tbm.blcfill.u64(i64 %tmp1) + ret i64 %0 +} + +define i32 @test_x86_tbm_blci_u32(i32 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_blci_u32: + ; CHECK-NOT: mov + ; CHECK: blci % + %0 = tail call i32 @llvm.x86.tbm.blci.u32(i32 %a) + ret i32 %0 +} + +declare i32 @llvm.x86.tbm.blci.u32(i32) nounwind readnone + +define i32 @test_x86_tbm_blci_u32_m(i32* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_blci_u32_m: + ; CHECK-NOT: mov + ; CHECK: blci (% + %tmp1 = load i32* %a, align 4 + %0 = tail call i32 @llvm.x86.tbm.blci.u32(i32 %tmp1) + ret i32 %0 +} + +define i64 @test_x86_tbm_blci_u64(i64 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_blci_u64: + ; CHECK-NOT: mov + ; CHECK: blci % + %0 = tail call i64 @llvm.x86.tbm.blci.u64(i64 %a) + ret i64 %0 +} + +declare i64 @llvm.x86.tbm.blci.u64(i64) nounwind readnone + +define i64 @test_x86_tbm_blci_u64_m(i64* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEl: test_x86_tbm_blci_u64_m: + ; CHECK-NOT: mov + ; CHECK: blci (% + %tmp1 = load i64* %a, align 8 + %0 = tail call i64 @llvm.x86.tbm.blci.u64(i64 %tmp1) + ret i64 %0 +} + +define i32 @test_x86_tbm_blcic_u32(i32 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_blcic_u32: + ; CHECK-NOT: mov + ; CHECK: blcic % + %0 = tail call i32 @llvm.x86.tbm.blcic.u32(i32 %a) + ret i32 %0 +} + +declare i32 @llvm.x86.tbm.blcic.u32(i32) nounwind readnone + +define i32 @test_x86_tbm_blcic_u32_m(i32* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_blcic_u32_m: + ; CHECK-NOT: mov + ; CHECK: blcic (% + %tmp1 = load i32* %a, align 4 + %0 = tail call i32 @llvm.x86.tbm.blcic.u32(i32 %tmp1) + ret i32 %0 +} + +define i64 @test_x86_tbm_blcic_u64(i64 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_blcic_u64: + ; CHECK-NOT: mov + ; CHECK: blcic % + %0 = tail call i64 @llvm.x86.tbm.blcic.u64(i64 %a) + ret i64 %0 +} + +declare i64 @llvm.x86.tbm.blcic.u64(i64) nounwind readnone + +define i64 @test_x86_tbm_blcic_u64_m(i64* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_blcic_u64_m: + ; CHECK-NOT: mov + ; CHECK: blcic (% + %tmp1 = load i64* %a, align 8 + %0 = tail call i64 @llvm.x86.tbm.blcic.u64(i64 %tmp1) + ret i64 %0 +} + +define i32 @test_x86_tbm_blcmsk_u32(i32 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_blcmsk_u32: + ; CHECK-NOT: mov + ; CHECK: blcmsk % + %0 = tail call i32 @llvm.x86.tbm.blcmsk.u32(i32 %a) + ret i32 %0 +} + +declare i32 @llvm.x86.tbm.blcmsk.u32(i32) nounwind readnone + +define i32 @test_x86_tbm_blcmsk_u32_m(i32* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_blcmsk_u32_m: + ; CHECK-NOT: mov + ; CHECK: blcmsk (% + %tmp1 = load i32* %a, align 4 + %0 = tail call i32 @llvm.x86.tbm.blcmsk.u32(i32 %tmp1) + ret i32 %0 +} + +define i64 @test_x86_tbm_blcmsk_u64(i64 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_blcmsk_u64: + ; CHECK-NOT: mov + ; CHECK: blcmsk % + %0 = tail call i64 @llvm.x86.tbm.blcmsk.u64(i64 %a) + ret i64 %0 +} + +declare i64 @llvm.x86.tbm.blcmsk.u64(i64) nounwind readnone + +define i64 @test_x86_tbm_blcmsk_u64_m(i64* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_blcmsk_u64_m: + ; CHECK-NOT: mov + ; CHECK: blcmsk (% + %tmp1 = load i64* %a, align 8 + %0 = tail call i64 @llvm.x86.tbm.blcmsk.u64(i64 %tmp1) + ret i64 %0 +} + +define i32 @test_x86_tbm_blcs_u32(i32 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_blcs_u32: + ; CHECK-NOT: mov + ; CHECK: blcs % + %0 = tail call i32 @llvm.x86.tbm.blcs.u32(i32 %a) + ret i32 %0 +} + +declare i32 @llvm.x86.tbm.blcs.u32(i32) nounwind readnone + +define i32 @test_x86_tbm_blcs_u32_m(i32* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_blcs_u32_m: + ; CHECK-NOT: mov + ; CHECK: blcs (% + %tmp1 = load i32* %a, align 4 + %0 = tail call i32 @llvm.x86.tbm.blcs.u32(i32 %tmp1) + ret i32 %0 +} + +define i64 @test_x86_tbm_blcs_u64(i64 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_blcs_u64: + ; CHECK-NOT: mov + ; CHECK: blcs % + %0 = tail call i64 @llvm.x86.tbm.blcs.u64(i64 %a) + ret i64 %0 +} + +declare i64 @llvm.x86.tbm.blcs.u64(i64) nounwind readnone + +define i64 @test_x86_tbm_blcs_u64_m(i64* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_blcs_u64_m: + ; CHECK-NOT: mov + ; CHECK: blcs (% + %tmp1 = load i64* %a, align 8 + %0 = tail call i64 @llvm.x86.tbm.blcs.u64(i64 %tmp1) + ret i64 %0 +} + +define i32 @test_x86_tbm_blsfill_u32(i32 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_blsfill_u32: + ; CHECK-NOT: mov + ; CHECK: blsfill % + %0 = tail call i32 @llvm.x86.tbm.blsfill.u32(i32 %a) + ret i32 %0 +} + +declare i32 @llvm.x86.tbm.blsfill.u32(i32) nounwind readnone + +define i32 @test_x86_tbm_blsfill_u32_m(i32* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_blsfill_u32_m: + ; CHECK-NOT: mov + ; CHECK: blsfill (% + %tmp1 = load i32* %a, align 4 + %0 = tail call i32 @llvm.x86.tbm.blsfill.u32(i32 %tmp1) + ret i32 %0 +} + +define i64 @test_x86_tbm_blsfill_u64(i64 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_blsfill_u64: + ; CHECK-NOT: mov + ; CHECK: blsfill % + %0 = tail call i64 @llvm.x86.tbm.blsfill.u64(i64 %a) + ret i64 %0 +} + +declare i64 @llvm.x86.tbm.blsfill.u64(i64) nounwind readnone + +define i64 @test_x86_tbm_blsfill_u64_m(i64* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_blsfill_u64_m: + ; CHECK-NOT: mov + ; CHECK: blsfill (% + %tmp1 = load i64* %a, align 8 + %0 = tail call i64 @llvm.x86.tbm.blsfill.u64(i64 %tmp1) + ret i64 %0 +} + +define i32 @test_x86_tbm_blsic_u32(i32 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_blsic_u32: + ; CHECK-NOT: mov + ; CHECK: blsic % + %0 = tail call i32 @llvm.x86.tbm.blsic.u32(i32 %a) + ret i32 %0 +} + +declare i32 @llvm.x86.tbm.blsic.u32(i32) nounwind readnone + +define i32 @test_x86_tbm_blsic_u32_m(i32* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_blsic_u32_m: + ; CHECK-NOT: mov + ; CHECK: blsic (% + %tmp1 = load i32* %a, align 4 + %0 = tail call i32 @llvm.x86.tbm.blsic.u32(i32 %tmp1) + ret i32 %0 +} + +define i64 @test_x86_tbm_blsic_u64(i64 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_blsic_u64: + ; CHECK-NOT: mov + ; CHECK: blsic % + %0 = tail call i64 @llvm.x86.tbm.blsic.u64(i64 %a) + ret i64 %0 +} + +declare i64 @llvm.x86.tbm.blsic.u64(i64) nounwind readnone + +define i64 @test_x86_tbm_blsic_u64_m(i64* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_blsic_u64_m: + ; CHECK-NOT: mov + ; CHECK: blsic (% + %tmp1 = load i64* %a, align 8 + %0 = tail call i64 @llvm.x86.tbm.blsic.u64(i64 %tmp1) + ret i64 %0 +} + +define i32 @test_x86_tbm_t1mskc_u32(i32 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_t1mskc_u32: + ; CHECK-NOT: mov + ; CHECK: t1mskc % + %0 = tail call i32 @llvm.x86.tbm.t1mskc.u32(i32 %a) + ret i32 %0 +} + +declare i32 @llvm.x86.tbm.t1mskc.u32(i32) nounwind readnone + +define i32 @test_x86_tbm_t1mskc_u32_m(i32* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_t1mskc_u32_m: + ; CHECK-NOT: mov + ; CHECK: t1mskc (% + %tmp1 = load i32* %a, align 4 + %0 = tail call i32 @llvm.x86.tbm.t1mskc.u32(i32 %tmp1) + ret i32 %0 +} + +define i64 @test_x86_tbm_t1mskc_u64(i64 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_t1mskc_u64: + ; CHECK-NOT: mov + ; CHECK: t1mskc % + %0 = tail call i64 @llvm.x86.tbm.t1mskc.u64(i64 %a) + ret i64 %0 +} + +declare i64 @llvm.x86.tbm.t1mskc.u64(i64) nounwind readnone + +define i64 @test_x86_tbm_t1mskc_u64_m(i64* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_t1mskc_u64_m: + ; CHECK-NOT: mov + ; CHECK: t1mskc (% + %tmp1 = load i64* %a, align 8 + %0 = tail call i64 @llvm.x86.tbm.t1mskc.u64(i64 %tmp1) + ret i64 %0 +} + +define i32 @test_x86_tbm_tzmsk_u32(i32 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_tzmsk_u32: + ; CHECK-NOT: mov + ; CHECK: tzmsk % + %0 = tail call i32 @llvm.x86.tbm.tzmsk.u32(i32 %a) + ret i32 %0 +} + +declare i32 @llvm.x86.tbm.tzmsk.u32(i32) nounwind readnone + +define i32 @test_x86_tbm_tzmsk_u32_m(i32* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEL: test_x86_tbm_tzmsk_u32_m: + ; CHECK-NOT: mov + ; CHECK: tzmsk (% + %tmp1 = load i32* %a, align 4 + %0 = tail call i32 @llvm.x86.tbm.tzmsk.u32(i32 %tmp1) + ret i32 %0 +} + +define i64 @test_x86_tbm_tzmsk_u64(i64 %a) nounwind readnone { +entry: + ; CHECK-LABEL: test_x86_tbm_tzmsk_u64: + ; CHECK-NOT: mov + ; CHECK: tzmsk % + %0 = tail call i64 @llvm.x86.tbm.tzmsk.u64(i64 %a) + ret i64 %0 +} + +declare i64 @llvm.x86.tbm.tzmsk.u64(i64) nounwind readnone + +define i64 @test_x86_tbm_tzmsk_u64_m(i64* nocapture %a) nounwind readonly { +entry: + ; CHECK-LABEl: test_x86_tbm_tzmsk_u64_m: + ; CHECK-NOT: mov + ; CHECK: tzmsk (% + %tmp1 = load i64* %a, align 8 + %0 = tail call i64 @llvm.x86.tbm.tzmsk.u64(i64 %tmp1) + ret i64 %0 +} + Index: test/MC/X86/x86_64-tbm-encoding.s =================================================================== --- test/MC/X86/x86_64-tbm-encoding.s +++ test/MC/X86/x86_64-tbm-encoding.s @@ -0,0 +1,196 @@ +// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s + +// bextri 32 reg +// CHECK: bextr $2814, %edi, %eax +// CHECK: encoding: [0x8f,0xea,0x78,0x10,0xc7,0xfe,0x0a,0x00,0x00] + bextr $2814, %edi, %eax + +// bextri 32 mem +// CHECK: bextr $2814, (%rdi), %eax +// CHECK: encoding: [0x8f,0xea,0x78,0x10,0x07,0xfe,0x0a,0x00,0x00] + bextr $2814, (%rdi), %eax + +// bextri 64 reg +// CHECK: bextr $2814, %rdi, %rax +// CHECK: encoding: [0x8f,0xea,0xf8,0x10,0xc7,0xfe,0x0a,0x00,0x00] + bextr $2814, %rdi, %rax + +// bextri 64 mem +// CHECK: bextr $2814, (%rdi), %rax +// CHECK: encoding: [0x8f,0xea,0xf8,0x10,0x07,0xfe,0x0a,0x00,0x00] + bextr $2814, (%rdi), %rax + +// blcfill 32 reg +// CHECK: blcfill %edi, %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0xcf] + blcfill %edi, %eax + +// blcfill 32 mem +// CHECK: blcfill (%rdi), %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0x0f] + blcfill (%rdi), %eax + +// blcfill 64 reg +// CHECK: blcfill %rdi, %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0xcf] + blcfill %rdi, %rax + +// blcfill 64 mem +// CHECK: blcfill (%rdi), %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0x0f] + blcfill (%rdi), %rax + +// blci 32 reg +// CHECK: blci %edi, %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x02,0xf7] + blci %edi, %eax + +// blci 32 mem +// CHECK: blci (%rdi), %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x02,0x37] + blci (%rdi), %eax + +// blci 64 reg +// CHECK: blci %rdi, %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x02,0xf7] + blci %rdi, %rax + +// blci 64 mem +// CHECK: blci (%rdi), %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x02,0x37] + blci (%rdi), %rax + +// blcic 32 reg +// CHECK: blcic %edi, %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0xef] + blcic %edi, %eax + +// blcic 32 mem +// CHECK: blcic (%rdi), %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0x2f] + blcic (%rdi), %eax + +// blcic 64 reg +// CHECK: blcic %rdi, %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0xef] + blcic %rdi, %rax + +// blcic 64 mem +// CHECK: blcic (%rdi), %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0x2f] + blcic (%rdi), %rax + +// blcmsk 32 reg +// CHECK: blcmsk %edi, %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x02,0xcf] + blcmsk %edi, %eax + +// blcmsk 32 mem +// CHECK: blcmsk (%rdi), %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x02,0x0f] + blcmsk (%rdi), %eax + +// blcmsk 64 reg +// CHECK: blcmsk %rdi, %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x02,0xcf] + blcmsk %rdi, %rax + +// blcmsk 64 mem +// CHECK: blcmsk (%rdi), %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x02,0x0f] + blcmsk (%rdi), %rax + +// blcs 32 reg +// CHECK: blcs %edi, %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0xdf] + blcs %edi, %eax + +// blcs 32 mem +// CHECK: blcs (%rdi), %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0x1f] + blcs (%rdi), %eax + +// blcs 64 reg +// CHECK: blcs %rdi, %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0xdf] + blcs %rdi, %rax + +// blcs 64 mem +// CHECK: blcs (%rdi), %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0x1f] + blcs (%rdi), %rax + +// blsfill 32 reg +// CHECK: blsfill %edi, %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0xd7] + blsfill %edi, %eax + +// blsfill 32 mem +// CHECK: blsfill (%rdi), %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0x17] + blsfill (%rdi), %eax + +// blsfill 64 reg +// CHECK: blsfill %rdi, %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0xd7] + blsfill %rdi, %rax + +// blsfill 64 mem +// CHECK: blsfill (%rdi), %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0x17] + blsfill (%rdi), %rax + +// blsic 32 reg +// CHECK: blsic %edi, %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0xf7] + blsic %edi, %eax + +// blsic 32 mem +// CHECK: blsic (%rdi), %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0x37] + blsic (%rdi), %eax + +// blsic 64 reg +// CHECK: blsic %rdi, %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0xf7] + blsic %rdi, %rax + +// t1mskc 32 reg +// CHECK: t1mskc %edi, %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0xff] + t1mskc %edi, %eax + +// t1mskc 32 mem +// CHECK: t1mskc (%rdi), %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0x3f] + t1mskc (%rdi), %eax + +// t1mskc 64 reg +// CHECK: t1mskc %rdi, %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0xff] + t1mskc %rdi, %rax + +// t1mskc 64 mem +// CHECK: t1mskc (%rdi), %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0x3f] + t1mskc (%rdi), %rax + +// tzmsk 32 reg +// CHECK: tzmsk %edi, %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0xe7] + tzmsk %edi, %eax + +// tzmsk 32 mem +// CHECK: tzmsk (%rdi), %eax +// CHECK: encoding: [0x8f,0xe9,0x78,0x01,0x27] + tzmsk (%rdi), %eax + +// tzmsk 64 reg +// CHECK: tzmsk %rdi, %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0xe7] + tzmsk %rdi, %rax + +// tzmsk 64 mem +// CHECK: tzmsk (%rdi), %rax +// CHECK: encoding: [0x8f,0xe9,0xf8,0x01,0x27] + tzmsk (%rdi), %rax