Index: lib/Target/Mips/MicroMips32r6InstrFormats.td
===================================================================
--- lib/Target/Mips/MicroMips32r6InstrFormats.td
+++ lib/Target/Mips/MicroMips32r6InstrFormats.td
@@ -860,3 +860,49 @@
   let Inst{10-9}  = fmt;
   let Inst{8-0}   = funct;
 }
+
+class POOL32A_MFTC0_FM_MMR6<string instr_asm, bits<5> funct, bits<6> opcode>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
+  bits<5> rt;
+  bits<5> rs;
+  bits<3> sel;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b000000;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-14} = 0;
+  let Inst{13-11} = sel;
+  let Inst{10-6}  = funct;
+  let Inst{5-0}   = opcode;
+}
+
+class POOL32F_MFTC1_FM_MMR6<string instr_asm, bits<8> funct>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
+  bits<5> rt;
+  bits<5> fs;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010101;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = fs;
+  let Inst{15-14} = 0;
+  let Inst{13-6}  = funct;
+  let Inst{5-0}   = 0b111011;
+}
+
+class POOL32A_MFTC2_FM_MMR6<string instr_asm, bits<10> funct>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
+  bits<5> rt;
+  bits<5> impl;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b000000;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = impl;
+  let Inst{15-6}  = funct;
+  let Inst{5-0}   = 0b111100;
+}
Index: lib/Target/Mips/MicroMips32r6InstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -65,6 +65,12 @@
 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
 class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
+class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>;
+class MFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfc1", 0b10000000>;
+class MFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfc2", 0b0100110100>;
+class MFHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfhc0", 0b00011, 0b110100>;
+class MFHC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfhc1", 0b11000000>;
+class MFHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfhc2", 0b1000110100>;
 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
@@ -536,6 +542,45 @@
 class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>;
 class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>;
 
+class MFC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
+                          RegisterOperand SrcRC> {
+  dag InOperandList = (ins SrcRC:$rs, uimm3:$sel);
+  dag OutOperandList = (outs DstRC:$rt);
+  string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
+  list<dag> Pattern = [];
+  Format f = FrmFR;
+  string BaseOpcode = opstr;
+}
+class MFC1_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
+                          RegisterOperand SrcRC,
+                          InstrItinClass Itin = NoItinerary,
+                          SDPatternOperator OpNode = null_frag> {
+  dag InOperandList = (ins SrcRC:$fs);
+  dag OutOperandList = (outs DstRC:$rt);
+  string AsmString = !strconcat(opstr, "\t$rt, $fs");
+  list<dag> Pattern = [(set DstRC:$rt, (OpNode SrcRC:$fs))];
+  Format f = FrmFR;
+  InstrItinClass Itinerary = Itin;
+  string BaseOpcode = opstr;
+}
+class MFC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
+                          RegisterOperand SrcRC> {
+  dag InOperandList = (ins SrcRC:$impl);
+  dag OutOperandList = (outs DstRC:$rt);
+  string AsmString = !strconcat(opstr, "\t$rt, $impl");
+  list<dag> Pattern = [];
+  Format f = FrmFR;
+  string BaseOpcode = opstr;
+}
+class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd>;
+class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd,
+                                           II_MFC1, bitconvert>, HARDFLOAT;
+class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd>;
+class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd>;
+class MFHC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, AFGR64Opnd,
+                                            II_MFHC1>, HARDFLOAT;
+class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd>;
+
 /// Floating Point Instructions
 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
                             InstrItinClass Itin, bit isComm,
@@ -987,6 +1032,12 @@
 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
 def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
+def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6;
+def MFC1_MMR6 : StdMMR6Rel, MFC1_MMR6_ENC, MFC1_MMR6_DESC, ISA_MICROMIPS32R6;
+def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_ENC, MFC2_MMR6_DESC, ISA_MICROMIPS32R6;
+def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6;
+def MFHC1_MMR6 : StdMMR6Rel, MFHC1_MMR6_ENC, MFHC1_MMR6_DESC, ISA_MICROMIPS32R6;
+def MFHC2_MMR6 : StdMMR6Rel, MFHC2_MMR6_ENC, MFHC2_MMR6_DESC, ISA_MICROMIPS32R6;
 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
@@ -1222,6 +1273,12 @@
 def : MipsInstAlias<"rdhwr $rt, $rs",
                     (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
                     ISA_MICROMIPS32R6;
+def : MipsInstAlias<"mfc0 $rt, $rs",
+                    (MFC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
+                    ISA_MICROMIPS32R6;
+def : MipsInstAlias<"mfhc0 $rt, $rs",
+                    (MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
+                    ISA_MICROMIPS32R6;
 
 //===----------------------------------------------------------------------===//
 //
Index: lib/Target/Mips/MicroMips64r6InstrFormats.td
===================================================================
--- lib/Target/Mips/MicroMips64r6InstrFormats.td
+++ lib/Target/Mips/MicroMips64r6InstrFormats.td
@@ -84,3 +84,20 @@
   let Inst{10-9}  = 0b00;
   let Inst{8-0}  = funct;
 }
+
+class POOL32S_DMFTC0_FM_MMR6<string instr_asm, bits<5> funct>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
+  bits<5> rt;
+  bits<5> rs;
+  bits<3> sel;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010110;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-14} = 0;
+  let Inst{13-11} = sel;
+  let Inst{10-6}  = funct;
+  let Inst{5-0}   = 0b111100;
+}
Index: lib/Target/Mips/MicroMips64r6InstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMips64r6InstrInfo.td
+++ lib/Target/Mips/MicroMips64r6InstrInfo.td
@@ -28,6 +28,9 @@
 class DMOD_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmod", 0b101011000>;
 class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>;
 class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>;
+class DMFC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmfc0", 0b00011>;
+class DMFC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmfc1", 0b10010000>;
+class DMFC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmfc2", 0b0110110100>;
 
 //===----------------------------------------------------------------------===//
 //
@@ -90,6 +93,11 @@
 class DDIVU_MM64R6_DESC : ArithLogicR<"ddivu", GPR32Opnd>;
 class DMODU_MM64R6_DESC : ArithLogicR<"dmodu", GPR32Opnd>;
 
+class DMFC0_MM64R6_DESC : MFC0_MMR6_DESC_BASE<"dmfc0", GPR64Opnd, COP0Opnd>;
+class DMFC1_MM64R6_DESC : MFC1_MMR6_DESC_BASE<"dmfc1", GPR64Opnd, FGR64Opnd,
+                                              II_DMFC1, bitconvert>;
+class DMFC2_MM64R6_DESC : MFC2_MMR6_DESC_BASE<"dmfc2", GPR64Opnd, COP2Opnd>;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
@@ -116,4 +124,17 @@
                      ISA_MICROMIPS64R6;
   def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC,
                      ISA_MICROMIPS64R6;
+  def DMFC0_MM64R6 : StdMMR6Rel, DMFC0_MM64R6_ENC, DMFC0_MM64R6_DESC,
+                     ISA_MICROMIPS64R6;
+  def DMFC1_MM64R6 : StdMMR6Rel, DMFC1_MM64R6_ENC, DMFC1_MM64R6_DESC,
+                     ISA_MICROMIPS64R6;
+  def DMFC2_MM64R6 : StdMMR6Rel, DMFC2_MM64R6_ENC, DMFC2_MM64R6_DESC,
+                     ISA_MICROMIPS64R6;
 }
+
+//===----------------------------------------------------------------------===//
+// Instruction aliases
+//===----------------------------------------------------------------------===//
+def : MipsInstAlias<"dmfc0 $rt, $rd",
+                    (DMFC0_MM64R6 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>,
+                    ISA_MICROMIPS64R6;
Index: lib/Target/Mips/Mips64InstrInfo.td
===================================================================
--- lib/Target/Mips/Mips64InstrInfo.td
+++ lib/Target/Mips/Mips64InstrInfo.td
@@ -622,7 +622,10 @@
                     ISA_MIPS3;
 
 // Two operand (implicit 0 selector) versions:
-def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>;
+let AdditionalPredicates = [NotInMicroMips] in {
+  def : MipsInstAlias<"dmfc0 $rt, $rd",
+                      (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>;
+}
 def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
 def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>;
 def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
Index: lib/Target/Mips/MipsInstrFPU.td
===================================================================
--- lib/Target/Mips/MipsInstrFPU.td
+++ lib/Target/Mips/MipsInstrFPU.td
@@ -379,8 +379,10 @@
                 MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
   let DecoderNamespace = "Mips64";
 }
-def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
-            bitconvert>, MFC1_FM<1>, ISA_MIPS3;
+let AdditionalPredicates = [NotInMicroMips] in {
+  def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
+                      bitconvert>, MFC1_FM<1>, ISA_MIPS3;
+}
 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
             bitconvert>, MFC1_FM<5>, ISA_MIPS3;
 
Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -1287,7 +1287,7 @@
 }
 
 class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
-  InstSE<(outs RO:$rt), (ins RD:$rd, uimm16:$sel),
+  InstSE<(outs RO:$rt), (ins RD:$rd, uimm3:$sel),
          !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
 
 class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
@@ -1741,7 +1741,10 @@
 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
 
 /// Move Control Registers From/To CPU Registers
-def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
+let AdditionalPredicates = [NotInMicroMips] in {
+  def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>,
+             ISA_MIPS32;
+}
 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
 def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
 def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
Index: test/MC/Disassembler/Mips/micromips32r6/valid.txt
===================================================================
--- test/MC/Disassembler/Mips/micromips32r6/valid.txt
+++ test/MC/Disassembler/Mips/micromips32r6/valid.txt
@@ -256,3 +256,11 @@
 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
 0x00 0x00 0x47 0x7c # CHECK: di
 0x00 0x0f 0x47 0x7c # CHECK: di $15
+0x00 0x67 0x00 0xfc # CHECK: mfc0 $3, $7, 0
+0x00 0x67 0x18 0xfc # CHECK: mfc0 $3, $7, 3
+0x54 0xaa 0x20 0x3b # CHECK: mfc1 $5, $f10
+0x01 0xe5 0x4d 0x3c # CHECK: mfc2 $15, $5
+0x02 0x95 0x00 0xf4 # CHECK: mfhc0 $20, $21, 0
+0x00 0x22 0x08 0xf4 # CHECK: mfhc0 $1, $2, 1
+0x54 0x06 0x30 0x3b # CHECK: mfhc1 $zero, $f6
+0x02 0xf0 0x8d 0x3c # CHECK: mfhc2 $23, $16
Index: test/MC/Disassembler/Mips/micromips64r6/valid.txt
===================================================================
--- test/MC/Disassembler/Mips/micromips64r6/valid.txt
+++ test/MC/Disassembler/Mips/micromips64r6/valid.txt
@@ -169,3 +169,7 @@
 0x00 0x00 0xe3 0x7c # CHECK: deret
 0x00 0x00 0x47 0x7c # CHECK: di
 0x00 0x0f 0x47 0x7c # CHECK: di $15
+0x5a 0x51 0x00 0xfc # CHECK: dmfc0 $18, $17
+0x59 0x21 0x08 0xfc # CHECK: dmfc0 $9, $1, 1
+0x55 0x24 0x24 0x3b # CHECK: dmfc1 $9, $f4
+0x01 0xd2 0x6d 0x3c # CHECK: dmfc2 $14, $18
Index: test/MC/Mips/micromips32r6/invalid.s
===================================================================
--- test/MC/Mips/micromips32r6/invalid.s
+++ test/MC/Mips/micromips32r6/invalid.s
@@ -107,3 +107,7 @@
   swm16 $16-$20, 8($sp)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 8($fp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  mfc0  $4, $3, -1         # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
+  mfc0  $4, $3, 8          # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
+  mfhc0 $4, $3, -1         # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
+  mfhc0 $4, $3, 8          # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
Index: test/MC/Mips/micromips32r6/valid.s
===================================================================
--- test/MC/Mips/micromips32r6/valid.s
+++ test/MC/Mips/micromips32r6/valid.s
@@ -250,3 +250,11 @@
   class.s $f2, $f3         # CHECK: class.s $f2, $f3       # encoding: [0x54,0x62,0x00,0x60]
   class.d $f2, $f4         # CHECK: class.d $f2, $f4       # encoding: [0x54,0x82,0x02,0x60]
   deret                    # CHECK: deret                  # encoding: [0x00,0x00,0xe3,0x7c]
+  mfc0 $3, $7              # CHECK: mfc0 $3, $7, 0      # encoding: [0x00,0x67,0x00,0xfc]
+  mfc0 $3, $7, 3           # CHECK: mfc0 $3, $7, 3      # encoding: [0x00,0x67,0x18,0xfc]
+  mfc1 $5, $f10            # CHECK: mfc1 $5, $f10       # encoding: [0x54,0xaa,0x20,0x3b]
+  mfc2 $15, $5             # CHECK: mfc2 $15, $5        # encoding: [0x01,0xe5,0x4d,0x3c]
+  mfhc0 $20, $21           # CHECK: mfhc0 $20, $21, 0   # encoding: [0x02,0x95,0x00,0xf4]
+  mfhc0 $1, $2, 1          # CHECK: mfhc0 $1, $2, 1     # encoding: [0x00,0x22,0x08,0xf4]
+  mfhc1 $zero, $f6         # CHECK: mfhc1 $zero, $f6    # encoding: [0x54,0x06,0x30,0x3b]
+  mfhc2 $23, $16           # CHECK: mfhc2 $23, $16      # encoding: [0x02,0xf0,0x8d,0x3c]
Index: test/MC/Mips/micromips64r6/invalid.s
===================================================================
--- test/MC/Mips/micromips64r6/invalid.s
+++ test/MC/Mips/micromips64r6/invalid.s
@@ -131,3 +131,5 @@
   swm16 $16-$20, 8($sp)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 8($fp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  dmfc0  $4, $3, -1        # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
+  dmfc0  $4, $3, 8         # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
Index: test/MC/Mips/micromips64r6/valid.s
===================================================================
--- test/MC/Mips/micromips64r6/valid.s
+++ test/MC/Mips/micromips64r6/valid.s
@@ -154,5 +154,9 @@
         ceil.l.d $f1, $f3        # CHECK: ceil.l.d $f1, $f3       # encoding: [0x54,0x23,0x53,0x3b]
         floor.l.s $f1, $f3       # CHECK: floor.l.s $f1, $f3      # encoding: [0x54,0x23,0x03,0x3b]
         floor.l.d $f1, $f3       # CHECK: floor.l.d $f1, $f3      # encoding: [0x54,0x23,0x43,0x3b]
+        dmfc0 $18, $17           # CHECK: dmfc0 $18, $17, 0       # encoding: [0x5a,0x51,0x00,0xfc]
+        dmfc0 $9, $1, 1          # CHECK: dmfc0 $9, $1, 1         # encoding: [0x59,0x21,0x08,0xfc]
+        dmfc1 $9, $f4            # CHECK: dmfc1 $9, $f4           # encoding: [0x55,0x24,0x24,0x3b]
+        dmfc2 $14, $18           # CHECK: dmfc2 $14, $18          # encoding: [0x01,0xd2,0x6d,0x3c]
 
 1:
Index: test/MC/Mips/mips32r5/invalid.s
===================================================================
--- test/MC/Mips/mips32r5/invalid.s
+++ test/MC/Mips/mips32r5/invalid.s
@@ -12,3 +12,9 @@
         jalr.hb $31, $31     # CHECK: :[[@LINE]]:9: error: source and destination must be different
         pref -1, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         pref 32, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
+        mfc0  $4, $3, -1     # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
+        mfc0  $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
+        mfhc0 $4, $3, -1     # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
+        mfhc0 $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
+        mfc2  $4, $3, -1     # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
+        mfc2  $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
Index: test/MC/Mips/mips32r6/invalid.s
===================================================================
--- test/MC/Mips/mips32r6/invalid.s
+++ test/MC/Mips/mips32r6/invalid.s
@@ -39,3 +39,9 @@
         lsa $2, $3, $4, 5    # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
         pref -1, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         pref 32, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
+        mfc0  $4, $3, -1     # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
+        mfc0  $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
+        mfhc0 $4, $3, -1     # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
+        mfhc0 $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
+        mfc2  $4, $3, -1     # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
+        mfc2  $4, $3, 8      # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
Index: test/MC/Mips/mips64r5/invalid.s
===================================================================
--- test/MC/Mips/mips64r5/invalid.s
+++ test/MC/Mips/mips64r5/invalid.s
@@ -14,3 +14,7 @@
         jalr.hb $31, $31     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
         pref -1, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         pref 32, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
+        dmfc0  $4, $3, -1    # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
+        dmfc0  $4, $3, 8     # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
+        dmfc2  $4, $3, -1    # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
+        dmfc2  $4, $3, 8     # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
Index: test/MC/Mips/mips64r6/invalid.s
===================================================================
--- test/MC/Mips/mips64r6/invalid.s
+++ test/MC/Mips/mips64r6/invalid.s
@@ -43,3 +43,7 @@
         lsa     $2, $3, $4, 5     # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
         pref -1, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
         pref 32, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
+        dmfc0  $4, $3, -1    # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
+        dmfc0  $4, $3, 8     # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
+        dmfc2  $4, $3, -1    # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
+        dmfc2  $4, $3, 8     # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate