Index: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -918,6 +918,17 @@ Size = 4; return Result; } + + if (hasMips32r6()) { + DEBUG(dbgs() << "Trying MicroMips32r6FPU table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMicroMips32r6FPU32, Instr, Insn, + Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + // This is an invalid instruction. Let the disassembler move forward by the // minimum instruction size. Size = 2; Index: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -870,3 +870,49 @@ let Inst{15-6} = funct; let Inst{5-0} = 0b111100; } + +class POOL32A_MFTC0_FM_MMR6 funct, bits<6> opcode> + : MMR6Arch, MipsR6Inst { + bits<5> rt; + bits<5> rs; + bits<3> sel; + + bits<32> Inst; + + let Inst{31-26} = 0b000000; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-14} = 0; + let Inst{13-11} = sel; + let Inst{10-6} = funct; + let Inst{5-0} = opcode; +} + +class POOL32F_MFTC1_FM_MMR6 funct> + : MMR6Arch { + bits<5> rt; + bits<5> fs; + + bits<32> Inst; + + let Inst{31-26} = 0b010101; + let Inst{25-21} = rt; + let Inst{20-16} = fs; + let Inst{15-14} = 0; + let Inst{13-6} = funct; + let Inst{5-0} = 0b111011; +} + +class POOL32A_MFTC2_FM_MMR6 funct> + : MMR6Arch, MipsR6Inst { + bits<5> rt; + bits<5> impl; + + bits<32> Inst; + + let Inst{31-26} = 0b000000; + let Inst{25-21} = rt; + let Inst{20-16} = impl; + let Inst{15-6} = funct; + let Inst{5-0} = 0b111100; +} Index: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -71,6 +71,12 @@ class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>; class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>; class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>; +class MTC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mtc0", 0b01011, 0b111100>; +class MTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mtc1", 0b10100000>; +class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>; +class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>; +class MTHC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mthc1", 0b11100000>; +class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>; class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>; class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>; class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>; @@ -538,6 +544,62 @@ class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>; class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>; +class MTC0_MMR6_DESC_BASE { + dag InOperandList = (ins SrcRC:$rt, uimm3:$sel); + dag OutOperandList = (outs DstRC:$rs); + string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel"); + list Pattern = []; + Format f = FrmFR; + string BaseOpcode = opstr; +} +class MTC1_MMR6_DESC_BASE< + string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, + InstrItinClass Itin = NoItinerary, SDPatternOperator OpNode = null_frag> + : MipsR6Inst { + dag InOperandList = (ins SrcRC:$rt); + dag OutOperandList = (outs DstRC:$fs); + string AsmString = !strconcat(opstr, "\t$rt, $fs"); + list Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))]; + Format f = FrmFR; + InstrItinClass Itinerary = Itin; + string BaseOpcode = opstr; +} +class MTC1_64_MMR6_DESC_BASE< + string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, + InstrItinClass Itin = NoItinerary> : MipsR6Inst { + dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt); + dag OutOperandList = (outs DstRC:$fs); + string AsmString = !strconcat(opstr, "\t$rt, $fs"); + list Pattern = []; + Format f = FrmFR; + InstrItinClass Itinerary = Itin; + string BaseOpcode = opstr; + // $fs_in is part of a white lie to work around a widespread bug in the FPU + // implementation. See expandBuildPairF64 for details. + let Constraints = "$fs = $fs_in"; +} +class MTC2_MMR6_DESC_BASE { + dag InOperandList = (ins SrcRC:$rt); + dag OutOperandList = (outs DstRC:$impl); + string AsmString = !strconcat(opstr, "\t$rt, $impl"); + list Pattern = []; + Format f = FrmFR; + string BaseOpcode = opstr; +} + +class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd>; +class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd, + II_MTC1, bitconvert>, HARDFLOAT; +class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd>; +class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd>; +class MTHC1_D32_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", AFGR64Opnd, GPR32Opnd>, + HARDFLOAT, FGR_32; +class MTHC1_D64_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", FGR64Opnd, GPR32Opnd>, + HARDFLOAT, FGR_64; +class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd>; + /// Floating Point Instructions class FARITH_MMR6_DESC_BASE, ISA_MICROMIPS32R6; +def : MipsInstAlias<"mtc0 $rt, $rs", + (MTC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"mthc0 $rt, $rs", + (MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>, + ISA_MICROMIPS32R6; //===----------------------------------------------------------------------===// // Index: llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td +++ llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td @@ -84,3 +84,20 @@ let Inst{10-9} = 0b00; let Inst{8-0} = funct; } + +class POOL32S_DMFTC0_FM_MMR6 funct> + : MMR6Arch, MipsR6Inst { + bits<5> rt; + bits<5> rs; + bits<3> sel; + + bits<32> Inst; + + let Inst{31-26} = 0b010110; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-14} = 0; + let Inst{13-11} = sel; + let Inst{10-6} = funct; + let Inst{5-0} = 0b111100; +} Index: llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td @@ -31,6 +31,9 @@ class DINSU_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b110100>; class DINSM_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b000100>; class DINS_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b001100>; +class DMTC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmtc0", 0b01011>; +class DMTC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmtc1", 0b10110000>; +class DMTC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmtc2", 0b0111110100>; //===----------------------------------------------------------------------===// // @@ -98,6 +101,10 @@ class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>; class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1, MipsIns>; +class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd>; +class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd, + II_DMTC1, bitconvert>; +class DMTC2_MM64R6_DESC : MTC2_MMR6_DESC_BASE<"dmtc2", COP2Opnd, GPR64Opnd>; //===----------------------------------------------------------------------===// // @@ -131,4 +138,16 @@ ISA_MICROMIPS64R6; def DINS_MM64R6: R6MMR6Rel, DINS_MM64R6_DESC, DINS_MM64R6_ENC, ISA_MICROMIPS64R6; + def DMTC0_MM64R6 : StdMMR6Rel, DMTC0_MM64R6_ENC, DMTC0_MM64R6_DESC, + ISA_MICROMIPS64R6; + def DMTC1_MM64R6 : StdMMR6Rel, DMTC1_MM64R6_DESC, DMTC1_MM64R6_ENC, + ISA_MICROMIPS64R6; + def DMTC2_MM64R6 : StdMMR6Rel, DMTC2_MM64R6_ENC, DMTC2_MM64R6_DESC, + ISA_MICROMIPS64R6; } + +//===----------------------------------------------------------------------===// +// Instruction aliases +//===----------------------------------------------------------------------===// +def : MipsInstAlias<"dmtc0 $rt, $rd", + (DMTC0_MM64R6 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>; Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td @@ -116,8 +116,6 @@ II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>; def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32; -def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, - MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32; def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, MADDS_FM_MM<0x1>; @@ -147,4 +145,6 @@ ROUND_W_FM_MM<0, 0x6c>; def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>, ROUND_W_FM_MM<0, 0x28>; + def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, + MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32; } Index: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td @@ -625,7 +625,10 @@ // Two operand (implicit 0 selector) versions: def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>; -def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>; +let AdditionalPredicates = [NotInMicroMips] in { + def : MipsInstAlias<"dmtc0 $rt, $rd", + (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>; +} def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>; def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>; Index: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td @@ -373,16 +373,20 @@ MFC1_FM<3>, ISA_MIPS32R2, FGR_64 { let DecoderNamespace = "Mips64"; } -def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, - MFC1_FM<7>, ISA_MIPS32R2, FGR_32; -def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, - MFC1_FM<7>, ISA_MIPS32R2, FGR_64 { - let DecoderNamespace = "Mips64"; +let AdditionalPredicates = [NotInMicroMips] in { + def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, + MFC1_FM<7>, ISA_MIPS32R2, FGR_32; + def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, + MFC1_FM<7>, ISA_MIPS32R2, FGR_64 { + let DecoderNamespace = "Mips64"; + } } def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, bitconvert>, MFC1_FM<1>, ISA_MIPS3; -def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, - bitconvert>, MFC1_FM<5>, ISA_MIPS3; +let AdditionalPredicates = [NotInMicroMips] in { + def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, + bitconvert>, MFC1_FM<5>, ISA_MIPS3; +} def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, ABSS_FM<0x6, 16>; Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td @@ -1888,7 +1888,10 @@ /// Move Control Registers From/To CPU Registers def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32; -def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32; +let AdditionalPredicates = [NotInMicroMips] in { + def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, + ISA_MIPS32; +} def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>; def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>; Index: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -258,3 +258,13 @@ 0x00 0x0f 0x47 0x7c # CHECK: di $15 0x00 0x00 0x43 0x7c # CHECK: tlbinv 0x00 0x00 0x53 0x7c # CHECK: tlbinvf +0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9, 0 +0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9 +0x00 0x22 0x3a 0xfc # CHECK: mtc0 $1, $2, 7 +0x54 0x64 0x28 0x3b # CHECK: mtc1 $3, $f4 +0x00 0xa6 0x5d 0x3c # CHECK: mtc2 $5, $6 +0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8, 0 +0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8 +0x01 0x2a 0x0a 0xf4 # CHECK: mthc0 $9, $10, 1 +0x55 0x6c 0x38 0x3b # CHECK: mthc1 $11, $f12 +0x01 0xae 0x9d 0x3c # CHECK: mthc2 $13, $14 Index: llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -174,3 +174,18 @@ 0x58 0x82 0x20 0x34 # CHECK: dinsu $4, $2, 32, 5 0x58 0x82 0x38 0xc4 # CHECK: dinsm $4, $2, 3, 5 0x58 0x82 0x38 0xcc # CHECK: dins $4, $2, 3, 5 +0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9, 0 +0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9 +0x00 0x22 0x3a 0xfc # CHECK: mtc0 $1, $2, 7 +0x54 0x64 0x28 0x3b # CHECK: mtc1 $3, $f4 +0x00 0xa6 0x5d 0x3c # CHECK: mtc2 $5, $6 +0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8, 0 +0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8 +0x01 0x2a 0x0a 0xf4 # CHECK: mthc0 $9, $10, 1 +0x55 0x6c 0x38 0x3b # CHECK: mthc1 $11, $f12 +0x01 0xae 0x9d 0x3c # CHECK: mthc2 $13, $14 +0x59 0xf0 0x02 0xfc # CHECK: dmtc0 $15, $16, 0 +0x59 0xf0 0x02 0xfc # CHECK: dmtc0 $15, $16 +0x5a 0x32 0x2a 0xfc # CHECK: dmtc0 $17, $18, 5 +0x56 0x74 0x2c 0x3b # CHECK: dmtc1 $19, $f20 +0x02 0xb6 0x7d 0x3c # CHECK: dmtc2 $21, $22 Index: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s +++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s @@ -110,3 +110,7 @@ swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate Index: llvm/trunk/test/MC/Mips/micromips32r6/valid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips32r6/valid.s +++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s @@ -259,3 +259,11 @@ deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c] tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c] tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c] + mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc] + mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc] + mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b] + mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c] + mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4] + mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4] + mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b] + mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c] Index: llvm/trunk/test/MC/Mips/micromips64r6/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips64r6/invalid.s +++ llvm/trunk/test/MC/Mips/micromips64r6/invalid.s @@ -138,3 +138,9 @@ swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate + dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate Index: llvm/trunk/test/MC/Mips/micromips64r6/valid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips64r6/valid.s +++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s @@ -159,4 +159,17 @@ dinsu $4, $2, 32, 5 # CHECK: dinsu $4, $2, 32, 5 # encoding: [0x58,0x82,0x20,0x34] dinsm $4, $2, 3, 5 # CHECK: dinsm $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xc4] dins $4, $2, 3, 5 # CHECK: dins $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xcc] + mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc] + mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc] + mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b] + mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c] + mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4] + mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4] + mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b] + mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c] + dmtc0 $15, $16 # CHECK: dmtc0 $15, $16, 0 # encoding: [0x59,0xf0,0x02,0xfc] + dmtc0 $17, $18, 5 # CHECK: dmtc0 $17, $18, 5 # encoding: [0x5a,0x32,0x2a,0xfc] + dmtc1 $19, $f20 # CHECK: dmtc1 $19, $f20 # encoding: [0x56,0x74,0x2c,0x3b] + dmtc2 $21, $22 # CHECK: dmtc2 $21, $22 # encoding: [0x02,0xb6,0x7d,0x3c] + 1: