Index: llvm/trunk/lib/CodeGen/TailDuplication.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/TailDuplication.cpp
+++ llvm/trunk/lib/CodeGen/TailDuplication.cpp
@@ -590,6 +590,11 @@
     if (MI.isNotDuplicable())
       return false;
 
+    // Convergent instructions can be duplicated only if doing so doesn't add
+    // new control dependencies, which is what we're going to do here.
+    if (MI.isConvergent())
+      return false;
+
     // Do not duplicate 'return' instructions if this is a pre-regalloc run.
     // A return may expand into a lot more instructions (e.g. reload of callee
     // saved registers) after PEI.
Index: llvm/trunk/test/CodeGen/NVPTX/TailDuplication-convergent.ll
===================================================================
--- llvm/trunk/test/CodeGen/NVPTX/TailDuplication-convergent.ll
+++ llvm/trunk/test/CodeGen/NVPTX/TailDuplication-convergent.ll
@@ -0,0 +1,45 @@
+; RUN: llc -O2 -tail-dup-size=100 -enable-tail-merge=0 < %s | FileCheck %s
+target triple = "nvptx64-nvidia-cuda"
+
+declare void @foo()
+declare void @llvm.cuda.syncthreads()
+
+; syncthreads shouldn't be duplicated.
+; CHECK: .func call_syncthreads
+; CHECK: bar.sync
+; CHECK-NOT: bar.sync
+define void @call_syncthreads(i32* %a, i32* %b, i1 %cond, i1 %cond2) nounwind {
+  br i1 %cond, label %L1, label %L2
+  br i1 %cond2, label %Ret, label %L1
+Ret:
+  ret void
+L1:
+  store i32 0, i32* %a
+  br label %L42
+L2:
+  store i32 1, i32* %a
+  br label %L42
+L42:
+  call void @llvm.cuda.syncthreads()
+  br label %Ret
+}
+
+; Check that call_syncthreads really does trigger tail duplication.
+; CHECK: .func call_foo
+; CHECK: call
+; CHECK: call
+define void @call_foo(i32* %a, i32* %b, i1 %cond, i1 %cond2) nounwind {
+  br i1 %cond, label %L1, label %L2
+  br i1 %cond2, label %Ret, label %L1
+Ret:
+  ret void
+L1:
+  store i32 0, i32* %a
+  br label %L42
+L2:
+  store i32 1, i32* %a
+  br label %L42
+L42:
+  call void @foo()
+  br label %Ret
+}