Index: include/llvm/CodeGen/SelectionDAG.h =================================================================== --- include/llvm/CodeGen/SelectionDAG.h +++ include/llvm/CodeGen/SelectionDAG.h @@ -582,6 +582,28 @@ return getVectorShuffle(VT, dl, N1, N2, MaskElts.data()); } + /// Return an ISD::BUILD_VECTOR node. The number of elements in VT, + /// which must be a vector type, must match the number of operands in Ops. + /// The operands must have the same type as VT's element type. + SDValue getBuildVector(SDLoc DL, EVT VT, ArrayRef Ops) { + assert(VT.getVectorNumElements() == Ops.size() && + "Must have the same number of vector elements as operands!"); + return getNode(ISD::BUILD_VECTOR, DL, VT, Ops); + } + + /// Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all + /// elements. VT must be a vector type, and its element type must be the + /// same as Op's type. + SDValue getSplatBuildVector(EVT VT, SDValue Op) { + assert(VT.getVectorElementType() == Op.getValueType() && + "Splatted value must have the vector element type!"); + if (Op.getOpcode() == ISD::UNDEF) + return getNode(ISD::UNDEF, SDLoc(), VT); + + SmallVector Ops(VT.getVectorNumElements(), Op); + return getNode(ISD::BUILD_VECTOR, SDLoc(Op), VT, Ops); + } + /// \brief Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to /// the shuffle node in input but with swapped operands. /// Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1193,11 +1193,8 @@ } SDValue Result(N, 0); - if (VT.isVector()) { - SmallVector Ops; - Ops.assign(VT.getVectorNumElements(), Result); - Result = getNode(ISD::BUILD_VECTOR, DL, VT, Ops); - } + if (VT.isVector()) + Result = getSplatBuildVector(VT, Result); return Result; } @@ -1237,11 +1234,8 @@ } SDValue Result(N, 0); - if (VT.isVector()) { - SmallVector Ops; - Ops.assign(VT.getVectorNumElements(), Result); - Result = getNode(ISD::BUILD_VECTOR, DL, VT, Ops); - } + if (VT.isVector()) + Result = getSplatBuildVector(VT, Result); return Result; } @@ -1610,11 +1604,9 @@ // If the shuffle itself creates a splat, build the vector directly. if (AllSame && SameNumElts) { - const SDValue &Splatted = BV->getOperand(MaskVec[0]); - SmallVector Ops(NElts, Splatted); - EVT BuildVT = BV->getValueType(0); - SDValue NewBV = getNode(ISD::BUILD_VECTOR, dl, BuildVT, Ops); + const SDValue &Splatted = BV->getOperand(MaskVec[0]); + SDValue NewBV = getSplatBuildVector(BuildVT, Splatted); // We may have jumped through bitcasts, so the type of the // BUILD_VECTOR may not match the type of the shuffle. @@ -3299,6 +3291,8 @@ if (!VT.isVector()) return Folded; SmallVector Outputs; + // FIXME: wtf? returns SDValue()? + assert(false); // We may have a vector type but a scalar result. Create a splat. Outputs.resize(VT.getVectorNumElements(), Outputs.back()); // Build a big vector out of the scalar elements we generated. @@ -3356,7 +3350,8 @@ Outputs.resize(VT.getVectorNumElements(), Outputs.back()); // Build a big vector out of the scalar elements we generated. - return getNode(ISD::BUILD_VECTOR, SDLoc(), VT, Outputs); + // FIXME: why no SDLoc? + return getBuildVector(SDLoc(), VT, Outputs); } SDValue SelectionDAG::FoldConstantVectorArithmetic(unsigned Opcode, SDLoc DL, @@ -3448,9 +3443,7 @@ ScalarResults.push_back(ScalarResult); } - assert(ScalarResults.size() == NumElts && - "Unexpected number of scalar results for BUILD_VECTOR"); - return getNode(ISD::BUILD_VECTOR, DL, VT, ScalarResults); + return getBuildVector(DL, VT, ScalarResults); } SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, @@ -3664,7 +3657,7 @@ break; } if (Ops.size() == VT.getVectorNumElements()) - return getNode(ISD::BUILD_VECTOR, DL, VT, Ops); + return getBuildVector(DL, VT, Ops); } break; } @@ -4096,13 +4089,9 @@ } if (VT != Value.getValueType() && !VT.isInteger()) - Value = DAG.getNode(ISD::BITCAST, dl, VT.getScalarType(), Value); - if (VT != Value.getValueType()) { - assert(VT.getVectorElementType() == Value.getValueType() && - "value type should be one vector element here"); - SmallVector BVOps(VT.getVectorNumElements(), Value); - Value = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, BVOps); - } + Value = DAG.getBitcast(VT.getScalarType(), Value); + if (VT != Value.getValueType()) + Value = DAG.getSplatBuildVector(VT, Value); return Value; } Index: lib/Target/AArch64/AArch64ISelLowering.cpp =================================================================== --- lib/Target/AArch64/AArch64ISelLowering.cpp +++ lib/Target/AArch64/AArch64ISelLowering.cpp @@ -2198,8 +2198,7 @@ // The values are implicitly truncated so sext vs. zext doesn't matter. Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32)); } - return DAG.getNode(ISD::BUILD_VECTOR, dl, - MVT::getVectorVT(TruncVT, NumElts), Ops); + return DAG.getBuildVector(dl, MVT::getVectorVT(TruncVT, NumElts), Ops); } static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { @@ -5616,16 +5615,16 @@ Shuffle = DAG.getNode( ISD::INTRINSIC_WO_CHAIN, DL, IndexVT, DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst, - DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, - makeArrayRef(TBLMask.data(), IndexLen))); + DAG.getBuildVector(DL, IndexVT, + makeArrayRef(TBLMask.data(), IndexLen))); } else { if (IndexLen == 8) { V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst); Shuffle = DAG.getNode( ISD::INTRINSIC_WO_CHAIN, DL, IndexVT, DAG.getConstant(Intrinsic::aarch64_neon_tbl1, DL, MVT::i32), V1Cst, - DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, - makeArrayRef(TBLMask.data(), IndexLen))); + DAG.getBuildVector(DL, IndexVT, + makeArrayRef(TBLMask.data(), IndexLen))); } else { // FIXME: We cannot, for the moment, emit a TBL2 instruction because we // cannot currently represent the register constraints on the input @@ -5635,10 +5634,9 @@ // &TBLMask[0], IndexLen)); Shuffle = DAG.getNode( ISD::INTRINSIC_WO_CHAIN, DL, IndexVT, - DAG.getConstant(Intrinsic::aarch64_neon_tbl2, DL, MVT::i32), - V1Cst, V2Cst, - DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, - makeArrayRef(TBLMask.data(), IndexLen))); + DAG.getConstant(Intrinsic::aarch64_neon_tbl2, DL, MVT::i32), V1Cst, + V2Cst, DAG.getBuildVector(DL, IndexVT, + makeArrayRef(TBLMask.data(), IndexLen))); } } return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle); @@ -6147,7 +6145,7 @@ } Ops.push_back(Lane); } - return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); + return DAG.getBuildVector(dl, VT, Ops); } SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, @@ -6448,7 +6446,7 @@ for (unsigned i = 0; i < NumElts; ++i) Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i))); EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts); - SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops); + SDValue Val = DAG.getBuildVector(dl, VecVT, Ops); Val = LowerBUILD_VECTOR(Val, DAG); if (Val.getNode()) return DAG.getNode(ISD::BITCAST, dl, VT, Val); Index: lib/Target/X86/X86ISelLowering.cpp =================================================================== --- lib/Target/X86/X86ISelLowering.cpp +++ lib/Target/X86/X86ISelLowering.cpp @@ -4475,7 +4475,7 @@ Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) : DAG.getConstant(0, dl, EltVT)); } - SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops); + SDValue ConstsNode = DAG.getBuildVector(dl, ConstVecVT, Ops); if (Split) ConstsNode = DAG.getBitcast(VT, ConstsNode); return ConstsNode; @@ -4535,8 +4535,8 @@ // If the input is a buildvector just emit a smaller one. if (Vec.getOpcode() == ISD::BUILD_VECTOR) - return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT, - makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk)); + return DAG.getNode(ISD::BUILD_VECTOR, + dl, ResultVT, makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk)); SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl); return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx); @@ -5984,17 +5984,11 @@ "Unexpected type in LowerBUILD_VECTORvXi1!"); SDLoc dl(Op); - if (ISD::isBuildVectorAllZeros(Op.getNode())) { - SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1); - SmallVector Ops(VT.getVectorNumElements(), Cst); - return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); - } + if (ISD::isBuildVectorAllZeros(Op.getNode())) + return DAG.getSplatBuildVector(VT, DAG.getTargetConstant(0, dl, MVT::i1)); - if (ISD::isBuildVectorAllOnes(Op.getNode())) { - SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1); - SmallVector Ops(VT.getVectorNumElements(), Cst); - return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); - } + if (ISD::isBuildVectorAllOnes(Op.getNode())) + return DAG.getSplatBuildVector(VT, DAG.getTargetConstant(1, dl, MVT::i1)); if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) { SDValue Imm = ConvertI1VectorToInteger(Op, DAG); @@ -6682,10 +6676,10 @@ EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); // Build both the lower and upper subvector. - SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, - makeArrayRef(&V[0], NumElems/2)); - SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, - makeArrayRef(&V[NumElems / 2], NumElems/2)); + SDValue Lower = + DAG.getBuildVector(dl, HVT, makeArrayRef(&V[0], NumElems / 2)); + SDValue Upper = DAG.getBuildVector( + dl, HVT, makeArrayRef(&V[NumElems / 2], NumElems / 2)); // Recreate the wider vector with the lower and upper part. if (VT.is256BitVector()) @@ -7205,7 +7199,7 @@ if (!V) return SDValue(); // No non-zeroable elements! - SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps); + SDValue VMask = DAG.getBuildVector(DL, VT, VMaskOps); V = DAG.getNode(VT.isFloatingPoint() ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND, DL, VT, V, VMask); @@ -7233,7 +7227,7 @@ MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero); } - SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps); + SDValue V1Mask = DAG.getBuildVector(DL, VT, MaskOps); V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask); // We have to cast V2 around. MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64); @@ -7396,10 +7390,9 @@ V1 = DAG.getBitcast(BlendVT, V1); V2 = DAG.getBitcast(BlendVT, V2); - return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT, - DAG.getNode(ISD::BUILD_VECTOR, DL, - BlendVT, VSELECTMask), - V1, V2)); + return DAG.getBitcast( + VT, DAG.getNode(ISD::VSELECT, DL, BlendVT, + DAG.getBuildVector(DL, BlendVT, VSELECTMask), V1, V2)); } default: @@ -7948,10 +7941,9 @@ (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8); } InputV = DAG.getBitcast(MVT::v16i8, InputV); - return DAG.getBitcast(VT, - DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV, - DAG.getNode(ISD::BUILD_VECTOR, DL, - MVT::v16i8, PSHUFBMask))); + return DAG.getBitcast( + VT, DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV, + DAG.getBuildVector(DL, MVT::v16i8, PSHUFBMask))); } // If we are extending from an offset, ensure we start on a boundary that @@ -9627,11 +9619,11 @@ if (V1InUse) V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, DAG.getBitcast(MVT::v16i8, V1), - DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask)); + DAG.getBuildVector(DL, MVT::v16i8, V1Mask)); if (V2InUse) V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, DAG.getBitcast(MVT::v16i8, V2), - DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask)); + DAG.getBuildVector(DL, MVT::v16i8, V2Mask)); // If we need shuffled inputs from both, blend the two. SDValue V; @@ -10265,8 +10257,8 @@ LoOps.push_back(BV->getOperand(i)); HiOps.push_back(BV->getOperand(i + OrigSplitNumElements)); } - LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps); - HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps); + LoV = DAG.getBuildVector(DL, OrigSplitVT, LoOps); + HiV = DAG.getBuildVector(DL, OrigSplitVT, HiOps); } return std::make_pair(DAG.getBitcast(SplitVT, LoV), DAG.getBitcast(SplitVT, HiV)); @@ -11009,14 +11001,12 @@ VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32) : DAG.getConstant(Mask[i], DL, MVT::i32); if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask)) - return DAG.getNode( - X86ISD::VPERMILPV, DL, MVT::v8f32, V1, - DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask)); + return DAG.getNode(X86ISD::VPERMILPV, DL, MVT::v8f32, V1, + DAG.getBuildVector(DL, MVT::v8i32, VPermMask)); if (Subtarget.hasAVX2()) - return DAG.getNode( - X86ISD::VPERMV, DL, MVT::v8f32, - DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1); + return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32, + DAG.getBuildVector(DL, MVT::v8i32, VPermMask), V1); // Otherwise, fall back. return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask, @@ -11103,9 +11093,8 @@ for (int i = 0; i < 8; ++i) VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32) : DAG.getConstant(Mask[i], DL, MVT::i32); - return DAG.getNode( - X86ISD::VPERMV, DL, MVT::v8i32, - DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1); + return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8i32, + DAG.getBuildVector(DL, MVT::v8i32, VPermMask), V1); } // Try to simplify this by merging 128-bit lanes to enable a lane-based @@ -11193,11 +11182,11 @@ PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8); PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8); } - return DAG.getBitcast(MVT::v16i16, - DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, - DAG.getBitcast(MVT::v32i8, V1), - DAG.getNode(ISD::BUILD_VECTOR, DL, - MVT::v32i8, PSHUFBMask))); + return DAG.getBitcast( + MVT::v16i16, + DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, + DAG.getBitcast(MVT::v32i8, V1), + DAG.getBuildVector(DL, MVT::v32i8, PSHUFBMask))); } // Try to simplify this by merging 128-bit lanes to enable a lane-based @@ -11271,9 +11260,8 @@ : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL, MVT::i8); - return DAG.getNode( - X86ISD::PSHUFB, DL, MVT::v32i8, V1, - DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)); + return DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, V1, + DAG.getBuildVector(DL, MVT::v32i8, PSHUFBMask)); } // Try to simplify this by merging 128-bit lanes to enable a lane-based @@ -13175,23 +13163,14 @@ // Create the splat vector for 0x4b000000. SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32); - SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow, - CstLow, CstLow, CstLow, CstLow}; - SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, - makeArrayRef(&CstLowArray[0], NumElts)); + SDValue VecCstLow = DAG.getSplatBuildVector(VecIntVT, CstLow); // Create the splat vector for 0x53000000. SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32); - SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh, - CstHigh, CstHigh, CstHigh, CstHigh}; - SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, - makeArrayRef(&CstHighArray[0], NumElts)); + SDValue VecCstHigh = DAG.getSplatBuildVector(VecIntVT, CstHigh); // Create the right shift. SDValue CstShift = DAG.getConstant(16, DL, MVT::i32); - SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift, - CstShift, CstShift, CstShift, CstShift}; - SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, - makeArrayRef(&CstShiftArray[0], NumElts)); + SDValue VecCstShift = DAG.getSplatBuildVector(VecIntVT, CstShift); SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift); SDValue Low, High; @@ -13214,8 +13193,7 @@ VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32)); } else { SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32); - SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask, - CstMask, CstMask, CstMask); + SDValue VecCstMask = DAG.getSplatBuildVector(VecIntVT, CstMask); // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000; SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask); Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow); @@ -13227,10 +13205,7 @@ // Create the vector constant for -(0x1.0p39f + 0x1.0p23f). SDValue CstFAdd = DAG.getConstantFP( APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32); - SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd, - CstFAdd, CstFAdd, CstFAdd, CstFAdd}; - SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT, - makeArrayRef(&CstFAddArray[0], NumElts)); + SDValue VecCstFAdd = DAG.getSplatBuildVector(VecFloatVT, CstFAdd); // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f); SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High); @@ -13547,9 +13522,8 @@ SDValue ResultOps[] = { Low32, High32 }; - SDValue pair = IsReplace - ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps) - : DAG.getMergeValues(ResultOps, DL); + SDValue pair = IsReplace ? DAG.getBuildVector(DL, MVT::i64, ResultOps) + : DAG.getMergeValues(ResultOps, DL); return std::make_pair(pair, SDValue()); } else { // Build the FP_TO_INT*_IN_MEM @@ -13765,7 +13739,7 @@ for (unsigned j = 0; j < 8; ++j) pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8)); } - SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask); + SDValue BV = DAG.getBuildVector(DL, MVT::v32i8, pshufbMask); In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV); In = DAG.getBitcast(MVT::v4i64, In); @@ -14787,7 +14761,7 @@ ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT)); } - return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1); + return DAG.getBuildVector(dl, VT, ULTOp1); } static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget, @@ -15011,8 +14985,7 @@ } else { SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32); SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32); - SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, - Sign, Zero, Sign, Zero); + SB = DAG.getBuildVector(dl, MVT::v4i32, {Sign, Zero, Sign, Zero}); } Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB); Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB); @@ -16455,7 +16428,7 @@ break; } - return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts); + return DAG.getBuildVector(dl, VT, Elts); } return DAG.getNode(Opc, dl, VT, SrcOp, @@ -16503,7 +16476,7 @@ ShOps.push_back(DAG.getUNDEF(SVT)); MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64; - ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps); + ShAmt = DAG.getBuildVector(dl, BVT, ShOps); } // The return type has to be a 128-bit type with the same element @@ -19166,7 +19139,7 @@ } Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT)); } - SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts); + SDValue BV = DAG.getBuildVector(dl, VT, Elts); return DAG.getNode(ISD::MUL, dl, VT, R, BV); } @@ -19519,8 +19492,8 @@ ArrayRef Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2); ArrayRef Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2); - Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts); - Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts); + Amt1 = DAG.getBuildVector(dl, NewVT, Amt1Csts); + Amt2 = DAG.getBuildVector(dl, NewVT, Amt2Csts); } else { // Variable shift amount Amt1 = Extract128BitVector(Amt, 0, DAG, dl); @@ -19898,7 +19871,7 @@ Elts.append(NumElts, DAG.getUNDEF(SVT)); EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2); - SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts); + SDValue BV = DAG.getBuildVector(dl, NewVT, Elts); SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV); return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64, DAG.getIntPtrConstant(0, dl)); @@ -19933,7 +19906,6 @@ SDLoc DL(V); MVT ByteVecVT = V.getSimpleValueType(); MVT EltVT = VT.getVectorElementType(); - int NumElts = VT.getVectorNumElements(); assert(ByteVecVT.getVectorElementType() == MVT::i8 && "Expected value to have byte element type."); assert(EltVT != MVT::i8 && @@ -19984,8 +19956,7 @@ // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s // right by 8. It is important to shift as i16s as i8 vector shift isn't // directly supported. - SmallVector Shifters(NumElts, DAG.getConstant(8, DL, EltVT)); - SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters); + SDValue Shifter = DAG.getSplatBuildVector(VT, DAG.getConstant(8, DL, EltVT)); SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter); V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl), DAG.getBitcast(ByteVecVT, V)); @@ -20024,14 +19995,13 @@ SmallVector LUTVec; for (int i = 0; i < NumByteElts; ++i) LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8)); - SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec); - SmallVector Mask0F(NumByteElts, - DAG.getConstant(0x0F, DL, MVT::i8)); - SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F); + SDValue InRegLUT = DAG.getBuildVector(DL, ByteVecVT, LUTVec); + SDValue M0F = + DAG.getSplatBuildVector(ByteVecVT, DAG.getConstant(0x0F, DL, MVT::i8)); // High nibbles - SmallVector Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8)); - SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four); + SDValue Four = DAG.getConstant(4, DL, MVT::i8); + SDValue FourV = DAG.getSplatBuildVector(ByteVecVT, Four); SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV); // Low nibbles @@ -20072,19 +20042,15 @@ auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) { MVT VT = V.getSimpleValueType(); - SmallVector Shifters( - VT.getVectorNumElements(), - DAG.getConstant(Shifter, DL, VT.getVectorElementType())); + SDValue ShifterV = DAG.getConstant(Shifter, DL, VT.getVectorElementType()); return DAG.getNode(OpCode, DL, VT, V, - DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters)); + DAG.getSplatBuildVector(VT, ShifterV)); }; + // FIXME: isn't this the same as GetShift? auto GetMask = [&](SDValue V, APInt Mask) { MVT VT = V.getSimpleValueType(); - SmallVector Masks( - VT.getVectorNumElements(), - DAG.getConstant(Mask, DL, VT.getVectorElementType())); - return DAG.getNode(ISD::AND, DL, VT, V, - DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks)); + SDValue MaskV = DAG.getConstant(Mask, DL, VT.getVectorElementType()); + return DAG.getNode(ISD::AND, DL, VT, V, DAG.getSplatBuildVector(VT, MaskV)); }; // We don't want to incur the implicit masks required to SRL vNi8 vectors on @@ -20322,7 +20288,7 @@ DAG.getUNDEF(EltVT); for (unsigned i = 0; i < WidenNumElts - InNumElts; ++i) Ops.push_back(FillVal); - return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops); + return DAG.getBuildVector(dl, NVT, Ops); } SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, NVT) : DAG.getUNDEF(NVT); @@ -20813,7 +20779,7 @@ N->getOperand(0)); SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl, MVT::f64); - SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias); + SDValue VBias = DAG.getSplatBuildVector(MVT::v2f64, Bias); SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn, DAG.getBitcast(MVT::v2i64, VBias)); Or = DAG.getBitcast(MVT::v2f64, Or); @@ -20959,7 +20925,7 @@ Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, ToVecInt, DAG.getIntPtrConstant(i, dl))); - Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts)); + Results.push_back(DAG.getBuildVector(dl, DstVT, Elts)); } } } @@ -23516,8 +23482,7 @@ MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes); Res = DAG.getBitcast(ByteVT, Input); DCI.AddToWorklist(Res.getNode()); - SDValue PSHUFBMaskOp = - DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask); + SDValue PSHUFBMaskOp = DAG.getBuildVector(DL, ByteVT, PSHUFBMask); DCI.AddToWorklist(PSHUFBMaskOp.getNode()); Res = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Res, PSHUFBMaskOp); DCI.AddToWorklist(Res.getNode()); @@ -26047,8 +26012,7 @@ if (RHSConstSplat) { N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(), SDValue(RHSConstSplat, 0)); - SmallVector C(WideVT.getVectorNumElements(), N1); - N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C); + N1 = DAG.getSplatBuildVector(WideVT, N1); } else if (RHSTrunc) { N1 = N1->getOperand(0); } @@ -26607,8 +26571,7 @@ // The pattern is detected. Subtract one from the constant vector, then // demote it and emit X86ISD::AVG instruction. SDValue One = DAG.getConstant(1, DL, InScalarVT); - SDValue Ones = DAG.getNode(ISD::BUILD_VECTOR, DL, InVT, - SmallVector(NumElems, One)); + SDValue Ones = DAG.getSplatBuildVector(InVT, One); Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], Ones); Operands[1] = DAG.getNode(ISD::TRUNCATE, DL, VT, Operands[1]); return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),