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    +
  1. Generalize target-specific backend passes that could be target-independent, + by adding necessary target hooks and making sure all IR/MI features (such as + register masks and predicated instructions) are properly handled. Enable these + for other targets where doing so is demonstrably beneficial. + For example: +
    1. lib/Target/Hexagon/RDF*
    2. +
    3. lib/Target/AArch64/AArch64AddressTypePromotion.cpp
    4. +
    +
  2. Merge the delay slot filling logic that is duplicated into (at least) the Sparc and Mips backends into a single target independent pass. Likewise, the branch shortening logic in several targets should be merged