Index: lib/Target/Mips/MicroMipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrInfo.td
+++ lib/Target/Mips/MicroMipsInstrInfo.td
@@ -49,7 +49,7 @@
 
 class mem_mm_4_generic : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops GPRMM16, simm4);
+  let MIOperandInfo = (ops ptr_rc, simm4);
   let OperandType = "OPERAND_MEMORY";
   let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
 }
@@ -75,7 +75,7 @@
 
 def mem_mm_sp_imm5_lsl2 : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
+  let MIOperandInfo = (ops ptr_rc:$base, simm5:$offset);
   let OperandType = "OPERAND_MEMORY";
   let ParserMatchClass = MicroMipsMemSPAsmOperand;
   let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
@@ -90,7 +90,7 @@
 
 def mem_mm_9 : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops GPR32, simm9);
+  let MIOperandInfo = (ops ptr_rc, simm9);
   let EncoderMethod = "getMemEncodingMMImm9";
   let ParserMatchClass = MipsMemSimm9AsmOperand;
   let OperandType = "OPERAND_MEMORY";
@@ -98,7 +98,7 @@
 
 def mem_mm_12 : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops GPR32, simm12);
+  let MIOperandInfo = (ops ptr_rc, simm12);
   let EncoderMethod = "getMemEncodingMMImm12";
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";
@@ -106,7 +106,7 @@
 
 def mem_mm_16 : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops GPR32, simm16);
+  let MIOperandInfo = (ops ptr_rc, simm16);
   let EncoderMethod = "getMemEncodingMMImm16";
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";
@@ -122,7 +122,7 @@
 
 def mem_mm_4sp : Operand<i32> {
   let PrintMethod = "printMemOperand";
-  let MIOperandInfo = (ops GPR32, uimm8);
+  let MIOperandInfo = (ops ptr_rc, uimm8);
   let EncoderMethod = "getMemEncodingMMImm4sp";
   let ParserMatchClass = MipsMemUimm4AsmOperand;
   let OperandType = "OPERAND_MEMORY";
@@ -203,7 +203,7 @@
   let ParserMatchClass = MovePRegPairAsmOperand;
   let PrintMethod = "printRegisterList";
   let DecoderMethod = "DecodeMovePRegPair";
-  let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
+  let MIOperandInfo = (ops ptr_rc, ptr_rc);
 }
 
 class MovePMM16<string opstr, RegisterOperand RO> :
@@ -224,7 +224,7 @@
   let ParserMatchClass = RegPairAsmOperand;
   let PrintMethod = "printRegisterPair";
   let DecoderMethod = "DecodeRegPairOperand";
-  let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
+  let MIOperandInfo = (ops ptr_rc, ptr_rc);
 }
 
 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
Index: lib/Target/Mips/MipsMachineFunction.cpp
===================================================================
--- lib/Target/Mips/MipsMachineFunction.cpp
+++ lib/Target/Mips/MipsMachineFunction.cpp
@@ -42,7 +42,9 @@
       STI.inMips16Mode()
           ? &Mips::CPU16RegsRegClass
           : STI.inMicroMipsMode()
-                ? &Mips::GPRMM16RegClass
+                ? STI.hasMips64()
+                      ? &Mips::GPRMM16_64RegClass
+                      : &Mips::GPRMM16RegClass
                 : static_cast<const MipsTargetMachine &>(MF.getTarget())
                           .getABI()
                           .IsN64()
Index: lib/Target/Mips/MipsRegisterInfo.cpp
===================================================================
--- lib/Target/Mips/MipsRegisterInfo.cpp
+++ lib/Target/Mips/MipsRegisterInfo.cpp
@@ -51,7 +51,13 @@
 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
                                      unsigned Kind) const {
   MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
-  return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
+  bool inMicroMips = MF.getSubtarget<MipsSubtarget>().inMicroMipsMode();
+ 
+  return ABI.ArePtrs64bit() ?
+             inMicroMips ?
+                 &Mips::GPRMM16_64RegClass : &Mips::GPR64RegClass
+             : inMicroMips ?
+                 &Mips::GPRMM16RegClass : &Mips::GPR32RegClass;
 }
 
 unsigned
Index: lib/Target/Mips/MipsRegisterInfo.td
===================================================================
--- lib/Target/Mips/MipsRegisterInfo.td
+++ lib/Target/Mips/MipsRegisterInfo.td
@@ -330,6 +330,12 @@
   // Reserved
   K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
 
+def GPRMM16_64 : RegisterClass<"Mips", [i64], 64, (add
+  // Callee save
+  S0_64, S1_64,
+  // Return Values and Arguments
+  V0_64, V1_64, A0_64, A1_64, A2_64, A3_64)>;
+
 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
   // Return Values and Arguments
   V0, V1, A0, A1, A2, A3,
Index: test/CodeGen/Mips/invalid_operands.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/invalid_operands.ll
@@ -0,0 +1,23 @@
+; RUN: llc %s -march=mips -mcpu=mips32r3 -mattr=micromips -filetype=asm \
+; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
+; RUN: llc %s -march=mips -mcpu=mips64r3 -mattr=micromips -filetype=asm \
+; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
+
+%struct.T = type { i32 }
+
+$_ZN1TaSERKS_ = comdat any
+
+define linkonce_odr void @_ZN1TaSERKS_(%struct.T* %this, %struct.T* dereferenceable(4) %t) #0 comdat align 2 {
+entry:
+  %this.addr = alloca %struct.T*, align 4
+  %t.addr = alloca %struct.T*, align 4
+  %this1 = load %struct.T*, %struct.T** %this.addr, align 4
+  %0 = load %struct.T*, %struct.T** %t.addr, align 4
+  %V3 = getelementptr inbounds %struct.T, %struct.T* %0, i32 0, i32 0
+  %1 = load i32, i32* %V3, align 4
+  %V4 = getelementptr inbounds %struct.T, %struct.T* %this1, i32 0, i32 0
+  store i32 %1, i32* %V4, align 4
+  ret void
+}
+
+; CHECK: lw16 ${{[0-9]+}}, 0($2)
Index: test/CodeGen/Mips/micromips-addiu.ll
===================================================================
--- test/CodeGen/Mips/micromips-addiu.ll
+++ test/CodeGen/Mips/micromips-addiu.ll
@@ -1,5 +1,8 @@
 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
 ; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+; For microMIPS64, also check 32 to 64 bit registers and 64 to 32 bit register copies
+; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
 
 @x = global i32 65504, align 4
 @y = global i32 60929, align 4
Index: test/CodeGen/Mips/micromips-andi.ll
===================================================================
--- test/CodeGen/Mips/micromips-andi.ll
+++ test/CodeGen/Mips/micromips-andi.ll
@@ -1,5 +1,8 @@
 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
 ; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+; For microMIPS64, also check 32 to 64 bit registers and 64 to 32 bit register copies
+; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
 
 @x = global i32 65504, align 4
 @y = global i32 60929, align 4
Index: test/CodeGen/Mips/micromips-gp-rc.ll
===================================================================
--- test/CodeGen/Mips/micromips-gp-rc.ll
+++ test/CodeGen/Mips/micromips-gp-rc.ll
@@ -1,5 +1,8 @@
 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
 ; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+; For microMIPS64, also check 32 to 64 bit registers and 64 to 32 bit register copies
+; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
 
 @g = external global i32