Index: llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td +++ llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td @@ -362,8 +362,7 @@ let Inst{63-32} = src2; } -class VOP3e op> : Enc64 { - bits<8> vdst; +class VOP3a op> : Enc64 { bits<2> src0_modifiers; bits<9> src0; bits<2> src1_modifiers; @@ -373,7 +372,6 @@ bits<1> clamp; bits<2> omod; - let Inst{7-0} = vdst; let Inst{8} = src0_modifiers{1}; let Inst{9} = src1_modifiers{1}; let Inst{10} = src2_modifiers{1}; @@ -389,6 +387,20 @@ let Inst{63} = src2_modifiers{0}; } +class VOP3e op> : VOP3a { + bits<8> vdst; + + let Inst{7-0} = vdst; +} + +// Encoding used for VOPC instructions encoded as VOP3 +// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst +class VOP3ce op> : VOP3a { + bits<8> sdst; + + let Inst{7-0} = sdst; +} + class VOP3be op> : Enc64 { bits<8> vdst; bits<2> src0_modifiers; Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1244,7 +1244,7 @@ } } - const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::dst); + const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::vdst); const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0); const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1); const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2); Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td +++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td @@ -1186,8 +1186,8 @@ // Returns the assembly string for the inputs and outputs of a VOP[12C] // instruction. This does not add the _e32 suffix, so it can be reused // by getAsm64. -class getAsm32 { - string dst = "$dst"; +class getAsm32 { + string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC string src0 = ", $src0"; string src1 = ", $src1"; string src2 = ", $src2"; @@ -1199,7 +1199,8 @@ // Returns the assembly string for the inputs and outputs of a VOP3 // instruction. -class getAsm64 { +class getAsm64 { + string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,"); string src1 = !if(!eq(NumSrcArgs, 1), "", !if(!eq(NumSrcArgs, 2), " $src1_modifiers", @@ -1207,19 +1208,20 @@ string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", ""); string ret = !if(!eq(HasModifiers, 0), - getAsm32.ret, - "$dst, "#src0#src1#src2#"$clamp"#"$omod"); + getAsm32.ret, + dst#", "#src0#src1#src2#"$clamp"#"$omod"); } -class getAsmDPP { +class getAsmDPP { + string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,"); string src1 = !if(!eq(NumSrcArgs, 1), "", !if(!eq(NumSrcArgs, 2), " $src1_modifiers", " $src1_modifiers,")); string args = !if(!eq(HasModifiers, 0), - getAsm32<0, NumSrcArgs>.ret, + getAsm32<0, NumSrcArgs, DstVT>.ret, src0#src1); - string ret = " $dst"#args#", $dpp_ctrl, "#"$bound_ctrl, "#"$bank_mask, "#"$row_mask"; + string ret = " "#dst#args#", $dpp_ctrl, "#"$bound_ctrl, "#"$bank_mask, "#"$row_mask"; } class VOPProfile _ArgVT> { @@ -1245,22 +1247,23 @@ field int NumSrcArgs = getNumSrcArgs.ret; field bit HasModifiers = hasModifiers.ret; - field dag Outs = !if(HasDst,(outs DstRC:$dst),(outs)); + field dag Outs = !if(HasDst,(outs DstRC:$vdst),(outs)); // VOP3b instructions are a special case with a second explicit // output. This is manually overridden for them. field dag Outs32 = Outs; field dag Outs64 = Outs; - field dag OutsDPP = (outs DstRCDPP:$dst); + field dag OutsDPP = !if(!eq(DstVT.Size, 1), (outs DstRCDPP:$sdst), // sdst for VOPC + (outs DstRCDPP:$vdst)); field dag Ins32 = getIns32.ret; field dag Ins64 = getIns64.ret; field dag InsDPP = getInsDPP.ret; - field string Asm32 = getAsm32.ret; - field string Asm64 = getAsm64.ret; - field string AsmDPP = getAsmDPP.ret; + field string Asm32 = getAsm32.ret; + field string Asm64 = getAsm64.ret; + field string AsmDPP = getAsmDPP.ret; } // FIXME: I think these F16/I16 profiles will need to use f16/i16 types in order @@ -1295,10 +1298,10 @@ // Write out to vcc or arbitrary SGPR. def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped]> { - let Asm32 = "$dst, vcc, $src0, $src1"; - let Asm64 = "$dst, $sdst, $src0, $src1"; - let Outs32 = (outs DstRC:$dst); - let Outs64 = (outs DstRC:$dst, SReg_64:$sdst); + let Asm32 = "$vdst, vcc, $src0, $src1"; + let Asm64 = "$vdst, $sdst, $src0, $src1"; + let Outs32 = (outs DstRC:$vdst); + let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst); } // Write out to vcc or arbitrary SGPR and read in from vcc or @@ -1310,10 +1313,10 @@ // restriction. SGPRs are still allowed because it should // technically be possible to use VCC again as src0. let Src0RC32 = VCSrc_32; - let Asm32 = "$dst, vcc, $src0, $src1, vcc"; - let Asm64 = "$dst, $sdst, $src0, $src1, $src2"; - let Outs32 = (outs DstRC:$dst); - let Outs64 = (outs DstRC:$dst, SReg_64:$sdst); + let Asm32 = "$vdst, vcc, $src0, $src1, vcc"; + let Asm64 = "$vdst, $sdst, $src0, $src1, $src2"; + let Outs32 = (outs DstRC:$vdst); + let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst); // Suppress src2 implied by type since the 32-bit encoding uses an // implicit VCC use. @@ -1342,11 +1345,12 @@ let Asm32 = "vcc, $src0, $src1"; // The destination for 32-bit encoding is implicit. let HasDst32 = 0; + let Outs64 = (outs DstRC:$sdst); } class VOPC_Class_Profile : VOPC_Profile { let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1); - let Asm64 = "$dst, $src0_modifiers, $src1"; + let Asm64 = "$sdst, $src0_modifiers, $src1"; } def VOPC_I1_F32_F32 : VOPC_Profile; @@ -1363,25 +1367,26 @@ def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> { let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2); - let Asm64 = "$dst, $src0, $src1, $src2"; + let Asm64 = "$vdst, $src0, $src1, $src2"; } def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>; def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> { field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2); - field string Asm = "$dst, $src0, $vsrc1, $src2"; + field string Asm = "$vdst, $src0, $vsrc1, $src2"; } def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> { let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2); let Ins64 = getIns64, 3, HasModifiers>.ret; - let Asm32 = getAsm32<1, 2>.ret; - let Asm64 = getAsm64<1, 2, HasModifiers>.ret; + let Asm32 = getAsm32<1, 2, f32>.ret; + let Asm64 = getAsm64<1, 2, HasModifiers, f32>.ret; } def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>; def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>; def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>; +// This class is used only with VOPC instructions. Use $sdst for out operand class SIInstAlias : InstAlias , PredicateControl { @@ -1392,13 +1397,13 @@ !if (p.HasDst32, !if (!eq(p.NumSrcArgs, 0), // 1 dst, 0 src - (inst p.DstRC:$dst), + (inst p.DstRC:$sdst), !if (!eq(p.NumSrcArgs, 1), // 1 dst, 1 src - (inst p.DstRC:$dst, p.Src0RC32:$src0), + (inst p.DstRC:$sdst, p.Src0RC32:$src0), !if (!eq(p.NumSrcArgs, 2), // 1 dst, 2 src - (inst p.DstRC:$dst, p.Src0RC32:$src0, p.Src1RC32:$src1), + (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1), // else - unreachable (inst)))), // else @@ -1481,8 +1486,6 @@ class VOP1_DPP : VOP1_DPPe , VOP_DPP { - // FIXME: remove when we are using the correct names for the encoding fields. - field bit vdst = 0; let AssemblerPredicates = [isVI]; let src0_modifiers = !if(p.HasModifiers, ?, 0); let src1_modifiers = 0; @@ -1589,6 +1592,22 @@ let AssemblerPredicates = [isVI]; } +class VOP3_C_Real_si op, dag outs, dag ins, string asm, string opName, + bit HasMods = 0, bit VOP3Only = 0> : + VOP3Common , + VOP3ce , + SIMCInstr { + let AssemblerPredicates = [isSICI]; +} + +class VOP3_C_Real_vi op, dag outs, dag ins, string asm, string opName, + bit HasMods = 0, bit VOP3Only = 0> : + VOP3Common , + VOP3ce_vi , + SIMCInstr { + let AssemblerPredicates = [isVI]; +} + class VOP3b_Real_si op, dag outs, dag ins, string asm, string opName, bit HasMods = 0, bit VOP3Only = 0> : VOP3Common , @@ -1694,13 +1713,13 @@ let SchedRW = sched; } - def _si : VOP3_Real_si , + def _si : VOP3_C_Real_si , VOP3DisableFields<1, 0, HasMods> { let Defs = !if(defExec, [EXEC], []); let SchedRW = sched; } - def _vi : VOP3_Real_vi , + def _vi : VOP3_C_Real_vi , VOP3DisableFields<1, 0, HasMods> { let Defs = !if(defExec, [EXEC], []); let SchedRW = sched; @@ -1743,9 +1762,9 @@ SDPatternOperator node = null_frag> : VOP1_Helper < op, opName, P, [], !if(P.HasModifiers, - [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0))]) + [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]) >; multiclass VOP1InstSI ; } @@ -1775,11 +1794,11 @@ string revOp = opName> : VOP2_Helper < op, opName, P, [], !if(P.HasModifiers, - [(set P.DstVT:$dst, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), + [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), revOp >; @@ -1791,11 +1810,11 @@ defm _e64 : VOP3SI_2_m ; } @@ -1818,11 +1837,11 @@ string revOp = opName> : VOP2b_Helper < op, opName, P, [], !if(P.HasModifiers, - [(set P.DstVT:$dst, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), + [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), revOp, !eq(P.NumSrcArgs, 3) >; @@ -1842,11 +1861,11 @@ : VOP2_VI3_Helper < op, opName, P, [], !if(P.HasModifiers, - [(set P.DstVT:$dst, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), + [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), revOp >; @@ -1919,7 +1938,7 @@ defm _e32 : VOPC_m ; - defm _e64 : VOP3_C_m ; } @@ -1930,7 +1949,7 @@ VOPProfile p, list sched> { defm _e32 : VOPC_m ; - defm _e64 : VOP3_C_m , VOP3DisableModFields<1, 0, 0>; } @@ -1943,12 +1962,12 @@ VOPC_Helper < op, opName, [], !if(P.HasModifiers, - [(set i1:$dst, + [(set i1:$sdst, (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), cond))], - [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]), + [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]), DefExec, revOp, P, sched >; @@ -1957,9 +1976,9 @@ list sched> : VOPC_Class_Helper < op, opName, [], !if(P.HasModifiers, - [(set i1:$dst, + [(set i1:$sdst, (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))], - [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]), + [(set i1:$sdst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]), DefExec, opName, P, sched >; @@ -2016,29 +2035,29 @@ multiclass VOP3Inst : VOP3_Helper < - op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64, + op, opName, (outs P.DstRC.RegClass:$vdst), P.Ins64, P.Asm64, !if(!eq(P.NumSrcArgs, 3), !if(P.HasModifiers, - [(set P.DstVT:$dst, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1, + [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))]), !if(!eq(P.NumSrcArgs, 2), !if(P.HasModifiers, - [(set P.DstVT:$dst, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]) + [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]) /* P.NumSrcArgs == 1 */, !if(P.HasModifiers, - [(set P.DstVT:$dst, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))), + [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]))), P.NumSrcArgs, P.HasModifiers, VOP3Only >; @@ -2048,14 +2067,14 @@ VOPProfile P, SDPatternOperator node = null_frag> : VOP3_Helper < op, opName, - (outs P.DstRC.RegClass:$dst), + (outs P.DstRC.RegClass:$vdst), (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0, InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1, InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2, ClampMod:$clamp, omod:$omod), - "$dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", - [(set P.DstVT:$dst, + "$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), Index: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td @@ -1503,7 +1503,7 @@ defm V_OR_B32 : VOP2Inst , "v_or_b32", VOP_I32_I32_I32>; defm V_XOR_B32 : VOP2Inst , "v_xor_b32", VOP_I32_I32_I32>; -let Constraints = "$dst = $src2", DisableEncoding="$src2", +let Constraints = "$vdst = $src2", DisableEncoding="$src2", isConvertibleToThreeAddress = 1 in { defm V_MAC_F32 : VOP2Inst , "v_mac_f32", VOP_MAC>; } @@ -1850,14 +1850,14 @@ let isCodeGenOnly = 1, isPseudo = 1 in { // For use in patterns -def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$dst), +def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst), (ins VSrc_64:$src0, VSrc_64:$src1, SSrc_64:$src2), "", [] >; let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in { // 64-bit vector move instruction. This is mainly used by the SIFoldOperands // pass to enable folding of inline immediates. -def V_MOV_B64_PSEUDO : InstSI <(outs VReg_64:$dst), (ins VSrc_64:$src0), "", []>; +def V_MOV_B64_PSEUDO : InstSI <(outs VReg_64:$vdst), (ins VSrc_64:$src0), "", []>; } // End let hasSideEffects = 0, mayLoad = 0, mayStore = 0 let hasSideEffects = 1, SALU = 1 in { Index: llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -287,9 +287,9 @@ MachineInstrBuilder Inst32 = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(Op32)); - // Add the dst operand if the 32-bit encoding also has an explicit $dst. + // Add the dst operand if the 32-bit encoding also has an explicit $vdst. // For VOPC instructions, this is replaced by an implicit def of vcc. - int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::dst); + int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst); if (Op32DstIdx != -1) { // dst Inst32.addOperand(MI.getOperand(0)); Index: llvm/trunk/lib/Target/AMDGPU/VIInstrFormats.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/VIInstrFormats.td +++ llvm/trunk/lib/Target/AMDGPU/VIInstrFormats.td @@ -104,8 +104,7 @@ let Inst{51-32} = offset; } -class VOP3e_vi op> : Enc64 { - bits<8> vdst; +class VOP3a_vi op> : Enc64 { bits<2> src0_modifiers; bits<9> src0; bits<2> src1_modifiers; @@ -115,7 +114,6 @@ bits<1> clamp; bits<2> omod; - let Inst{7-0} = vdst; let Inst{8} = src0_modifiers{1}; let Inst{9} = src1_modifiers{1}; let Inst{10} = src2_modifiers{1}; @@ -131,6 +129,20 @@ let Inst{63} = src2_modifiers{0}; } +class VOP3e_vi op> : VOP3a_vi { + bits<8> vdst; + + let Inst{7-0} = vdst; +} + +// Encoding used for VOPC instructions encoded as VOP3 +// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst +class VOP3ce_vi op> : VOP3a_vi { + bits<8> sdst; + + let Inst{7-0} = sdst; +} + class VOP3be_vi op> : Enc64 { bits<8> vdst; bits<2> src0_modifiers; @@ -183,21 +195,21 @@ } class VOP1_DPPe op> : VOP_DPPe { - bits<8> dst; + bits<8> vdst; let Inst{8-0} = 0xfa; // dpp let Inst{16-9} = op; - let Inst{24-17} = dst; + let Inst{24-17} = vdst; let Inst{31-25} = 0x3f; //encoding } class VOP2_DPPe op> : Enc32 { - bits<8> dst; + bits<8> vdst; bits<8> src1; let Inst{8-0} = 0xfa; //dpp let Inst{16-9} = src1; - let Inst{24-17} = dst; + let Inst{24-17} = vdst; let Inst{30-25} = op; let Inst{31} = 0x0; //encoding }