Index: lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp =================================================================== --- lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -488,6 +488,9 @@ bool isS16ImmX4() const { return Kind == Expression || (Kind == Immediate && isInt<16>(getImm()) && (getImm() & 3) == 0); } + bool isS16ImmX16() const { return Kind == Expression || + (Kind == Immediate && isInt<16>(getImm()) && + (getImm() & 15) == 0); } bool isS17Imm() const { switch (Kind) { case Expression: Index: lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp =================================================================== --- lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -368,6 +368,21 @@ return MCDisassembler::Success; } +static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, + int64_t Address, const void *Decoder) { + // Decode the memrix16 field (imm, reg), which has the low 12-bits as the + // displacement with 16-byte aligned, and the next 5 bits as the register #. + + uint64_t Base = Imm >> 12; + uint64_t Disp = Imm & 0xFFF; + + assert(Base < 32 && "Invalid base register"); + + Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4))); + Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); + return MCDisassembler::Success; +} + static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { // The cr bit encoding is 0x80 >> cr_reg_num. Index: lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -69,6 +69,9 @@ unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; @@ -249,6 +252,19 @@ return RegBits; } +unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + // Encode (imm, reg) as a memrix16, which has the low 12-bits as the + // displacement and the next 5 bits as the register #. + assert(MI.getOperand(OpNo+1).isReg()); + unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12; + + const MCOperand &MO = MI.getOperand(OpNo); + assert(MO.isImm()); + + return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits; +} unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, Index: lib/Target/PowerPC/PPC.td =================================================================== --- lib/Target/PowerPC/PPC.td +++ lib/Target/PowerPC/PPC.td @@ -124,6 +124,12 @@ def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", "Enable POWER8 vector instructions", [FeatureVSX, FeatureP8Altivec]>; +def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", + "Enable POWER9 Altivec instructions", + [FeatureP8Altivec]>; +def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", + "Enable POWER9 vector instructions", + [FeatureP8Vector, FeatureP9Altivec]>; def FeatureDirectMove : SubtargetFeature<"direct-move", "HasDirectMove", "true", "Enable Power8 direct move instructions", Index: lib/Target/PowerPC/PPCInstrFormats.td =================================================================== --- lib/Target/PowerPC/PPCInstrFormats.td +++ lib/Target/PowerPC/PPCInstrFormats.td @@ -360,6 +360,21 @@ let Inst{30-31} = xo; } +// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] +class DQ_RD6_RS5_DQ12 opcode, bits<3> xo, dag OOL, dag IOL, + string asmstr, InstrItinClass itin, list pattern> + : I { + bits<6> XT; + bits<17> DS_RA; + + let Pattern = pattern; + + let Inst{6-10} = XT{4-0}; + let Inst{11-15} = DS_RA{16-12}; // Register # + let Inst{16-27} = DS_RA{11-0}; // Displacement. + let Inst{28} = XT{5}; + let Inst{29-31} = xo; +} // 1.7.6 X-Form class XForm_base_r3xo opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, Index: lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- lib/Target/PowerPC/PPCInstrInfo.td +++ lib/Target/PowerPC/PPCInstrInfo.td @@ -635,6 +635,13 @@ def dispRIX : Operand { let ParserMatchClass = PPCDispRIXOperand; } +def PPCDispRIX16Operand : AsmOperandClass { + let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16"; + let RenderMethod = "addImmOperands"; +} +def dispRIX16 : Operand { + let ParserMatchClass = PPCDispRIX16Operand; +} def PPCDispSPE8Operand : AsmOperandClass { let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8"; let RenderMethod = "addImmOperands"; @@ -673,6 +680,12 @@ let EncoderMethod = "getMemRIXEncoding"; let DecoderMethod = "decodeMemRIXOperands"; } +def memrix16 : Operand { // memri, imm is 16-aligned, 12-bit, Inst{16:27} + let PrintMethod = "printMemRegImm"; + let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); + let EncoderMethod = "getMemRIX16Encoding"; + let DecoderMethod = "decodeMemRIX16Operands"; +} def spe8dis : Operand { // SPE displacement where the imm is 8-aligned. let PrintMethod = "printMemRegImm"; let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); Index: lib/Target/PowerPC/PPCInstrVSX.td =================================================================== --- lib/Target/PowerPC/PPCInstrVSX.td +++ lib/Target/PowerPC/PPCInstrVSX.td @@ -1759,3 +1759,80 @@ def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)), (i64 VectorExtractions.LE_VARIABLE_DWORD)>; } // IsLittleEndian, HasDirectMove + +// The following VSX instructions were introduced in Power ISA 3.0 +def HasP9Vector : Predicate<"PPCSubTarget->hasP9Vector()">; +let Predicates = [HasP9Vector] in { + //---------------------------------------------------------------------------- + // Vector/Scalar Load/Store Instructions + + let mayLoad = 1 in { + // Load Vector + def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$src), + "lxv $XT, $src", IIC_LdStLFD, []>; + // Load DWord + def LXSD : DSForm_1<57, 2, (outs vrrc:$vD), (ins memrix:$src), + "lxsd $vD, $src", IIC_LdStLFD, []>; + // Load SP from src, convert it to DP, and place in dword[0] + def LXSSP : DSForm_1<57, 3, (outs vrrc:$vD), (ins memrix:$src), + "lxssp $vD, $src", IIC_LdStLFD, []>; + + // [PO T RA RB XO TX] almost equal to [PO S RA RB XO SX], but has different + // "out" and "in" dag + class X_XT6_RA5_RB5 opcode, bits<10> xo, string opc, + RegisterOperand vtype, list pattern> + : XX1Form; + + // Load as Integer Byte/Halfword & Zero Indexed + def LXSIBZX : X_XT6_RA5_RB5<31, 781, "lxsibzx", vsfrc, []>; + def LXSIHZX : X_XT6_RA5_RB5<31, 813, "lxsihzx", vsfrc, []>; + + // Load Vector Halfword*8/Byte*16 Indexed + def LXVH8X : X_XT6_RA5_RB5<31, 812, "lxvh8x" , vsrc, []>; + def LXVB16X : X_XT6_RA5_RB5<31, 876, "lxvb16x", vsrc, []>; + + // Load Vector Indexed + def LXVX : X_XT6_RA5_RB5<31, 268, "lxvx" , vsrc, []>; + + // Load Vector (Left-justified) with Length + def LXVL : X_XT6_RA5_RB5<31, 269, "lxvl" , vsrc, []>; + def LXVLL : X_XT6_RA5_RB5<31, 301, "lxvll" , vsrc, []>; + + // Load Vector Word & Splat Indexed + def LXVWSX : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>; + } // end mayLoad + + let mayStore = 1 in { + // Store Vector + def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$dst), + "stxv $XT, $dst", IIC_LdStSTFD, []>; + // Store DWord + def STXSD : DSForm_1<61, 2, (outs), (ins vrrc:$vS, memrix:$dst), + "stxsd $vS, $dst", IIC_LdStSTFD, []>; + // Convert DP of dword[0] to SP, and Store to dst + def STXSSP : DSForm_1<61, 3, (outs), (ins vrrc:$vS, memrix:$dst), + "stxssp $vS, $dst", IIC_LdStSTFD, []>; + + // [PO S RA RB XO SX] + class X_XS6_RA5_RB5 opcode, bits<10> xo, string opc, + RegisterOperand vtype, list pattern> + : XX1Form; + + // Store as Integer Byte/Halfword Indexed + def STXSIBX : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsfrc, []>; + def STXSIHX : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsfrc, []>; + + // Store Vector Halfword*8/Byte*16 Indexed + def STXVH8X : X_XS6_RA5_RB5<31, 940, "stxvh8x" , vsrc, []>; + def STXVB16X : X_XS6_RA5_RB5<31, 1004, "stxvb16x", vsrc, []>; + + // Store Vector Indexed + def STXVX : X_XS6_RA5_RB5<31, 396, "stxvx" , vsrc, []>; + + // Store Vector (Left-justified) with Length + def STXVL : X_XS6_RA5_RB5<31, 397, "stxvl" , vsrc, []>; + def STXVLL : X_XS6_RA5_RB5<31, 429, "stxvll" , vsrc, []>; + } // end mayStore +} // end HasP9Vector Index: lib/Target/PowerPC/PPCSubtarget.h =================================================================== --- lib/Target/PowerPC/PPCSubtarget.h +++ lib/Target/PowerPC/PPCSubtarget.h @@ -92,6 +92,8 @@ bool HasP8Vector; bool HasP8Altivec; bool HasP8Crypto; + bool HasP9Vector; + bool HasP9Altivec; bool HasFCPSGN; bool HasFSQRT; bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES; @@ -229,6 +231,8 @@ bool hasP8Vector() const { return HasP8Vector; } bool hasP8Altivec() const { return HasP8Altivec; } bool hasP8Crypto() const { return HasP8Crypto; } + bool hasP9Vector() const { return HasP9Vector; } + bool hasP9Altivec() const { return HasP9Altivec; } bool hasMFOCRF() const { return HasMFOCRF; } bool hasISEL() const { return HasISEL; } bool hasPOPCNTD() const { return HasPOPCNTD; } Index: lib/Target/PowerPC/PPCSubtarget.cpp =================================================================== --- lib/Target/PowerPC/PPCSubtarget.cpp +++ lib/Target/PowerPC/PPCSubtarget.cpp @@ -70,6 +70,8 @@ HasP8Vector = false; HasP8Altivec = false; HasP8Crypto = false; + HasP9Vector = false; + HasP9Altivec = false; HasFCPSGN = false; HasFSQRT = false; HasFRE = false; Index: lib/Target/PowerPC/README_P9.txt =================================================================== --- /dev/null +++ lib/Target/PowerPC/README_P9.txt @@ -0,0 +1,59 @@ +//===- README_P9.txt - Notes for improving Power9 code gen ----------------===// + +TODO: Instructions Need Implement Instrinstics or Map to LLVM IR + +Altivec: + +VSX: +- Load/Store Vector: lxv stxv + . Has likely SDAG match + . (set v?:$XT, (load ix16addr:$src)) + store $dst + . Need define ix16addr in PPCInstrInfo.td + ix16addr: 16-byte aligned, see "def memrix16" in PPCInstrInfo.td + +- Load/Store Vector Indexed: lxvx stxvx + . Has likely SDAG match + . (set v?:$XT, (load xoaddr:$src)) + store $dst + +- Load/Store DWord: lxsd stxsd + . Similar to lxsdx/stxsdx + . (set f64:$XT, (load ixaddr:$src)) + store $dst + +- Load/Store SP, with conversion from/to DP: lxssp stxssp + . Similar to lxsspx/stxsspx + . (set f32:$XT, (load ixaddr:$src)) + store $dst + +- Load as Integer Byte/Halfword & Zero Indexed: lxsibzx lxsihzx + . Similar to lxsiwzx + . (set f64:$XT, (PPClfiwzx xoaddr:$src)) + +- Store as Integer Byte/Halfword Indexed: stxsibx stxsihx + . Similar to stxsiwx + . (PPCstfiwx f64:$XT, xoaddr:$dst) + +- Load Vector Halfword*8/Byte*16 Indexed: lxvh8x lxvb16x + . Similar to lxvd2x/lxvw4x + . (set v8i16:$XT, (int_ppc_vsx_lxvh8x xoaddr:$src)) + v16i8 lxvb16x + +- Store Vector Halfword*8/Byte*16 Indexed: stxvh8x stxvb16x + . Similar to stxvd2x/stxvw4x + . (store v8i16:$XT, xoaddr:$dst) + v16i8 + +- Load/Store Vector (Left-justified) with Length: lxvl lxvll stxvl stxvll + . Likely needs an intrinsic + . (set v?:$XT, (int_ppc_vsx_lxvl xoaddr:$src)) + lxvll + + . (int_ppc_vsx_stxvl xoaddr:$dst)) + stxvll + +- Load Vector Word & Splat Indexed: lxvwsx + . Likely needs an intrinsic + . (set v?:$XT, (int_ppc_vsx_lxvwsx xoaddr:$src)) + Index: test/MC/Disassembler/PowerPC/vsx.txt =================================================================== --- test/MC/Disassembler/PowerPC/vsx.txt +++ test/MC/Disassembler/PowerPC/vsx.txt @@ -539,3 +539,80 @@ # CHECK: mtvsrwz 0, 3 0x7c 0x03 0x01 0xe6 + +# Power9 Instructions: + +# CHECK: lxv 61, 32752(31) +0xf7 0xbf 0x7f 0xf9 + +# CHECK: lxv 61, -32768(0) +0xf7 0xa0 0x80 0x09 + +# CHECK: stxv 61, 32752(31) +0xf7 0xbf 0x7f 0xfd + +# CHECK: stxv 61, -32768(0) +0xf7 0xa0 0x80 0x0d + +# CHECK: lxsd 31, -32768(0) +0xe7 0xe0 0x80 0x02 + +# CHECK: lxsd 31, 32764(12) +0xe7 0xec 0x7f 0xfe + +# CHECK: lxssp 31, -32768(0) +0xe7 0xe0 0x80 0x03 + +# CHECK: lxssp 31, 32764(12) +0xe7 0xec 0x7f 0xff + +# CHECK: stxsd 31, 32764(12) +0xf7 0xec 0x7f 0xfe + +# CHECK: stxssp 31, -32768(0) +0xf7 0xe0 0x80 0x03 + +# CHECK: lxvx 57, 12, 27 +0x7f 0x2c 0xda 0x19 + +# CHECK: lxsibzx 57, 12, 27 +0x7f 0x2c 0xde 0x1b + +# CHECK: lxsihzx 57, 12, 27 +0x7f 0x2c 0xde 0x5b + +# CHECK: lxvb16x 57, 12, 27 +0x7f 0x2c 0xde 0xd9 + +# CHECK: lxvh8x 57, 12, 27 +0x7f 0x2c 0xde 0x59 + +# CHECK: lxvl 57, 12, 27 +0x7f 0x2c 0xda 0x1b + +# CHECK: lxvll 57, 12, 27 +0x7f 0x2c 0xda 0x5b + +# CHECK: lxvwsx 57, 12, 27 +0x7f 0x2c 0xda 0xd9 + +# CHECK: stxsibx 57, 12, 27 +0x7f 0x2c 0xdf 0x1b + +# CHECK: stxsihx 57, 12, 27 +0x7f 0x2c 0xdf 0x5b + +# CHECK: stxvh8x 57, 12, 27 +0x7f 0x2c 0xdf 0x59 + +# CHECK: stxvb16x 57, 12, 27 +0x7f 0x2c 0xdf 0xd9 + +# CHECK: stxvx 57, 12, 27 +0x7f 0x2c 0xdb 0x19 + +# CHECK: stxvl 57, 12, 27 +0x7f 0x2c 0xdb 0x1b + +# CHECK: stxvll 57, 12, 27 +0x7f 0x2c 0xdb 0x5b Index: test/MC/PowerPC/vsx.s =================================================================== --- test/MC/PowerPC/vsx.s +++ test/MC/PowerPC/vsx.s @@ -547,3 +547,106 @@ # CHECK-BE: mtvsrwz 0, 3 # encoding: [0x7c,0x03,0x01,0xe6] # CHECK-LE: mtvsrwz 0, 3 # encoding: [0xe6,0x01,0x03,0x7c] mtvsrwz 0, 3 + +# Power9 Instructions: + +# Load/Store Vector, test maximum and minimum displacement value +# CHECK-BE: lxv 61, 32752(31) # encoding: [0xf7,0xbf,0x7f,0xf9] +# CHECK-LE: lxv 61, 32752(31) # encoding: [0xf9,0x7f,0xbf,0xf7] + lxv 61, 32752(31) +# CHECK-BE: lxv 61, -32768(0) # encoding: [0xf7,0xa0,0x80,0x09] +# CHECK-LE: lxv 61, -32768(0) # encoding: [0x09,0x80,0xa0,0xf7] + lxv 61, -32768(0) +# CHECK-BE: stxv 61, 32752(31) # encoding: [0xf7,0xbf,0x7f,0xfd] +# CHECK-LE: stxv 61, 32752(31) # encoding: [0xfd,0x7f,0xbf,0xf7] + stxv 61, 32752(31) +# CHECK-BE: stxv 61, -32768(0) # encoding: [0xf7,0xa0,0x80,0x0d] +# CHECK-LE: stxv 61, -32768(0) # encoding: [0x0d,0x80,0xa0,0xf7] + stxv 61, -32768(0) + +# Load/Store DWord +# CHECK-BE: lxsd 31, -32768(0) # encoding: [0xe7,0xe0,0x80,0x02] +# CHECK-LE: lxsd 31, -32768(0) # encoding: [0x02,0x80,0xe0,0xe7] + lxsd 31, -32768(0) +# CHECK-BE: lxsd 31, 32764(12) # encoding: [0xe7,0xec,0x7f,0xfe] +# CHECK-LE: lxsd 31, 32764(12) # encoding: [0xfe,0x7f,0xec,0xe7] + lxsd 31, 32764(12) +# CHECK-BE: stxsd 31, 32764(12) # encoding: [0xf7,0xec,0x7f,0xfe] +# CHECK-LE: stxsd 31, 32764(12) # encoding: [0xfe,0x7f,0xec,0xf7] + stxsd 31, 32764(12) + +# Load SP from src, convert it to DP, and place in dword[0] +# CHECK-BE: lxssp 31, -32768(0) # encoding: [0xe7,0xe0,0x80,0x03] +# CHECK-LE: lxssp 31, -32768(0) # encoding: [0x03,0x80,0xe0,0xe7] + lxssp 31, -32768(0) +# CHECK-BE: lxssp 31, 32764(12) # encoding: [0xe7,0xec,0x7f,0xff] +# CHECK-LE: lxssp 31, 32764(12) # encoding: [0xff,0x7f,0xec,0xe7] + lxssp 31, 32764(12) + +# Convert DP of dword[0] to SP, and Store to dst +# CHECK-BE: stxssp 31, -32768(0) # encoding: [0xf7,0xe0,0x80,0x03] +# CHECK-LE: stxssp 31, -32768(0) # encoding: [0x03,0x80,0xe0,0xf7] + stxssp 31, -32768(0) + +# Load as Integer Byte/Halfword & Zero Indexed +# CHECK-BE: lxsibzx 57, 12, 27 # encoding: [0x7f,0x2c,0xde,0x1b] +# CHECK-LE: lxsibzx 57, 12, 27 # encoding: [0x1b,0xde,0x2c,0x7f] + lxsibzx 57, 12, 27 +# CHECK-BE: lxsihzx 57, 12, 27 # encoding: [0x7f,0x2c,0xde,0x5b] +# CHECK-LE: lxsihzx 57, 12, 27 # encoding: [0x5b,0xde,0x2c,0x7f] + lxsihzx 57, 12, 27 + +# Load Vector Halfword*8/Byte*16 Indexed +# CHECK-BE: lxvh8x 57, 12, 27 # encoding: [0x7f,0x2c,0xde,0x59] +# CHECK-LE: lxvh8x 57, 12, 27 # encoding: [0x59,0xde,0x2c,0x7f] + lxvh8x 57, 12, 27 +# CHECK-BE: lxvb16x 57, 12, 27 # encoding: [0x7f,0x2c,0xde,0xd9] +# CHECK-LE: lxvb16x 57, 12, 27 # encoding: [0xd9,0xde,0x2c,0x7f] + lxvb16x 57, 12, 27 + +# Load Vector Indexed +# CHECK-BE: lxvx 57, 12, 27 # encoding: [0x7f,0x2c,0xda,0x19] +# CHECK-LE: lxvx 57, 12, 27 # encoding: [0x19,0xda,0x2c,0x7f] + lxvx 57, 12, 27 + +# Load Vector (Left-justified) with Length +# CHECK-BE: lxvl 57, 12, 27 # encoding: [0x7f,0x2c,0xda,0x1b] +# CHECK-LE: lxvl 57, 12, 27 # encoding: [0x1b,0xda,0x2c,0x7f] + lxvl 57, 12, 27 +# CHECK-BE: lxvll 57, 12, 27 # encoding: [0x7f,0x2c,0xda,0x5b] +# CHECK-LE: lxvll 57, 12, 27 # encoding: [0x5b,0xda,0x2c,0x7f] + lxvll 57, 12, 27 + +# Load Vector Word & Splat Indexed +# CHECK-BE: lxvwsx 57, 12, 27 # encoding: [0x7f,0x2c,0xda,0xd9] +# CHECK-LE: lxvwsx 57, 12, 27 # encoding: [0xd9,0xda,0x2c,0x7f] + lxvwsx 57, 12, 27 + +# Store as Integer Byte/Halfword Indexed +# CHECK-BE: stxsibx 57, 12, 27 # encoding: [0x7f,0x2c,0xdf,0x1b] +# CHECK-LE: stxsibx 57, 12, 27 # encoding: [0x1b,0xdf,0x2c,0x7f] + stxsibx 57, 12, 27 +# CHECK-BE: stxsihx 57, 12, 27 # encoding: [0x7f,0x2c,0xdf,0x5b] +# CHECK-LE: stxsihx 57, 12, 27 # encoding: [0x5b,0xdf,0x2c,0x7f] + stxsihx 57, 12, 27 + +# Store Vector Halfword*8/Byte*16 Indexed +# CHECK-BE: stxvh8x 57, 12, 27 # encoding: [0x7f,0x2c,0xdf,0x59] +# CHECK-LE: stxvh8x 57, 12, 27 # encoding: [0x59,0xdf,0x2c,0x7f] + stxvh8x 57, 12, 27 +# CHECK-BE: stxvb16x 57, 12, 27 # encoding: [0x7f,0x2c,0xdf,0xd9] +# CHECK-LE: stxvb16x 57, 12, 27 # encoding: [0xd9,0xdf,0x2c,0x7f] + stxvb16x 57, 12, 27 + +# Store Vector Indexed +# CHECK-BE: stxvx 57, 12, 27 # encoding: [0x7f,0x2c,0xdb,0x19] +# CHECK-LE: stxvx 57, 12, 27 # encoding: [0x19,0xdb,0x2c,0x7f] + stxvx 57, 12, 27 + +# Store Vector (Left-justified) with Length +# CHECK-BE: stxvl 57, 12, 27 # encoding: [0x7f,0x2c,0xdb,0x1b] +# CHECK-LE: stxvl 57, 12, 27 # encoding: [0x1b,0xdb,0x2c,0x7f] + stxvl 57, 12, 27 +# CHECK-BE: stxvll 57, 12, 27 # encoding: [0x7f,0x2c,0xdb,0x5b] +# CHECK-LE: stxvll 57, 12, 27 # encoding: [0x5b,0xdb,0x2c,0x7f] + stxvll 57, 12, 27