Index: lib/Target/Mips/MicroMips32r6InstrFormats.td
===================================================================
--- lib/Target/Mips/MicroMips32r6InstrFormats.td
+++ lib/Target/Mips/MicroMips32r6InstrFormats.td
@@ -391,7 +391,7 @@
let Inst{15-0} = offset;
}
-class POOL32C_STORE_EVA_FM_MMR6<bits<3> funct> {
+class POOL32C_STORE_EVA_FM_MMR6<bits<4> funct, bits<3> fmt> {
bits<5> rt;
bits<21> addr;
bits<5> base = addr{20-16};
@@ -402,12 +402,12 @@
let Inst{31-26} = 0b011000;
let Inst{25-21} = rt;
let Inst{20-16} = base;
- let Inst{15-12} = 0b1010;
- let Inst{11-9} = funct;
+ let Inst{15-12} = funct;
+ let Inst{11-9} = fmt;
let Inst{8-0} = offset;
}
-class LOAD_WORD_EVA_FM_MMR6<bits<3> funct> {
+class POOL32C_LOAD_WORD_EVA_FM_MMR6<bits<4> funct, bits<3> fmt> {
bits<5> rt;
bits<21> addr;
bits<5> base = addr{20-16};
@@ -418,8 +418,8 @@
let Inst{31-26} = 0b011000;
let Inst{25-21} = rt;
let Inst{20-16} = base;
- let Inst{15-12} = 0b0110;
- let Inst{11-9} = funct;
+ let Inst{15-12} = funct;
+ let Inst{11-9} = fmt;
let Inst{8-0} = offset;
}
Index: lib/Target/Mips/MicroMips32r6InstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -126,12 +126,12 @@
class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
-class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
-class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
+class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b1010, 0b100>;
+class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b1010, 0b110>;
class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
-class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
-class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
-class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
+class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b1010, 0b101>;
+class LLE_MMR6_ENC : POOL32C_LOAD_WORD_EVA_FM_MMR6<0b0110, 0b110>;
+class LWE_MMR6_ENC : POOL32C_LOAD_WORD_EVA_FM_MMR6<0b0110, 0b111>;
class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>;
@@ -168,6 +168,10 @@
class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
+class LLX_MMR6_ENC : POOL32C_LOAD_WORD_EVA_FM_MMR6<0b0001, 0b000>;
+class LLXE_MMR6_ENC : POOL32C_LOAD_WORD_EVA_FM_MMR6<0b0110, 0b010>;
+class SCX_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b1001, 0b000>;
+class SCXE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b1010, 0b000>;
class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
RegisterOperand GPROpnd>
@@ -782,28 +786,39 @@
}
class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
-class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
- : MMR6Arch<instr_asm>, MipsR6Inst {
+class STORE_EVA_MMR6_DESC_BASE<string opstr, RegisterOperand RO,
+ Operand ImmOpnd>
+ : MMR6Arch<opstr>, MipsR6Inst {
dag OutOperandList = (outs);
- dag InOperandList = (ins RO:$rt, mem_mm_9:$addr);
- string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
+ dag InOperandList = (ins RO:$rt, ImmOpnd:$addr);
+ string AsmString = !strconcat(opstr, "\t$rt, $addr");
string DecoderMethod = "DecodeStoreEvaOpMM";
bit mayStore = 1;
}
-class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
-class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
+class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd, mem_simm9gpr>;
+class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd, mem_simm9gpr>;
+class SCX_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"scx", GPR32Opnd, mem_simm9gpr>;
+class SCXE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"scxe", GPR32Opnd,
+ mem_simm9gpr>;
class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
-class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
-class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
- MMR6Arch<instr_asm>, MipsR6Inst {
+class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd, mem_simm9gpr>;
+class LOAD_WORD_EVA_MMR6_DESC_BASE<string opstr, RegisterOperand RO,
+ Operand ImmOpnd>
+ : MMR6Arch<opstr>, MipsR6Inst {
dag OutOperandList = (outs RO:$rt);
- dag InOperandList = (ins mem_mm_12:$addr);
- string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
+ dag InOperandList = (ins ImmOpnd:$addr);
+ string AsmString = !strconcat(opstr, "\t$rt, $addr");
string DecoderMethod = "DecodeMemMMImm9";
bit mayLoad = 1;
}
-class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
-class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
+class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd,
+ mem_simm9gpr>;
+class LLX_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"llx", GPR32Opnd,
+ mem_simm9gpr>;
+class LLXE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"llxe", GPR32Opnd,
+ mem_simm9gpr>;
+class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd,
+ mem_simm9gpr>;
class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
MMR6Arch<"addu16">;
class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
@@ -1142,9 +1157,13 @@
def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
+def SCX_MMR6 : R6MMR6Rel, SCX_MMR6_DESC, SCX_MMR6_ENC, ISA_MICROMIPS32R6;
+def SCXE_MMR6 : R6MMR6Rel, SCXE_MMR6_DESC, SCXE_MMR6_ENC, ISA_MICROMIPS32R6;
def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
+def LLX_MMR6 : R6MMR6Rel, LLX_MMR6_DESC, LLX_MMR6_ENC, ISA_MICROMIPS32R6;
+def LLXE_MMR6 : R6MMR6Rel, LLXE_MMR6_DESC, LLXE_MMR6_ENC, ISA_MICROMIPS32R6;
def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
Index: lib/Target/Mips/MicroMipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrInfo.td
+++ lib/Target/Mips/MicroMipsInstrInfo.td
@@ -264,7 +264,7 @@
}
class LLEBaseMM<string opstr, RegisterOperand RO> :
- InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
+ InstSE<(outs RO:$rt), (ins mem_simm9gpr:$addr),
!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
let DecoderMethod = "DecodeMemMMImm9";
let mayLoad = 1;
@@ -279,7 +279,7 @@
}
class SCEBaseMM<string opstr, RegisterOperand RO> :
- InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
+ InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9gpr:$addr),
!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
let DecoderMethod = "DecodeMemMMImm9";
let mayStore = 1;
@@ -751,9 +751,12 @@
def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
def LHE_MM : Load<"lhe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
def LHuE_MM : Load<"lhue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
- def LWE_MM : Load<"lwe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
- def SBE_MM : Store<"sbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
- def SHE_MM : Store<"she", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
+ def LWE_MM : LoadMemory<"lwe", GPR32Opnd, mem_simm9gpr>,
+ POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
+ def SBE_MM : StoreMemory<"sbe", GPR32Opnd, mem_simm9gpr>,
+ POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
+ def SHE_MM : StoreMemory<"she", GPR32Opnd, mem_simm9gpr>,
+ POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9gpr>,
POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
}
Index: lib/Target/Mips/MipsEVAInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsEVAInstrInfo.td
+++ lib/Target/Mips/MipsEVAInstrInfo.td
@@ -51,9 +51,10 @@
//===----------------------------------------------------------------------===//
// Memory Load/Store EVA descriptions
-class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
+class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+ Operand ImmOpnd> {
dag OutOperandList = (outs GPROpnd:$rt);
- dag InOperandList = (ins mem_simm9:$addr);
+ dag InOperandList = (ins ImmOpnd:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
string DecoderMethod = "DecodeMemEVA";
@@ -61,25 +62,26 @@
bit mayLoad = 1;
}
-class LBE_DESC : LOAD_EVA_DESC_BASE<"lbe", GPR32Opnd>;
-class LBuE_DESC : LOAD_EVA_DESC_BASE<"lbue", GPR32Opnd>;
-class LHE_DESC : LOAD_EVA_DESC_BASE<"lhe", GPR32Opnd>;
-class LHuE_DESC : LOAD_EVA_DESC_BASE<"lhue", GPR32Opnd>;
-class LWE_DESC : LOAD_EVA_DESC_BASE<"lwe", GPR32Opnd>;
+class LBE_DESC : LOAD_EVA_DESC_BASE<"lbe", GPR32Opnd, mem_simm9>;
+class LBuE_DESC : LOAD_EVA_DESC_BASE<"lbue", GPR32Opnd, mem_simm9>;
+class LHE_DESC : LOAD_EVA_DESC_BASE<"lhe", GPR32Opnd, mem_simm9>;
+class LHuE_DESC : LOAD_EVA_DESC_BASE<"lhue", GPR32Opnd, mem_simm9>;
+class LWE_DESC : LOAD_EVA_DESC_BASE<"lwe", GPR32Opnd, mem_simm9gpr>;
class STORE_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+ Operand ImmOpnd,
SDPatternOperator OpNode = null_frag> {
dag OutOperandList = (outs);
- dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
+ dag InOperandList = (ins GPROpnd:$rt, ImmOpnd:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
string DecoderMethod = "DecodeMemEVA";
bit mayStore = 1;
}
-class SBE_DESC : STORE_EVA_DESC_BASE<"sbe", GPR32Opnd>;
-class SHE_DESC : STORE_EVA_DESC_BASE<"she", GPR32Opnd>;
-class SWE_DESC : STORE_EVA_DESC_BASE<"swe", GPR32Opnd>;
+class SBE_DESC : STORE_EVA_DESC_BASE<"sbe", GPR32Opnd, mem_simm9gpr>;
+class SHE_DESC : STORE_EVA_DESC_BASE<"she", GPR32Opnd, mem_simm9gpr>;
+class SWE_DESC : STORE_EVA_DESC_BASE<"swe", GPR32Opnd, mem_simm9>;
// Load/Store Left/Right EVA descriptions
class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
@@ -109,7 +111,7 @@
// Load-linked EVA, Store-conditional EVA descriptions
class LLE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
dag OutOperandList = (outs GPROpnd:$rt);
- dag InOperandList = (ins mem_simm9:$addr);
+ dag InOperandList = (ins mem_simm9gpr:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
bit mayLoad = 1;
@@ -120,7 +122,7 @@
class SCE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
dag OutOperandList = (outs GPROpnd:$dst);
- dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
+ dag InOperandList = (ins GPROpnd:$rt, mem_simm9gpr:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
bit mayStore = 1;
Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -892,15 +892,21 @@
}
// Memory Load/Store
-class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
- InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
- InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
+class LoadMemory<string opstr, DAGOperand RO, DAGOperand MO,
+ SDPatternOperator OpNode = null_frag,
+ InstrItinClass Itin = NoItinerary,
+ ComplexPattern Addr = addr> :
+ InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
[(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
let DecoderMethod = "DecodeMem";
let canFoldAsLoad = 1;
let mayLoad = 1;
}
+class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
+ InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
+ LoadMemory<opstr, RO, mem, OpNode, Itin, Addr>;
+
class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
SDPatternOperator OpNode = null_frag,
InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
Index: test/MC/Disassembler/Mips/micromips32r6/valid.txt
===================================================================
--- test/MC/Disassembler/Mips/micromips32r6/valid.txt
+++ test/MC/Disassembler/Mips/micromips32r6/valid.txt
@@ -256,3 +256,7 @@
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
0x00 0x00 0x47 0x7c # CHECK: di
0x00 0x0f 0x47 0x7c # CHECK: di $15
+0x60 0x85 0x10 0x06 # CHECK: llx $4, 6($5)
+0x60 0x85 0x64 0x06 # CHECK: llxe $4, 6($5)
+0x60 0x85 0x90 0x06 # CHECK: scx $4, 6($5)
+0x60 0x85 0xa0 0x06 # CHECK: scxe $4, 6($5)
Index: test/MC/Disassembler/Mips/micromips64r6/valid.txt
===================================================================
--- test/MC/Disassembler/Mips/micromips64r6/valid.txt
+++ test/MC/Disassembler/Mips/micromips64r6/valid.txt
@@ -169,3 +169,7 @@
0x00 0x00 0xe3 0x7c # CHECK: deret
0x00 0x00 0x47 0x7c # CHECK: di
0x00 0x0f 0x47 0x7c # CHECK: di $15
+0x60 0x85 0x10 0x06 # CHECK: llx $4, 6($5)
+0x60 0x85 0x64 0x06 # CHECK: llxe $4, 6($5)
+0x60 0x85 0x90 0x06 # CHECK: scx $4, 6($5)
+0x60 0x85 0xa0 0x06 # CHECK: scxe $4, 6($5)
Index: test/MC/Mips/eva/invalid.s
===================================================================
--- test/MC/Mips/eva/invalid.s
+++ test/MC/Mips/eva/invalid.s
@@ -9,3 +9,8 @@
cachee 32, 255($7) # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
prefe -1, 255($7) # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
prefe 32, 255($7) # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+ lle $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ lwe $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ sbe $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ sce $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ she $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Index: test/MC/Mips/eva/invalid_R6.s
===================================================================
--- test/MC/Mips/eva/invalid_R6.s
+++ test/MC/Mips/eva/invalid_R6.s
@@ -18,3 +18,8 @@
swre $s4,255($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swre $s4,-256($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swre $s2,86($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ lle $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ lwe $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ sbe $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ sce $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ she $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Index: test/MC/Mips/micromips/invalid.s
===================================================================
--- test/MC/Mips/micromips/invalid.s
+++ test/MC/Mips/micromips/invalid.s
@@ -33,3 +33,8 @@
sra $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
srl $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
srl $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+ lle $4, 512($5) # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+ lwe $4, 512($5) # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+ sbe $4, 512($5) # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+ sce $4, 512($5) # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+ she $4, 512($5) # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
Index: test/MC/Mips/micromips32r6/invalid.s
===================================================================
--- test/MC/Mips/micromips32r6/invalid.s
+++ test/MC/Mips/micromips32r6/invalid.s
@@ -107,3 +107,12 @@
swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ lle $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ llx $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ llxe $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ lwe $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ sbe $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ sce $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ scx $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ scxe $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ she $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Index: test/MC/Mips/micromips32r6/valid.s
===================================================================
--- test/MC/Mips/micromips32r6/valid.s
+++ test/MC/Mips/micromips32r6/valid.s
@@ -250,3 +250,7 @@
class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60]
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60]
deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c]
+ llx $4, 6($5) # CHECK: llx $4, 6($5) # encoding: [0x60,0x85,0x10,0x06]
+ llxe $4, 6($5) # CHECK: llxe $4, 6($5) # encoding: [0x60,0x85,0x64,0x06]
+ scx $4, 6($5) # CHECK: scx $4, 6($5) # encoding: [0x60,0x85,0x90,0x06]
+ scxe $4, 6($5) # CHECK: scxe $4, 6($5) # encoding: [0x60,0x85,0xa0,0x06]
Index: test/MC/Mips/micromips64r6/invalid.s
===================================================================
--- test/MC/Mips/micromips64r6/invalid.s
+++ test/MC/Mips/micromips64r6/invalid.s
@@ -131,3 +131,12 @@
swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ lle $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ llx $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ llxe $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ lwe $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ sbe $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ sce $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ scx $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ scxe $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ she $4, 512($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Index: test/MC/Mips/micromips64r6/valid.s
===================================================================
--- test/MC/Mips/micromips64r6/valid.s
+++ test/MC/Mips/micromips64r6/valid.s
@@ -150,5 +150,9 @@
di # CHECK: di # encoding: [0x00,0x00,0x47,0x7c]
di $0 # CHECK: di # encoding: [0x00,0x00,0x47,0x7c]
di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c]
+ llx $4, 6($5) # CHECK: llx $4, 6($5) # encoding: [0x60,0x85,0x10,0x06]
+ llxe $4, 6($5) # CHECK: llxe $4, 6($5) # encoding: [0x60,0x85,0x64,0x06]
+ scx $4, 6($5) # CHECK: scx $4, 6($5) # encoding: [0x60,0x85,0x90,0x06]
+ scxe $4, 6($5) # CHECK: scxe $4, 6($5) # encoding: [0x60,0x85,0xa0,0x06]
1: