Index: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -2946,18 +2946,17 @@
                               const bool Signed) {
   MipsTargetStreamer &TOut = getTargetStreamer();
 
-  if (hasMips32r6()) {
-    Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
-    return false;
-  }
-
   warnIfNoMacro(IDLoc);
 
-  const MCOperand &RsRegOp = Inst.getOperand(0);
+  const MCOperand &RdRegOp = Inst.getOperand(0);
+  assert(RdRegOp.isReg() && "expected register operand kind");
+  unsigned RdReg = RdRegOp.getReg();
+
+  const MCOperand &RsRegOp = Inst.getOperand(1);
   assert(RsRegOp.isReg() && "expected register operand kind");
   unsigned RsReg = RsRegOp.getReg();
 
-  const MCOperand &RtRegOp = Inst.getOperand(1);
+  const MCOperand &RtRegOp = Inst.getOperand(2);
   assert(RtRegOp.isReg() && "expected register operand kind");
   unsigned RtReg = RtRegOp.getReg();
   unsigned DivOp;
@@ -3026,7 +3025,7 @@
     TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
 
   if (!Signed) {
-    TOut.emitR(Mips::MFLO, RsReg, IDLoc, STI);
+    TOut.emitR(Mips::MFLO, RdReg, IDLoc, STI);
     return false;
   }
 
@@ -3054,7 +3053,7 @@
     TOut.emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, STI);
     TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI);
   }
-  TOut.emitR(Mips::MFLO, RsReg, IDLoc, STI);
+  TOut.emitR(Mips::MFLO, RdReg, IDLoc, STI);
   return false;
 }
 
Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
@@ -2358,17 +2358,34 @@
 // Once the tablegen-erated errors are made better, this needs to be fixed and
 // predicates needs to be restored.
 
-def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
-                                  "div\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
-
-def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
-                                  "divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
-
-def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
-                                   "ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
-
-def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
-                                   "ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
+def SDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+                                  (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+                                  "div\t$rd, $rs, $rt">,
+                ISA_MIPS1_NOT_32R6_64R6;
+def UDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+                                  (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+                                  "divu\t$rd, $rs, $rt">,
+                ISA_MIPS1_NOT_32R6_64R6;
+def : MipsInstAlias<"div $rt, $rs", (SDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
+                                               GPR32Opnd:$rs), 0>,
+      ISA_MIPS1_NOT_32R6_64R6;
+def : MipsInstAlias<"divu $rt, $rs", (UDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
+                                                GPR32Opnd:$rs), 0>,
+      ISA_MIPS1_NOT_32R6_64R6;
+def DSDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+                                   (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+                                   "ddiv\t$rd, $rs, $rt">,
+                 ISA_MIPS64_NOT_64R6;
+def DUDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+                                   (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+                                   "ddivu\t$rd, $rs, $rt">,
+                 ISA_MIPS64_NOT_64R6;
+def : MipsInstAlias<"ddiv $rt, $rs", (DSDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
+                                                 GPR32Opnd:$rs), 0>,
+      ISA_MIPS64_NOT_64R6;
+def : MipsInstAlias<"ddivu $rt, $rs", (DUDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
+                                                  GPR32Opnd:$rs), 0>,
+      ISA_MIPS64_NOT_64R6;
 
 def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
                             "ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
Index: llvm/trunk/test/MC/Mips/macro-ddiv-bad.s
===================================================================
--- llvm/trunk/test/MC/Mips/macro-ddiv-bad.s
+++ llvm/trunk/test/MC/Mips/macro-ddiv-bad.s
@@ -1,18 +1,18 @@
 # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \
-# RUN: FileCheck %s --check-prefix=R6
+# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
+# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
+# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
 # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \
-# RUN: FileCheck %s --check-prefix=R6
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
-# RUN: FileCheck %s --check-prefix=NOT-R6
+# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
 # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \
-# RUN: FileCheck %s --check-prefix=NOT-R6
+# RUN: FileCheck %s --check-prefix=MIPS64-NOT-R6
 
   .text
-  ddiv $25, $11
-  # R6: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  ddivu $25, $11
+  # MIPS32-OR-R6: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
 
-  ddiv $25, $0
-  # NOT-R6: :[[@LINE-1]]:3: warning: division by zero
+  ddivu $25, $0
+  # MIPS64-NOT-R6: :[[@LINE-1]]:3: warning: division by zero
 
-  ddiv $0,$0
-  # NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero
+  ddivu $0,$0
+  # MIPS64-NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero
Index: llvm/trunk/test/MC/Mips/macro-ddiv.s
===================================================================
--- llvm/trunk/test/MC/Mips/macro-ddiv.s
+++ llvm/trunk/test/MC/Mips/macro-ddiv.s
@@ -48,6 +48,28 @@
   ddiv $0,$0
 # CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
 
+  ddiv  $4,$5,$6
+# CHECK-NOTRAP: bne $6, $zero, 8          # encoding: [0x14,0xc0,0x00,0x02]
+# CHECK-NOTRAP: ddiv $zero, $5, $6        # encoding: [0x00,0xa6,0x00,0x1e]
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: addiu $1, $zero, -1       # encoding: [0x24,0x01,0xff,0xff]
+# CHECK-NOTRAP: bne $6, $1, 20            # encoding: [0x14,0xc1,0x00,0x05]
+# CHECK-NOTRAP: addiu $1, $zero, 1        # encoding: [0x24,0x01,0x00,0x01]
+# CHECK-NOTRAP: dsll32 $1, $1, 31         # encoding: [0x00,0x01,0x0f,0xfc]
+# CHECK-NOTRAP: bne $5, $1, 8             # encoding: [0x14,0xa1,0x00,0x02]
+# CHECK-NOTRAP: sll $zero, $zero, 0       # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-NOTRAP: break 6                   # encoding: [0x00,0x06,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                   # encoding: [0x00,0x00,0x20,0x12]
+
+  ddiv  $4,$5,$0
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+
+  ddiv  $4,$0,$0
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+
+  ddiv $0, $4, $5
+# CHECK-NOTRAP: ddiv $zero, $4, $5        # encoding: [0x00,0x85,0x00,0x1e]
+
   ddiv $25,$11
 # CHECK-TRAP: teq $11, $zero, 7           # encoding: [0x01,0x60,0x01,0xf4]
 # CHECK-TRAP: ddiv $zero, $25, $11        # encoding: [0x03,0x2b,0x00,0x1e]
@@ -83,3 +105,22 @@
 
   ddiv $0,$0
 # CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+
+  ddiv  $4,$5,$6
+# CHECK-TRAP: teq $6, $zero, 7            # encoding: [0x00,0xc0,0x01,0xf4]
+# CHECK-TRAP: ddiv $zero, $5, $6          # encoding: [0x00,0xa6,0x00,0x1e]
+# CHECK-TRAP: addiu $1, $zero, -1         # encoding: [0x24,0x01,0xff,0xff]
+# CHECK-TRAP: bne $6, $1, 12              # encoding: [0x14,0xc1,0x00,0x03]
+# CHECK-TRAP: addiu $1, $zero, 1          # encoding: [0x24,0x01,0x00,0x01]
+# CHECK-TRAP: dsll32 $1, $1, 31           # encoding: [0x00,0x01,0x0f,0xfc]
+# CHECK-TRAP: teq $5, $1, 6               # encoding: [0x00,0xa1,0x01,0xb4]
+# CHECK-TRAP: mflo $4                     # encoding: [0x00,0x00,0x20,0x12]
+
+  ddiv  $4,$5,$0
+# CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+
+  ddiv  $4,$0,$0
+# CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+
+  ddiv $0, $4, $5
+# CHECK-TRAP: ddiv $zero, $4, $5          # encoding: [0x00,0x85,0x00,0x1e]
Index: llvm/trunk/test/MC/Mips/macro-ddivu-bad.s
===================================================================
--- llvm/trunk/test/MC/Mips/macro-ddivu-bad.s
+++ llvm/trunk/test/MC/Mips/macro-ddivu-bad.s
@@ -1,18 +1,18 @@
 # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \
-# RUN: FileCheck %s --check-prefix=R6
+# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
+# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
+# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
 # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \
-# RUN: FileCheck %s --check-prefix=R6
-# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
-# RUN: FileCheck %s --check-prefix=NOT-R6
+# RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
 # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \
-# RUN: FileCheck %s --check-prefix=NOT-R6
+# RUN: FileCheck %s --check-prefix=MIPS64-NOT-R6
 
   .text
   ddivu $25, $11
-  # R6: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  # MIPS32-OR-R6: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
 
   ddivu $25, $0
-  # NOT-R6: :[[@LINE-1]]:3: warning: division by zero
+  # MIPS64-NOT-R6: :[[@LINE-1]]:3: warning: division by zero
 
   ddivu $0,$0
-  # NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero
+  # MIPS64-NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero
Index: llvm/trunk/test/MC/Mips/macro-ddivu.s
===================================================================
--- llvm/trunk/test/MC/Mips/macro-ddivu.s
+++ llvm/trunk/test/MC/Mips/macro-ddivu.s
@@ -33,6 +33,27 @@
 # CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
 # CHECK-NOTRAP: mflo $zero                # encoding: [0x00,0x00,0x00,0x12]
 
+  ddivu  $4,$5,$6
+# CHECK-NOTRAP: bne $6, $zero, 8          # encoding: [0x14,0xc0,0x00,0x02]
+# CHECK-NOTRAP: ddivu $zero, $5, $6       # encoding: [0x00,0xa6,0x00,0x1f]
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                   # encoding: [0x00,0x00,0x20,0x12]
+
+  ddivu $4,$5,$0
+# CHECK-NOTRAP: bne $zero, $zero, 8       # encoding: [0x14,0x00,0x00,0x02]
+# CHECK-NOTRAP: ddivu $zero, $5, $zero    # encoding: [0x00,0xa0,0x00,0x1f]
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                   # encoding: [0x00,0x00,0x20,0x12]
+
+  ddivu $4,$0,$0
+# CHECK-NOTRAP: bne $zero, $zero, 8       # encoding: [0x14,0x00,0x00,0x02]
+# CHECK-NOTRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                   # encoding: [0x00,0x00,0x20,0x12]
+
+  ddivu $0, $4, $5
+# CHECK-NOTRAP: ddivu $zero, $4, $5       # encoding: [0x00,0x85,0x00,0x1f]
+
   ddivu $25, $11
 # CHECK-TRAP: teq $11, $zero, 7           # encoding: [0x01,0x60,0x01,0xf4]
 # CHECK-TRAP: ddivu $zero, $25, $11       # encoding: [0x03,0x2b,0x00,0x1f]
@@ -57,3 +78,21 @@
 # CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
 # CHECK-TRAP: ddivu $zero, $zero, $zero   # encoding: [0x00,0x00,0x00,0x1f]
 # CHECK-TRAP: mflo $zero                  # encoding: [0x00,0x00,0x00,0x12]
+
+  ddivu  $4,$5,$6
+# CHECK-TRAP: teq $6, $zero, 7            # encoding: [0x00,0xc0,0x01,0xf4]
+# CHECK-TRAP: ddivu $zero, $5, $6         # encoding: [0x00,0xa6,0x00,0x1f]
+# CHECK-TRAP: mflo $4                     # encoding: [0x00,0x00,0x20,0x12]
+
+  ddivu $4,$5,$0
+# CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+# CHECK-TRAP: ddivu $zero, $5, $zero      # encoding: [0x00,0xa0,0x00,0x1f]
+# CHECK-TRAP: mflo $4                     # encoding: [0x00,0x00,0x20,0x12]
+
+  ddivu $4,$0,$0
+# CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+# CHECK-TRAP: ddivu $zero, $zero, $zero   # encoding: [0x00,0x00,0x00,0x1f]
+# CHECK-TRAP: mflo $4                     # encoding: [0x00,0x00,0x20,0x12]
+
+  ddivu $0, $4, $5
+# CHECK-TRAP: ddivu $zero, $4, $5         # encoding: [0x00,0x85,0x00,0x1f]
Index: llvm/trunk/test/MC/Mips/macro-div-bad.s
===================================================================
--- llvm/trunk/test/MC/Mips/macro-div-bad.s
+++ llvm/trunk/test/MC/Mips/macro-div-bad.s
@@ -9,7 +9,7 @@
 
   .text
   div $25, $11
-  # R6: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
 
   div $25, $0
   # NOT-R6: :[[@LINE-1]]:3: warning: division by zero
Index: llvm/trunk/test/MC/Mips/macro-div.s
===================================================================
--- llvm/trunk/test/MC/Mips/macro-div.s
+++ llvm/trunk/test/MC/Mips/macro-div.s
@@ -36,6 +36,27 @@
   div $0,$0
 # CHECK-NOTRAP: div $zero, $zero, $zero   # encoding: [0x00,0x00,0x00,0x1a]
 
+  div  $4,$5,$6
+# CHECK-NOTRAP: bnez $6, 8                # encoding: [0x14,0xc0,0x00,0x02]
+# CHECK-NOTRAP: div $zero, $5, $6         # encoding: [0x00,0xa6,0x00,0x1a]
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: addiu $1, $zero, -1       # encoding: [0x24,0x01,0xff,0xff]
+# CHECK-NOTRAP: bne $6, $1, 16            # encoding: [0x14,0xc1,0x00,0x04]
+# CHECK-NOTRAP: lui $1, 32768             # encoding: [0x3c,0x01,0x80,0x00]
+# CHECK-NOTRAP: bne $5, $1, 8             # encoding: [0x14,0xa1,0x00,0x02]
+# CHECK-NOTRAP: nop                       # encoding: [0x00,0x00,0x00,0x00]
+# CHECK-NOTRAP: break 6                   # encoding: [0x00,0x06,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                   # encoding: [0x00,0x00,0x20,0x12]
+
+  div  $4,$5,$0
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+
+  div  $4,$0,$0
+# CHECK-NOTRAP: break 7                   # encoding: [0x00,0x07,0x00,0x0d]
+
+  div $0, $4, $5
+# CHECK-NOTRAP: div $zero, $4, $5         # encoding: [0x00,0x85,0x00,0x1a]
+
   div $25, $11
 # CHECK-TRAP: teq $11, $zero, 7           # encoding: [0x01,0x60,0x01,0xf4]
 # CHECK-TRAP: div $zero, $25, $11         # encoding: [0x03,0x2b,0x00,0x1a]
@@ -62,3 +83,21 @@
 
   div $0,$0
 # CHECK-TRAP: div $zero, $zero, $zero     # encoding: [0x00,0x00,0x00,0x1a]
+
+  div  $4,$5,$6
+# CHECK-TRAP: teq $6, $zero, 7            # encoding: [0x00,0xc0,0x01,0xf4]
+# CHECK-TRAP: div $zero, $5, $6           # encoding: [0x00,0xa6,0x00,0x1a]
+# CHECK-TRAP: addiu $1, $zero, -1         # encoding: [0x24,0x01,0xff,0xff]
+# CHECK-TRAP: bne $6, $1, 8               # encoding: [0x14,0xc1,0x00,0x02]
+# CHECK-TRAP: lui $1, 32768               # encoding: [0x3c,0x01,0x80,0x00]
+# CHECK-TRAP: teq $5, $1, 6               # encoding: [0x00,0xa1,0x01,0xb4]
+# CHECK-TRAP: mflo  $4                    # encoding: [0x00,0x00,0x20,0x12]
+
+  div  $4,$5,$0
+# CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+
+  div  $4,$0,$0
+# CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
+
+  div $0, $4, $5
+# CHECK-TRAP: div $zero, $4, $5           # encoding: [0x00,0x85,0x00,0x1a]
\ No newline at end of file
Index: llvm/trunk/test/MC/Mips/macro-divu-bad.s
===================================================================
--- llvm/trunk/test/MC/Mips/macro-divu-bad.s
+++ llvm/trunk/test/MC/Mips/macro-divu-bad.s
@@ -9,7 +9,7 @@
 
   .text
   divu $25, $11
-  # R6: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
 
   divu $25, $0
   # NOT-R6: :[[@LINE-1]]:3: warning: division by zero
Index: llvm/trunk/test/MC/Mips/macro-divu.s
===================================================================
--- llvm/trunk/test/MC/Mips/macro-divu.s
+++ llvm/trunk/test/MC/Mips/macro-divu.s
@@ -27,23 +27,62 @@
   divu $0,$0
 # CHECK-NOTRAP: divu $zero, $zero, $zero  # encoding: [0x00,0x00,0x00,0x1b]
 
-  divu $25, $11
-# CHECK-TRAP: teq	$11, $zero, 7           # encoding: [0x01,0x60,0x01,0xf4]
-# CHECK-TRAP: divu $zero, $25, $11        # encoding: [0x03,0x2b,0x00,0x1b]
-# CHECK-TRAP: mflo $25                    # encoding: [0x00,0x00,0xc8,0x12]
-
-  divu $24,$12
-# CHECK-TRAP: teq $12, $zero, 7           # encoding: [0x01,0x80,0x01,0xf4]
-# CHECK-TRAP: divu $zero, $24, $12        # encoding: [0x03,0x0c,0x00,0x1b]
-# CHECK-TRAP: mflo $24                    # encoding: [0x00,0x00,0xc0,0x12]
+   divu $4,$5,$6
+# CHECK-NOTRAP: bnez $6, 8                 # encoding: [0x14,0xc0,0x00,0x02]
+# CHECK-NOTRAP: divu $zero, $5, $6         # encoding: [0x00,0xa6,0x00,0x1b]
+# CHECK-NOTRAP: break 7                    # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                    # encoding: [0x00,0x00,0x20,0x12]
+
+   divu $4,$5,$0
+# CHECK-NOTRAP: bnez $zero, 8              # encoding: [0x14,0x00,0x00,0x02]
+# CHECK-NOTRAP: divu $zero, $5, $zero      # encoding: [0x00,0xa0,0x00,0x1b]
+# CHECK-NOTRAP: break 7                    # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                    # encoding: [0x00,0x00,0x20,0x12]
+
+   divu $4,$0,$0
+# CHECK-NOTRAP: bnez $zero, 8              # encoding: [0x14,0x00,0x00,0x02]
+# CHECK-NOTRAP: divu $zero, $zero, $zero   # encoding: [0x00,0x00,0x00,0x1b]
+# CHECK-NOTRAP: break 7                    # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK-NOTRAP: mflo $4                    # encoding: [0x00,0x00,0x20,0x12]
+
+  divu $0, $4, $5
+# CHECK-NOTRAP: divu $zero, $4, $5         # encoding: [0x00,0x85,0x00,0x1b]
+
+   divu $25, $11
+# CHECK-TRAP: teq $11, $zero, 7            # encoding: [0x01,0x60,0x01,0xf4]
+# CHECK-TRAP: divu $zero, $25, $11         # encoding: [0x03,0x2b,0x00,0x1b]
+# CHECK-TRAP: mflo $25                     # encoding: [0x00,0x00,0xc8,0x12]
+
+   divu $24,$12
+# CHECK-TRAP: teq $12, $zero, 7            # encoding: [0x01,0x80,0x01,0xf4]
+# CHECK-TRAP: divu $zero, $24, $12         # encoding: [0x03,0x0c,0x00,0x1b]
+# CHECK-TRAP: mflo $24                     # encoding: [0x00,0x00,0xc0,0x12]
 
   divu $25,$0
-# CHECK-TRAP: teq $zero, $zero, 7         # encoding: [0x00,0x00,0x01,0xf4]
-# CHECK-TRAP: divu $zero, $25, $zero      # encoding: [0x03,0x20,0x00,0x1b]
-# CHECK-TRAP: mflo $25                    # encoding: [0x00,0x00,0xc8,0x12]
+# CHECK-TRAP: teq $zero, $zero, 7          # encoding: [0x00,0x00,0x01,0xf4]
+# CHECK-TRAP: divu $zero, $25, $zero       # encoding: [0x03,0x20,0x00,0x1b]
+# CHECK-TRAP: mflo $25                     # encoding: [0x00,0x00,0xc8,0x12]
 
   divu $0,$9
-# CHECK-TRAP: divu $zero, $zero, $9       # encoding: [0x00,0x09,0x00,0x1b]
+# CHECK-TRAP: divu $zero, $zero, $9        # encoding: [0x00,0x09,0x00,0x1b]
 
   divu $0,$0
-# CHECK-TRAP: divu $zero, $zero, $zero    # encoding: [0x00,0x00,0x00,0x1b]
+# CHECK-TRAP: divu $zero, $zero, $zero     # encoding: [0x00,0x00,0x00,0x1b]
+
+  divu $4,$5,$6
+# CHECK-TRAP: teq $6, $zero, 7             # encoding: [0x00,0xc0,0x01,0xf4]
+# CHECK-TRAP: divu $zero, $5, $6           # encoding: [0x00,0xa6,0x00,0x1b]
+# CHECK-TRAP: mflo $4                      # encoding: [0x00,0x00,0x20,0x12]
+
+  divu $4,$5,$0
+# CHECK-TRAP: teq $zero, $zero, 7          # encoding: [0x00,0x00,0x01,0xf4]
+# CHECK-TRAP: divu $zero, $5, $zero        # encoding: [0x00,0xa0,0x00,0x1b]
+# CHECK-TRAP: mflo $4                      # encoding: [0x00,0x00,0x20,0x12]
+
+  divu $4,$0,$0
+# CHECK-TRAP: teq $zero, $zero, 7          # encoding: [0x00,0x00,0x01,0xf4]
+# CHECK-TRAP: divu $zero, $zero, $zero     # encoding: [0x00,0x00,0x00,0x1b]
+# CHECK-TRAP: mflo $4                      # encoding: [0x00,0x00,0x20,0x12]
+
+  divu $0, $4, $5
+# CHECK-TRAP: divu $zero, $4, $5           # encoding: [0x00,0x85,0x00,0x1b]
\ No newline at end of file