Index: lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
===================================================================
--- lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -454,9 +454,11 @@
   bool isU6ImmX2() const { return Kind == Immediate &&
                                   isUInt<6>(getImm()) &&
                                   (getImm() & 1) == 0; }
+  bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
   bool isU7ImmX4() const { return Kind == Immediate &&
                                   isUInt<7>(getImm()) &&
                                   (getImm() & 3) == 0; }
+  bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
   bool isU8ImmX8() const { return Kind == Immediate &&
                                   isUInt<8>(getImm()) &&
                                   (getImm() & 7) == 0; }
Index: lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
===================================================================
--- lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
+++ lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
@@ -55,6 +55,8 @@
   void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  void printU7ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU10ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printU12ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
Index: lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
===================================================================
--- lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
+++ lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
@@ -299,6 +299,20 @@
   O << (unsigned int)Value;
 }
 
+void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
+                                       raw_ostream &O) {
+  unsigned int Value = MI->getOperand(OpNo).getImm();
+  assert(Value <= 127 && "Invalid u7imm argument!");
+  O << (unsigned int)Value;
+}
+
+void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
+                                       raw_ostream &O) {
+  unsigned int Value = MI->getOperand(OpNo).getImm();
+  assert(Value <= 255 && "Invalid u8imm argument!");
+  O << (unsigned int)Value;
+}
+
 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
                                         raw_ostream &O) {
   unsigned short Value = MI->getOperand(OpNo).getImm();
Index: lib/Target/PowerPC/PPC.td
===================================================================
--- lib/Target/PowerPC/PPC.td
+++ lib/Target/PowerPC/PPC.td
@@ -124,6 +124,12 @@
 def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
                                         "Enable POWER8 vector instructions",
                                         [FeatureVSX, FeatureP8Altivec]>;
+def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
+                                        "Enable POWER9 Altivec instructions",
+                                        [FeatureP8Altivec]>;
+def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
+                                        "Enable POWER9 vector instructions",
+                                        [FeatureP8Vector, FeatureP9Altivec]>;
 def FeatureDirectMove :
   SubtargetFeature<"direct-move", "HasDirectMove", "true",
                    "Enable Power8 direct move instructions",
Index: lib/Target/PowerPC/PPCInstrFormats.td
===================================================================
--- lib/Target/PowerPC/PPCInstrFormats.td
+++ lib/Target/PowerPC/PPCInstrFormats.td
@@ -747,6 +747,44 @@
   let Inst{31}    = RC;
 }
 
+// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RC]
+class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
+                    string asmstr, InstrItinClass itin, list<dag> pattern>
+  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+  let A = xo2;
+}
+
+class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+                      string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<3> BF;
+  bits<7> DCMX;
+  bits<5> VB;
+
+  let Pattern = pattern;
+
+  let Inst{6-8}  = BF;
+  let Inst{9-15} = DCMX;
+  let Inst{16-20} = VB;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
+class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+                 string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bits<8> IMM8;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = XT{4-0};
+  let Inst{11-12} = 0;
+  let Inst{13-20} = IMM8;
+  let Inst{21-30} = xo;
+  let Inst{31}    = XT{5};
+}
+
 // XX*-Form (VSX)
 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 
               InstrItinClass itin, list<dag> pattern>
@@ -820,6 +858,95 @@
   let Inst{31}    = XT{5};
 }
 
+class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+                       string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bits<6> XB;
+  bits<5> UIM5;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = XT{4-0};
+  let Inst{11-15} = UIM5;
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-29} = xo;
+  let Inst{30}    = XB{5};
+  let Inst{31}    = XT{5};
+}
+
+// [PO T XO B XO BX /]
+class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
+                       string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<5> RT;
+  bits<6> XB;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = RT;
+  let Inst{11-15} = xo2;
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-29} = xo;
+  let Inst{30}    = XB{5};
+  let Inst{31}    = 0;
+}
+
+// [PO T XO B XO BX TX]
+class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
+                      string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bits<6> XB;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = XT{4-0};
+  let Inst{11-15} = xo2;
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-29} = xo;
+  let Inst{30}    = XB{5};
+  let Inst{31}    = XT{5};
+}
+
+class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+                      string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<3> BF;
+  bits<7> DCMX;
+  bits<6> XB;
+
+  let Pattern = pattern;
+
+  let Inst{6-8}  = BF;
+  let Inst{9-15} = DCMX;
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-29} = xo;
+  let Inst{30}    = XB{5};
+  let Inst{31}    = 0;
+}
+
+class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
+                        dag OOL, dag IOL, string asmstr, InstrItinClass itin,
+                        list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bits<7> DCMX;
+  bits<6> XB;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = XT{4-0};
+  let Inst{11-15} = DCMX{4-0};
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-24} = xo1;
+  let Inst{25}    = DCMX{5};
+  let Inst{26-28} = xo2;
+  let Inst{29}    = DCMX{6};
+  let Inst{30}    = XB{5};
+  let Inst{31}    = XT{5};
+}
+
 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 
               InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
Index: lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- lib/Target/PowerPC/PPCInstrInfo.td
+++ lib/Target/PowerPC/PPCInstrInfo.td
@@ -507,6 +507,24 @@
   let ParserMatchClass = PPCU6ImmAsmOperand;
   let DecoderMethod = "decodeUImmOperand<6>";
 }
+def PPCU7ImmAsmOperand : AsmOperandClass {
+  let Name = "U7Imm"; let PredicateMethod = "isU7Imm";
+  let RenderMethod = "addImmOperands";
+}
+def u7imm   : Operand<i32> {
+  let PrintMethod = "printU7ImmOperand";
+  let ParserMatchClass = PPCU7ImmAsmOperand;
+  let DecoderMethod = "decodeUImmOperand<7>";
+}
+def PPCU8ImmAsmOperand : AsmOperandClass {
+  let Name = "U8Imm"; let PredicateMethod = "isU8Imm";
+  let RenderMethod = "addImmOperands";
+}
+def u8imm   : Operand<i32> {
+  let PrintMethod = "printU8ImmOperand";
+  let ParserMatchClass = PPCU8ImmAsmOperand;
+  let DecoderMethod = "decodeUImmOperand<8>";
+}
 def PPCU10ImmAsmOperand : AsmOperandClass {
   let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
   let RenderMethod = "addImmOperands";
Index: lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- lib/Target/PowerPC/PPCInstrVSX.td
+++ lib/Target/PowerPC/PPCInstrVSX.td
@@ -1759,3 +1759,99 @@
   def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)),
             (i64 VectorExtractions.LE_VARIABLE_DWORD)>;
 } // IsLittleEndian, HasDirectMove
+
+// The following VSX instructions were introduced in Power ISA 3.0
+def HasP9Vector : Predicate<"PPCSubTarget->hasP9Vector()">;
+let Predicates = [HasP9Vector] in {
+
+  class X_VT5_XO5_VB5<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
+                      list<dag> pattern>
+    : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vrrc:$vB),
+                    !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
+
+  class XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
+                        list<dag> pattern>
+    : XX2_RD5_XO5_RS6<opcode, xo2, xo, (outs g8rc:$rT), (ins vsfrc:$XB),
+                      !strconcat(opc, " $rT, $XB"), IIC_VecFP, pattern>;
+
+  class XX2_XT6_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
+                      list<dag> pattern>
+    : XX2_RD6_XO5_RS6<opcode, xo2, xo, (outs vsfrc:$XT), (ins vsfrc:$XB),
+                      !strconcat(opc, " $XT, $XB"), IIC_VecFP, pattern>;
+
+  class XX3_XT5_XA5_XB5<bits<6> opcode, bits<8> xo, string opc,
+                        InstrItinClass itin, list<dag> pattern>
+    : XX3Form<opcode, xo, (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
+              !strconcat(opc, " $XT, $XA, $XB"), itin, pattern>;
+
+  // Insert Exponent DP/QP
+  def XSIEXPDP : XX1Form <60, 918, (outs vsfrc:$XT), (ins g8rc:$rA, g8rc:$rB),
+                          "xsiexpdp $XT, $rA, $rB", IIC_VecFP, []>;
+  def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$vT), (ins vrrc:$vA, vrrc:$vB),
+                          "xsiexpqp $vT, $vA, $vB", IIC_VecFP, []>;
+
+  // Extract Exponent/Significand DP/QP
+  def XSXEXPDP : XX2_RT5_XO5_XB6<60,  0, 347, "xsxexpdp", []>;
+  def XSXSIGDP : XX2_RT5_XO5_XB6<60,  1, 347, "xsxsigdp", []>;
+  def XSXEXPQP : X_VT5_XO5_VB5  <63,  2, 804, "xsxexpqp", []>;
+  def XSXSIGQP : X_VT5_XO5_VB5  <63, 18, 804, "xsxsigqp", []>;
+
+  // Vector Insert Word
+  def XXINSERTW   : XX2_RD6_UIM5_RS6<60, 181,
+                                 (outs vsfrc:$XT), (ins u5imm:$UIMM, vsfrc:$XB),
+                                 "xxinsertw $XT, $XB, $UIMM", IIC_VecFP, []>;
+
+  // Vector Extract Unsigned Word
+  def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165,
+                                 (outs vsfrc:$XT), (ins u5imm:$UIMM, vsfrc:$XB),
+                                 "xxextractuw $XT, $XB, $UIMM", IIC_VecFP, []>;
+
+  // Vector Insert Exponent DP/SP
+  def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", IIC_VecFP, []>;
+  def XVIEXPSP : XX3_XT5_XA5_XB5<60, 216, "xviexpsp", IIC_VecFP, []>;
+
+  // Vector Extract Exponent/Significand DP/SP
+  def XVXEXPDP : XX2_XT6_XO5_XB6<60,  0, 475, "xvxexpdp", []>;
+  def XVXEXPSP : XX2_XT6_XO5_XB6<60,  8, 475, "xvxexpsp", []>;
+  def XVXSIGDP : XX2_XT6_XO5_XB6<60,  1, 475, "xvxsigdp", []>;
+  def XVXSIGSP : XX2_XT6_XO5_XB6<60,  9, 475, "xvxsigsp", []>;
+
+  // Test Data Class SP/DP/QP
+  def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298,
+                              (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
+                              "xststdcsp $BF, $XB, $DCMX", IIC_VecFP, []>;
+  def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362,
+                              (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
+                              "xststdcdp $BF, $XB, $DCMX", IIC_VecFP, []>;
+  def XSTSTDCQP : X_BF3_DCMX7_RS5  <63, 708,
+                              (outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$vB),
+                              "xststdcqp $BF, $vB, $DCMX", IIC_VecFP, []>;
+
+  // Vector Test Data Class SP/DP
+  def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5,
+                              (outs vsfrc:$XT), (ins u7imm:$DCMX, vsfrc:$XB),
+                              "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP, []>;
+  def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5,
+                              (outs vsfrc:$XT), (ins u7imm:$DCMX, vsfrc:$XB),
+                              "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP, []>;
+
+  // Maximum/Minimum Type-C/Type-J DP
+  def XSMAXCDP : XX3_XT5_XA5_XB5<60, 128, "xsmaxcdp", IIC_VecFP, []>;
+  def XSMAXJDP : XX3_XT5_XA5_XB5<60, 144, "xsmaxjdp", IIC_VecFP, []>;
+  def XSMINCDP : XX3_XT5_XA5_XB5<60, 136, "xsmincdp", IIC_VecFP, []>;
+  def XSMINJDP : XX3_XT5_XA5_XB5<60, 152, "xsminjdp", IIC_VecFP, []>;
+
+  // Vector Byte-Reverse H/W/D/Q Word
+  def XXBRH : XX2_XT6_XO5_XB6<60,  7, 475, "xxbrh", []>;
+  def XXBRW : XX2_XT6_XO5_XB6<60, 15, 475, "xxbrw", []>;
+  def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", []>;
+  def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", []>;
+
+  // Vector Permute
+  def XXPERM  : XX3_XT5_XA5_XB5<60, 26, "xxperm" , IIC_VecFP, []>;
+  def XXPERMR : XX3_XT5_XA5_XB5<60, 58, "xxpermr", IIC_VecFP, []>;
+
+  // Vector Splat Immediate Byte
+  def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsfrc:$XT), (ins u8imm:$IMM8),
+                            "xxspltib $XT, $IMM8", IIC_VecFP, []>;
+} // end HasP9Vector
Index: lib/Target/PowerPC/PPCSubtarget.h
===================================================================
--- lib/Target/PowerPC/PPCSubtarget.h
+++ lib/Target/PowerPC/PPCSubtarget.h
@@ -92,6 +92,8 @@
   bool HasP8Vector;
   bool HasP8Altivec;
   bool HasP8Crypto;
+  bool HasP9Vector;
+  bool HasP9Altivec;
   bool HasFCPSGN;
   bool HasFSQRT;
   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
@@ -229,6 +231,8 @@
   bool hasP8Vector() const { return HasP8Vector; }
   bool hasP8Altivec() const { return HasP8Altivec; }
   bool hasP8Crypto() const { return HasP8Crypto; }
+  bool hasP9Vector() const { return HasP9Vector; }
+  bool hasP9Altivec() const { return HasP9Altivec; }
   bool hasMFOCRF() const { return HasMFOCRF; }
   bool hasISEL() const { return HasISEL; }
   bool hasPOPCNTD() const { return HasPOPCNTD; }
Index: lib/Target/PowerPC/PPCSubtarget.cpp
===================================================================
--- lib/Target/PowerPC/PPCSubtarget.cpp
+++ lib/Target/PowerPC/PPCSubtarget.cpp
@@ -70,6 +70,8 @@
   HasP8Vector = false;
   HasP8Altivec = false;
   HasP8Crypto = false;
+  HasP9Vector = false;
+  HasP9Altivec = false;
   HasFCPSGN = false;
   HasFSQRT = false;
   HasFRE = false;
Index: lib/Target/PowerPC/README_P9.txt
===================================================================
--- /dev/null
+++ lib/Target/PowerPC/README_P9.txt
@@ -0,0 +1,8 @@
+//===- README_P9.txt - Notes for improving Power9 code gen ----------------===//
+
+TODO: Instructions Need Implement Instrinstics or Map to LLVM IR
+
+Altivec:
+
+VSX:
+
Index: test/MC/Disassembler/PowerPC/vsx.txt
===================================================================
--- test/MC/Disassembler/PowerPC/vsx.txt
+++ test/MC/Disassembler/PowerPC/vsx.txt
@@ -539,3 +539,98 @@
 
 # CHECK: mtvsrwz 0, 3
 0x7c 0x03 0x01 0xe6
+
+# Power9 Instructions:
+
+# CHECK: xsiexpdp 63, 3, 4
+0xf3 0xe3 0x27 0x2d
+
+# CHECK: xsiexpqp 7, 31, 27
+0xfc 0xff 0xde 0xc8
+
+# CHECK: xviexpdp 7, 63, 27
+0xf0 0xff 0xdf 0xc4
+
+# CHECK: xviexpsp 7, 63, 27
+0xf0 0xff 0xde 0xc4
+
+# CHECK: xxextractuw 7, 63, 15
+0xf0 0xef 0xfa 0x96
+
+# CHECK: xxinsertw 7, 63, 15
+0xf0 0xef 0xfa 0xd6
+
+# CHECK: xsxexpdp 7, 63
+0xf0 0xe0 0xfd 0x6e
+
+# CHECK: xsxsigdp 7, 63
+0xf0 0xe1 0xfd 0x6e
+
+# CHECK: xsxexpqp 7, 31
+0xfc 0xe2 0xfe 0x48
+
+# CHECK: xsxsigqp 7, 31
+0xfc 0xf2 0xfe 0x48
+
+# CHECK: xvxexpdp 7, 63
+0xf0 0xe0 0xff 0x6e
+
+# CHECK: xvxexpsp 7, 63
+0xf0 0xe8 0xff 0x6e
+
+# CHECK: xvxsigdp 7, 63
+0xf0 0xe1 0xff 0x6e
+
+# CHECK: xvxsigsp 7, 63
+0xf0 0xe9 0xff 0x6e
+
+# CHECK: xststdcsp 7, 63, 127
+0xf3 0xff 0xfc 0xaa
+
+# CHECK: xststdcdp 7, 63, 127
+0xf3 0xff 0xfd 0xaa
+
+# CHECK: xststdcqp 7, 31, 127
+0xff 0xff 0xfd 0x88
+
+# CHECK: xststdcsp 7, 63, 127
+0xf3 0xff 0xfc 0xaa
+
+# CHECK: xststdcdp 7, 63, 127
+0xf3 0xff 0xfd 0xaa
+
+# CHECK: xststdcqp 7, 31, 127
+0xff 0xff 0xfd 0x88
+
+# CHECK: xsmaxcdp 7, 63, 27
+0xf0 0xff 0xdc 0x04
+
+# CHECK: xsmaxjdp 7, 63, 27
+0xf0 0xff 0xdc 0x84
+
+# CHECK: xsmincdp 7, 63, 27
+0xf0 0xff 0xdc 0x44
+
+# CHECK: xsminjdp 7, 63, 27
+0xf0 0xff 0xdc 0xc4
+
+# CHECK: xxbrh 7, 63
+0xf0 0xe7 0xff 0x6e
+
+# CHECK: xxbrw 7, 63
+0xf0 0xef 0xff 0x6e
+
+# CHECK: xxbrd 7, 63
+0xf0 0xf7 0xff 0x6e
+
+# CHECK: xxbrq 7, 63
+0xf0 0xff 0xff 0x6e
+
+# CHECK: xxperm 7, 63, 27
+0xf0 0xff 0xd8 0xd4
+
+# CHECK: xxpermr 7, 63, 27
+0xf0 0xff 0xd9 0xd4
+
+# CHECK: xxspltib 63, 255
+0xf3 0xe7 0xfa 0xd1
Index: test/MC/PowerPC/vsx.s
===================================================================
--- test/MC/PowerPC/vsx.s
+++ test/MC/PowerPC/vsx.s
@@ -547,3 +547,122 @@
 # CHECK-BE: mtvsrwz 0, 3                       # encoding: [0x7c,0x03,0x01,0xe6]
 # CHECK-LE: mtvsrwz 0, 3                       # encoding: [0xe6,0x01,0x03,0x7c]
             mtvsrwz 0, 3
+
+# Power9 Instructions:
+
+# Insert Exponent DP/QP
+# CHECK-BE: xsiexpdp 63, 3, 4                  # encoding: [0xf3,0xe3,0x27,0x2d]
+# CHECK-LE: xsiexpdp 63, 3, 4                  # encoding: [0x2d,0x27,0xe3,0xf3]
+            xsiexpdp 63, 3, 4
+# CHECK-BE: xsiexpqp 7, 31, 27                 # encoding: [0xfc,0xff,0xde,0xc8]
+# CHECK-LE: xsiexpqp 7, 31, 27                 # encoding: [0xc8,0xde,0xff,0xfc]
+            xsiexpqp 7, 31, 27
+
+# Vector Insert Exponent DP
+# CHECK-BE: xviexpdp 7, 63, 27                 # encoding: [0xf0,0xff,0xdf,0xc4]
+# CHECK-LE: xviexpdp 7, 63, 27                 # encoding: [0xc4,0xdf,0xff,0xf0]
+            xviexpdp 7, 63, 27
+# CHECK-BE: xviexpsp 7, 63, 27                 # encoding: [0xf0,0xff,0xde,0xc4]
+# CHECK-LE: xviexpsp 7, 63, 27                 # encoding: [0xc4,0xde,0xff,0xf0]
+            xviexpsp 7, 63, 27
+
+# Vector Extract Unsigned Word
+# CHECK-BE: xxextractuw 7, 63, 15              # encoding: [0xf0,0xef,0xfa,0x96]
+# CHECK-LE: xxextractuw 7, 63, 15              # encoding: [0x96,0xfa,0xef,0xf0]
+            xxextractuw 7, 63, 15
+
+# Vector Insert Word
+# CHECK-BE: xxinsertw 7, 63, 15                # encoding: [0xf0,0xef,0xfa,0xd6]
+# CHECK-LE: xxinsertw 7, 63, 15                # encoding: [0xd6,0xfa,0xef,0xf0]
+            xxinsertw 7, 63, 15
+
+# Extract Exponent/Significand DP/QP
+# CHECK-BE: xsxexpdp 7, 63                     # encoding: [0xf0,0xe0,0xfd,0x6e]
+# CHECK-LE: xsxexpdp 7, 63                     # encoding: [0x6e,0xfd,0xe0,0xf0]
+            xsxexpdp 7, 63
+# CHECK-BE: xsxsigdp 7, 63                     # encoding: [0xf0,0xe1,0xfd,0x6e]
+# CHECK-LE: xsxsigdp 7, 63                     # encoding: [0x6e,0xfd,0xe1,0xf0]
+            xsxsigdp 7, 63
+# CHECK-BE: xsxexpqp 7, 31                     # encoding: [0xfc,0xe2,0xfe,0x48]
+# CHECK-LE: xsxexpqp 7, 31                     # encoding: [0x48,0xfe,0xe2,0xfc]
+            xsxexpqp 7, 31
+# CHECK-BE: xsxsigqp 7, 31                     # encoding: [0xfc,0xf2,0xfe,0x48]
+# CHECK-LE: xsxsigqp 7, 31                     # encoding: [0x48,0xfe,0xf2,0xfc]
+            xsxsigqp 7, 31
+
+# Vector Extract Exponent/Significand DP
+# CHECK-BE: xvxexpdp 7, 63                     # encoding: [0xf0,0xe0,0xff,0x6e]
+# CHECK-LE: xvxexpdp 7, 63                     # encoding: [0x6e,0xff,0xe0,0xf0]
+            xvxexpdp 7, 63
+# CHECK-BE: xvxexpsp 7, 63                     # encoding: [0xf0,0xe8,0xff,0x6e]
+# CHECK-LE: xvxexpsp 7, 63                     # encoding: [0x6e,0xff,0xe8,0xf0]
+            xvxexpsp 7, 63
+# CHECK-BE: xvxsigdp 7, 63                     # encoding: [0xf0,0xe1,0xff,0x6e]
+# CHECK-LE: xvxsigdp 7, 63                     # encoding: [0x6e,0xff,0xe1,0xf0]
+            xvxsigdp 7, 63
+# CHECK-BE: xvxsigsp 7, 63                     # encoding: [0xf0,0xe9,0xff,0x6e]
+# CHECK-LE: xvxsigsp 7, 63                     # encoding: [0x6e,0xff,0xe9,0xf0]
+            xvxsigsp 7, 63
+
+# Test Data Class SP/DP/QP
+# CHECK-BE: xststdcsp 7, 63, 127               # encoding: [0xf3,0xff,0xfc,0xaa]
+# CHECK-LE: xststdcsp 7, 63, 127               # encoding: [0xaa,0xfc,0xff,0xf3]
+            xststdcsp 7, 63, 127
+# CHECK-BE: xststdcdp 7, 63, 127               # encoding: [0xf3,0xff,0xfd,0xaa]
+# CHECK-LE: xststdcdp 7, 63, 127               # encoding: [0xaa,0xfd,0xff,0xf3]
+            xststdcdp 7, 63, 127
+# CHECK-BE: xststdcqp 7, 31, 127               # encoding: [0xff,0xff,0xfd,0x88]
+# CHECK-LE: xststdcqp 7, 31, 127               # encoding: [0x88,0xfd,0xff,0xff]
+            xststdcqp 7, 31, 127
+
+# Vector Test Data Class SP/DP
+# CHECK-BE: xststdcsp 7, 63, 127               # encoding: [0xf3,0xff,0xfc,0xaa]
+# CHECK-LE: xststdcsp 7, 63, 127               # encoding: [0xaa,0xfc,0xff,0xf3]
+            xststdcsp 7, 63, 127
+# CHECK-BE: xststdcdp 7, 63, 127               # encoding: [0xf3,0xff,0xfd,0xaa]
+# CHECK-LE: xststdcdp 7, 63, 127               # encoding: [0xaa,0xfd,0xff,0xf3]
+            xststdcdp 7, 63, 127
+# CHECK-BE: xststdcqp 7, 31, 127               # encoding: [0xff,0xff,0xfd,0x88]
+# CHECK-LE: xststdcqp 7, 31, 127               # encoding: [0x88,0xfd,0xff,0xff]
+            xststdcqp 7, 31, 127
+
+# Maximum/Minimum Type-C/Type-J DP
+# CHECK-BE: xsmaxcdp 7, 63, 27                 # encoding: [0xf0,0xff,0xdc,0x04]
+# CHECK-LE: xsmaxcdp 7, 63, 27                 # encoding: [0x04,0xdc,0xff,0xf0]
+            xsmaxcdp 7, 63, 27
+# CHECK-BE: xsmaxjdp 7, 63, 27                 # encoding: [0xf0,0xff,0xdc,0x84]
+# CHECK-LE: xsmaxjdp 7, 63, 27                 # encoding: [0x84,0xdc,0xff,0xf0]
+            xsmaxjdp 7, 63, 27
+# CHECK-BE: xsmincdp 7, 63, 27                 # encoding: [0xf0,0xff,0xdc,0x44]
+# CHECK-LE: xsmincdp 7, 63, 27                 # encoding: [0x44,0xdc,0xff,0xf0]
+            xsmincdp 7, 63, 27
+# CHECK-BE: xsminjdp 7, 63, 27                 # encoding: [0xf0,0xff,0xdc,0xc4]
+# CHECK-LE: xsminjdp 7, 63, 27                 # encoding: [0xc4,0xdc,0xff,0xf0]
+            xsminjdp 7, 63, 27
+
+# Vector Byte-Reverse H/W/D/Q Word
+# CHECK-BE: xxbrh 7, 63                        # encoding: [0xf0,0xe7,0xff,0x6e]
+# CHECK-LE: xxbrh 7, 63                        # encoding: [0x6e,0xff,0xe7,0xf0]
+            xxbrh 7, 63
+# CHECK-BE: xxbrw 7, 63                        # encoding: [0xf0,0xef,0xff,0x6e]
+# CHECK-LE: xxbrw 7, 63                        # encoding: [0x6e,0xff,0xef,0xf0]
+            xxbrw 7, 63
+# CHECK-BE: xxbrd 7, 63                        # encoding: [0xf0,0xf7,0xff,0x6e]
+# CHECK-LE: xxbrd 7, 63                        # encoding: [0x6e,0xff,0xf7,0xf0]
+            xxbrd 7, 63
+# CHECK-BE: xxbrq 7, 63                        # encoding: [0xf0,0xff,0xff,0x6e]
+# CHECK-LE: xxbrq 7, 63                        # encoding: [0x6e,0xff,0xff,0xf0]
+            xxbrq 7, 63
+
+# Vector Permute
+# CHECK-BE: xxperm 7, 63, 27                   # encoding: [0xf0,0xff,0xd8,0xd4]
+# CHECK-LE: xxperm 7, 63, 27                   # encoding: [0xd4,0xd8,0xff,0xf0]
+            xxperm 7, 63, 27
+# CHECK-BE: xxpermr 7, 63, 27                  # encoding: [0xf0,0xff,0xd9,0xd4]
+# CHECK-LE: xxpermr 7, 63, 27                  # encoding: [0xd4,0xd9,0xff,0xf0]
+            xxpermr 7, 63, 27
+
+# Vector Splat Immediate Byte
+# CHECK-BE: xxspltib 63, 255                   # encoding: [0xf3,0xe7,0xfa,0xd1]
+# CHECK-LE: xxspltib 63, 255                   # encoding: [0xd1,0xfa,0xe7,0xf3]
+            xxspltib 63, 255