Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -81,16 +81,10 @@ } } -// Pick a DEXT or DINS instruction variant based on the pos and size operands -static void LowerDextDins(MCInst& InstIn) { - int Opcode = InstIn.getOpcode(); - - if (Opcode == Mips::DEXT) - assert(InstIn.getNumOperands() == 4 && - "Invalid no. of machine operands for DEXT!"); - else // Only DEXT and DINS are possible - assert(InstIn.getNumOperands() == 5 && - "Invalid no. of machine operands for DINS!"); +// Pick a DINS instruction variant based on the pos and size operands +static void LowerDins(MCInst& InstIn) { + assert(InstIn.getNumOperands() == 5 && + "Invalid no. of machine operands for DINS!"); assert(InstIn.getOperand(2).isImm()); int64_t pos = InstIn.getOperand(2).getImm(); @@ -98,17 +92,17 @@ int64_t size = InstIn.getOperand(3).getImm(); if (size <= 32) { - if (pos < 32) // DEXT/DINS, do nothing + if (pos < 32) // DINS, do nothing return; - // DEXTU/DINSU + // DINSU InstIn.getOperand(2).setImm(pos - 32); - InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU); + InstIn.setOpcode(Mips::DINSU); return; } - // DEXTM/DINSM - assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32"); + // DINSM + assert(pos < 32 && "DINS cannot have both size and pos > 32"); InstIn.getOperand(3).setImm(size - 32); - InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM); + InstIn.setOpcode(Mips::DINSM); return; } @@ -164,9 +158,8 @@ LowerLargeShift(TmpInst); break; // Double extract instruction is chosen by pos and size operands - case Mips::DEXT: case Mips::DINS: - LowerDextDins(TmpInst); + LowerDins(TmpInst); } unsigned long N = Fixups.size(); Index: lib/Target/Mips/MicroMips64r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips64r6InstrInfo.td +++ lib/Target/Mips/MicroMips64r6InstrInfo.td @@ -68,7 +68,7 @@ // TODO: Add 'pos + size' constraint check to dext* instructions // DEXT: 0 < pos + size <= 63 // DEXTM, DEXTU: 32 < pos + size <= 64 -class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5, +class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5_report_uimm6, uimm5_plus1, MipsExt>; class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm5, uimm5_plus33, MipsExt>; Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -845,8 +845,8 @@ def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM_MM<0x1ec>, ISA_MIPS32R2; // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction - def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, - MipsExt>, EXT_FM_MM<0x2c>; + def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5, + immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>; def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM_MM<0x0c>; Index: lib/Target/Mips/Mips64InstrInfo.td =================================================================== --- lib/Target/Mips/Mips64InstrInfo.td +++ lib/Target/Mips/Mips64InstrInfo.td @@ -268,15 +268,14 @@ def RDHWR64 : ReadHardware, RDHWR_FM; let AdditionalPredicates = [NotInMicroMips] in { - // TODO: Add 'pos + size' constraint check to dext* instructions - // DEXT: 0 < pos + size <= 63 - // DEXTM, DEXTU: 32 < pos + size <= 64 - def DEXT : ExtBase<"dext", GPR64Opnd, uimm5, uimm5_plus1, MipsExt>, - EXT_FM<3>; - def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, MipsExt>, - EXT_FM<1>; + // The 'pos + size' constraints are enforced by the code that lowers into + // MipsISD::Ext. + def DEXT : ExtBase<"dext", GPR64Opnd, uimm5_report_uimm6, uimm5_plus1, + immZExt5, immZExt5Plus1, MipsExt>, EXT_FM<3>; + def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, immZExt5, + immZExt5Plus33, MipsExt>, EXT_FM<1>; def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1, - MipsExt>, EXT_FM<2>; + immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>; } def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>; Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -626,6 +626,13 @@ !cast("UImm16RelaxedAsmOperandClass"); } +// Like uimm5 but reports a less confusing error for 32-63 when +// an instruction alias permits that. +def uimm5_report_uimm6 : Operand { + let PrintMethod = "printUnsignedImm"; + let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass; +} + // Like uimm5_64 but reports a less confusing error for 32-63 when // an instruction alias permits that. def uimm5_64_report_uimm6 : Operand { @@ -798,6 +805,16 @@ // shamt field must fit in 5 bits. def immZExt5 : ImmLeaf; +def immZExt5Plus1 : PatLeaf<(imm), [{ + return isUInt<5>(N->getZExtValue() - 1); +}]>; +def immZExt5Plus32 : PatLeaf<(imm), [{ + return isUInt<5>(N->getZExtValue() - 32); +}]>; +def immZExt5Plus33 : PatLeaf<(imm), [{ + return isUInt<5>(N->getZExtValue() - 33); +}]>; + // True if (N + 1) fits in 16-bit field. def immSExt16Plus1 : PatLeaf<(imm), [{ return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); @@ -1246,10 +1263,11 @@ // Ext and Ins class ExtBase : + Operand SizeOpnd, PatFrag PosImm, PatFrag SizeImm, + SDPatternOperator Op = null_frag> : InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size), !strconcat(opstr, " $rt, $rs, $pos, $size"), - [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT, + [(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))], II_EXT, FrmR, opstr>, ISA_MIPS32R2; class InsBase, RDHWR_FM; } // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction -def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, MipsExt>, - EXT_FM<0>; +def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5, + immZExt5Plus1, MipsExt>, EXT_FM<0>; def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>; /// Move Control Registers From/To CPU Registers Index: test/CodeGen/Mips/fcopysign-f32-f64.ll =================================================================== --- test/CodeGen/Mips/fcopysign-f32-f64.ll +++ test/CodeGen/Mips/fcopysign-f32-f64.ll @@ -18,7 +18,7 @@ ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[SLL1]] ; 64: mtc1 $[[OR]], $f0 -; 64R2: dext ${{[0-9]+}}, ${{[0-9]+}}, 63, 1 +; 64R2: dextu ${{[0-9]+}}, ${{[0-9]+}}, 63, 1 ; 64R2: ins $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1 ; 64R2: mtc1 $[[INS]], $f0 Index: test/CodeGen/Mips/fcopysign.ll =================================================================== --- test/CodeGen/Mips/fcopysign.ll +++ test/CodeGen/Mips/fcopysign.ll @@ -27,7 +27,7 @@ ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] ; 64: dmtc1 $[[OR]], $f0 -; 64R2: dext $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1 +; 64R2: dextu $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1 ; 64R2: dins $[[INS:[0-9]+]], $[[EXT]], 63, 1 ; 64R2: dmtc1 $[[INS]], $f0 Index: test/CodeGen/Mips/mips64extins.ll =================================================================== --- test/CodeGen/Mips/mips64extins.ll +++ test/CodeGen/Mips/mips64extins.ll @@ -2,6 +2,7 @@ define i64 @dext(i64 %i) nounwind readnone { entry: +; CHECK-LABEL: dext: ; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10 %shr = lshr i64 %i, 5 %and = and i64 %shr, 1023 @@ -10,7 +11,8 @@ define i64 @dextm(i64 %i) nounwind readnone { entry: -; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 34 +; CHECK-LABEL: dextm: +; CHECK: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 34 %shr = lshr i64 %i, 5 %and = and i64 %shr, 17179869183 ret i64 %and @@ -18,7 +20,8 @@ define i64 @dextu(i64 %i) nounwind readnone { entry: -; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 34, 6 +; CHECK-LABEL: dextu: +; CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 34, 6 %shr = lshr i64 %i, 34 %and = and i64 %shr, 63 ret i64 %and @@ -26,6 +29,7 @@ define i64 @dins(i64 %i, i64 %j) nounwind readnone { entry: +; CHECK-LABEL: dins: ; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10 %shl2 = shl i64 %j, 8 %and = and i64 %shl2, 261888 @@ -36,6 +40,7 @@ define i64 @dinsm(i64 %i, i64 %j) nounwind readnone { entry: +; CHECK-LABEL: dinsm: ; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 10, 33 %shl4 = shl i64 %j, 10 %and = and i64 %shl4, 8796093021184 @@ -46,6 +51,7 @@ define i64 @dinsu(i64 %i, i64 %j) nounwind readnone { entry: +; CHECK-LABEL: dinsu: ; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13 %shl4 = shl i64 %j, 40 %and = and i64 %shl4, 9006099743113216 Index: test/MC/Mips/micromips64r6/invalid.s =================================================================== --- test/MC/Mips/micromips64r6/invalid.s +++ test/MC/Mips/micromips64r6/invalid.s @@ -19,8 +19,8 @@ cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate # FIXME: Check various 'pos + size' constraints on dext* - dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate - dext $2, $3, 32, 1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate + dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate + dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate dext $2, $3, 1, 0 # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32 dext $2, $3, 1, 33 # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32 dextm $2, $3, -1, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate Index: test/MC/Mips/mips64r2/invalid.s =================================================================== --- test/MC/Mips/mips64r2/invalid.s +++ test/MC/Mips/mips64r2/invalid.s @@ -9,8 +9,8 @@ cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate # FIXME: Check various 'pos + size' constraints on dext* - dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate - dext $2, $3, 32, 1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate + dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate + dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate dext $2, $3, 1, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 32 dext $2, $3, 1, 33 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 32 dextm $2, $3, -1, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate