Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -252,6 +252,18 @@ bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); + bool expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + + bool expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + + bool expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + + bool expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI, bool IsLoad); @@ -2240,6 +2252,17 @@ return expandDRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::ABSMacro: return expandAbs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; + case Mips::MULImmMacro: + case Mips::DMULImmMacro: + return expandMulImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; + case Mips::MULOMacro: + case Mips::DMULOMacro: + return expandMulO(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; + case Mips::MULOUMacro: + case Mips::DMULOUMacro: + return expandMulOU(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; + case Mips::DMULMacro: + return expandDMULMacro(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::LDMacro: case Mips::SDMacro: return expandLoadStoreDMacro(Inst, IDLoc, Out, STI, @@ -3871,6 +3894,119 @@ return false; } +bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { + MipsTargetStreamer &TOut = getTargetStreamer(); + unsigned ATReg = Mips::NoRegister; + unsigned DstReg = Inst.getOperand(0).getReg(); + unsigned SrcReg = Inst.getOperand(1).getReg(); + int32_t ImmValue = Inst.getOperand(2).getImm(); + + ATReg = getATReg(IDLoc); + if (!ATReg) + return true; + + loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out, STI); + + TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT, + SrcReg, ATReg, IDLoc, STI); + + TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); + + return false; +} + +bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { + MipsTargetStreamer &TOut = getTargetStreamer(); + unsigned ATReg = Mips::NoRegister; + unsigned DstReg = Inst.getOperand(0).getReg(); + unsigned SrcReg = Inst.getOperand(1).getReg(); + unsigned TmpReg = Inst.getOperand(2).getReg(); + + ATReg = getATReg(Inst.getLoc()); + if (!ATReg) + return true; + + TOut.emitRR(Inst.getOpcode() == Mips::MULOMacro ? Mips::MULT : Mips::DMULT, + SrcReg, TmpReg, IDLoc, STI); + + TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); + + TOut.emitRRI(Inst.getOpcode() == Mips::MULOMacro ? Mips::SRA : Mips::DSRA32, + DstReg, DstReg, 0x1F, IDLoc, STI); + + TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); + + if (useTraps()) { + TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI); + } else { + MCContext & Context = TOut.getStreamer().getContext(); + MCSymbol * BrTarget = Context.createTempSymbol(); + TOut.emitRRX( + Mips::BEQ, DstReg, ATReg, + MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context)), + IDLoc, STI); + if (AssemblerOptions.back()->isReorder()) + TOut.emitNop(IDLoc, STI); + TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); + + TOut.getStreamer().EmitLabel(BrTarget); + } + TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); + + return false; +} + +bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { + MipsTargetStreamer &TOut = getTargetStreamer(); + unsigned ATReg = Mips::NoRegister; + unsigned DstReg = Inst.getOperand(0).getReg(); + unsigned SrcReg = Inst.getOperand(1).getReg(); + unsigned TmpReg = Inst.getOperand(2).getReg(); + + ATReg = getATReg(IDLoc); + if (!ATReg) + return true; + + TOut.emitRR(Inst.getOpcode() == Mips::MULOUMacro ? Mips::MULTu : Mips::DMULTu, + SrcReg, TmpReg, IDLoc, STI); + + TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); + TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); + if (useTraps()) { + TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI); + } else { + MCContext & Context = TOut.getStreamer().getContext(); + MCSymbol * BrTarget = Context.createTempSymbol(); + TOut.emitRRX( + Mips::BEQ, ATReg, Mips::ZERO, + MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context)), + IDLoc, STI); + if (AssemblerOptions.back()->isReorder()) + TOut.emitNop(IDLoc, STI); + TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); + + TOut.getStreamer().EmitLabel(BrTarget); + } + + return false; +} + +bool MipsAsmParser::expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { + MipsTargetStreamer &TOut = getTargetStreamer(); + unsigned DstReg = Inst.getOperand(0).getReg(); + unsigned SrcReg = Inst.getOperand(1).getReg(); + unsigned TmpReg = Inst.getOperand(2).getReg(); + + TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI); + TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); + + return false; +} + static unsigned nextReg(unsigned Reg) { switch (Reg) { case Mips::ZERO: return Mips::AT; Index: lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp +++ lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp @@ -726,14 +726,13 @@ void MipsTargetELFStreamer::emitLabel(MCSymbol *S) { auto *Symbol = cast(S); - if (!isMicroMipsEnabled()) - return; getStreamer().getAssembler().registerSymbol(*Symbol); uint8_t Type = Symbol->getType(); if (Type != ELF::STT_FUNC) return; - Symbol->setOther(ELF::STO_MIPS_MICROMIPS); + if (isMicroMipsEnabled()) + Symbol->setOther(ELF::STO_MIPS_MICROMIPS); } void MipsTargetELFStreamer::finish() { Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -2303,6 +2303,38 @@ def : MipsInstAlias<"seq $rd, $imm", (SEQIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>, NOT_ASE_CNMIPS; + +def MULImmMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, + simm32_relaxed:$imm), + "mul\t$rd, $rs, $imm">; +def MULOMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, + GPR32Opnd:$rt), + "mulo\t$rd, $rs, $rt">, + ISA_MIPS1_NOT_32R6_64R6; +def MULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, + GPR32Opnd:$rt), + "mulou\t$rd, $rs, $rt">, + ISA_MIPS1_NOT_32R6_64R6; + +def DMULImmMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, + simm32_relaxed:$imm), + "dmul\t$rs, $rt, $imm">, + ISA_MIPS1_NOT_32R6_64R6; +def DMULOMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, + GPR32Opnd:$rd), + "dmulo\t$rs, $rt, $rd">, + ISA_MIPS1_NOT_32R6_64R6; +def DMULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, + GPR32Opnd:$rd), + "dmulou\t$rs, $rt, $rd">, + ISA_MIPS1_NOT_32R6_64R6; + +def DMULMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, + GPR32Opnd:$rd), + "dmul\t$rs, $rt, $rd"> { + let InsnPredicates = [HasMips64, NotMips64r6, NotCnMips]; +} + //===----------------------------------------------------------------------===// // Instruction aliases //===----------------------------------------------------------------------===// @@ -2467,6 +2499,14 @@ def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6; def : MipsInstAlias<"sync", (SYNC 0), 1>, ISA_MIPS2; + +def : MipsInstAlias<"mulo $rs, $rt", + (MULOMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, + ISA_MIPS1_NOT_32R6_64R6; +def : MipsInstAlias<"mulou $rs, $rt", + (MULOUMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, + ISA_MIPS1_NOT_32R6_64R6; + //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions //===----------------------------------------------------------------------===// Index: test/MC/Mips/mul-macro-variants.s =================================================================== --- /dev/null +++ test/MC/Mips/mul-macro-variants.s @@ -0,0 +1,155 @@ + +# RUN: llvm-mc %s -triple mips-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s +# RUN: llvm-mc %s -triple mips-unknown-linux -show-encoding -mcpu=mips64r3 | FileCheck %s +# RUN: llvm-mc %s -triple mips-unknown-linux -show-encoding -mcpu=mips64r5 | FileCheck %s + +# RUN: llvm-mc %s -triple mips-unknown-linux -show-encoding -mattr=use-tcc-in-div -mcpu=mips64 | FileCheck %s --check-prefix=CHECK-TRAP +# RUN: llvm-mc %s -triple mips-unknown-linux -show-encoding -mattr=use-tcc-in-div -mcpu=mips64r2 | FileCheck %s --check-prefix=CHECK-TRAP +# RUN: llvm-mc %s -triple mips-unknown-linux -show-encoding -mattr=use-tcc-in-div -mcpu=mips64r3 | FileCheck %s --check-prefix=CHECK-TRAP +# RUN: llvm-mc %s -triple mips-unknown-linux -show-encoding -mattr=use-tcc-in-div -mcpu=mips64r5 | FileCheck %s --check-prefix=CHECK-TRAP + +.text +text_label: + + mul $4, $5 +# CHECK: mul $4, $4, $5 # encoding: [0x70,0x85,0x20,0x02] +# CHECK-TRAP: mul $4, $4, $5 # encoding: [0x70,0x85,0x20,0x02] + mul $4, $5, $6 +# CHECK: mul $4, $5, $6 # encoding: [0x70,0xa6,0x20,0x02] +# CHECK-TRAP: mul $4, $5, $6 # encoding: [0x70,0xa6,0x20,0x02] + mul $4, $5, 0 +# CHECK: addiu $1, $zero, 0 # encoding: [0x24,0x01,0x00,0x00] +# CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: addiu $1, $zero, 0 # encoding: [0x24,0x01,0x00,0x00] +# CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + mul $4, $5, 1 +# CHECK: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01] +# CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01] +# CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + mul $4, $5, 0x8000 +# CHECK: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00] +# CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00] +# CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + mul $4, $5, -0x8000 +# CHECK: addiu $1, $zero, -32768 # encoding: [0x24,0x01,0x80,0x00] +# CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: addiu $1, $zero, -32768 # encoding: [0x24,0x01,0x80,0x00] +# CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + mul $4, $5, 0x10000 +# CHECK: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + mul $4, $5, 0x1a5a5 +# CHECK: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK: ori $1, $1, 42405 # encoding: [0x34,0x21,0xa5,0xa5] +# CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-TRAP: ori $1, $1, 42405 # encoding: [0x34,0x21,0xa5,0xa5] +# CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + mulo $4, $5 +# CHECK: mult $4, $5 # encoding: [0x00,0x85,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK: sra $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc3] +# CHECK: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK: beq $4, $1, $tmp0 # encoding: [0x10,0x81,A,A] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: break 6 # encoding: [0x00,0x06,0x00,0x0d] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: mult $4, $5 # encoding: [0x00,0x85,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: sra $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc3] +# CHECK-TRAP: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK-TRAP: tne $4, $1, 6 # encoding: [0x00,0x81,0x01,0xb6] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + + mulo $4, $5, $6 +# CHECK: mult $5, $6 # encoding: [0x00,0xa6,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK: sra $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc3] +# CHECK: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK: beq $4, $1, $tmp1 # encoding: [0x10,0x81,A,A] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: break 6 # encoding: [0x00,0x06,0x00,0x0d] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: mult $5, $6 # encoding: [0x00,0xa6,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: sra $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc3] +# CHECK-TRAP: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK-TRAP: tne $4, $1, 6 # encoding: [0x00,0x81,0x01,0xb6] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + mulou $4,$5 +# CHECK: multu $4, $5 # encoding: [0x00,0x85,0x00,0x19] +# CHECK: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK: beqz $1, $tmp2 # encoding: [0x10,0x20,A,A] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: break 6 # encoding: [0x00,0x06,0x00,0x0d] +# CHECK-TRAP: multu $4, $5 # encoding: [0x00,0x85,0x00,0x19] +# CHECK-TRAP: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: tne $1, $zero, 6 # encoding: [0x00,0x20,0x01,0xb6] + mulou $4, $5, $6 +# CHECK: multu $5, $6 # encoding: [0x00,0xa6,0x00,0x19] +# CHECK: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK: beqz $1, $tmp3 # encoding: [0x10,0x20,A,A] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: break 6 # encoding: [0x00,0x06,0x00,0x0d] +# CHECK-TRAP: multu $5, $6 # encoding: [0x00,0xa6,0x00,0x19] +# CHECK-TRAP: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: tne $1, $zero, 6 # encoding: [0x00,0x20,0x01,0xb6] + + dmul $4, $5, $6 +# CHECK: dmultu $5, $6 # encoding: [0x00,0xa6,0x00,0x1d] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP dmultu $5, $6 # encoding: [0x00,0xa6,0x00,0x1d] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + dmul $4, $5, 1 +# CHECK: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01] +# CHECK: dmult $5, $1 # encoding: [0x00,0xa1,0x00,0x1c] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01] +# CHECK-TRAP: dmult $5, $1 # encoding: [0x00,0xa1,0x00,0x1c] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + dmulo $4, $5, $6 +# CHECK: dmult $5, $6 # encoding: [0x00,0xa6,0x00,0x1c] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK: dsra32 $4, $4, 31 # encoding: [0x00,0x04,0x27,0xff] +# CHECK: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK: beq $4, $1, $tmp4 # encoding: [0x10,0x81,A,A] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: break 6 # encoding: [0x00,0x06,0x00,0x0d] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: dmult $5, $6 # encoding: [0x00,0xa6,0x00,0x1c] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: dsra32 $4, $4, 31 # encoding: [0x00,0x04,0x27,0xff] +# CHECK-TRAP: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK-TRAP: tne $4, $1, 6 # encoding: [0x00,0x81,0x01,0xb6] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + dmulou $4,$5,$6 +# CHECK: dmultu $5, $6 # encoding: [0x00,0xa6,0x00,0x1d] +# CHECK: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK: beqz $1, $tmp5 # encoding: [0x10,0x20,A,A] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: break 6 # encoding: [0x00,0x06,0x00,0x0d] +# CHECK-TRAP: dmultu $5, $6 # encoding: [0x00,0xa6,0x00,0x1d] +# CHECK-TRAP: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: tne $1, $zero, 6 # encoding: [0x00,0x20,0x01,0xb6]