Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -236,6 +236,13 @@ bool expandAbs(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions); + bool expandMulImm(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions); + bool expandMulO(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions); + bool expandMulOU(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions); + void createNop(bool hasShortDelaySlot, SMLoc IDLoc, SmallVectorImpl &Instructions); @@ -2093,6 +2100,18 @@ case Mips::ABSMacro: return expandAbs(Inst, IDLoc, Instructions) ? MER_Fail : MER_Success; + case Mips::MULImm: + case Mips::DMULImm: + return expandMulImm(Inst, IDLoc, Instructions) ? MER_Fail + : MER_Success; + case Mips::MULOMacro: + case Mips::DMULOMacro: + return expandMulO(Inst, IDLoc, Instructions) ? MER_Fail + : MER_Success; + case Mips::MULOUMacro: + case Mips::DMULOUMacro: + return expandMulOU(Inst, IDLoc, Instructions) ? MER_Fail + : MER_Success; } } @@ -3553,6 +3572,93 @@ return false; } +bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + unsigned ATReg = Mips::NoRegister; + unsigned DReg = Inst.getOperand(0).getReg(); + unsigned SReg = Inst.getOperand(1).getReg(); + int32_t ImmValue = Inst.getOperand(2).getImm(); + + ATReg = getATReg(Inst.getLoc()); + if (!ATReg) + return true; + + loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, Inst.getLoc(), Instructions); + + unsigned Opcode = Mips::NOP; + (Inst.getOpcode() == Mips::MULImm) ? Opcode = Mips::MULT : Opcode = Mips::DMULT; + emitRR(Opcode, SReg, ATReg, IDLoc, Instructions); + + emitR(Mips::MFLO, DReg, IDLoc, Instructions); + + return false; +} + +bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + unsigned ATReg = Mips::NoRegister; + unsigned DReg = Inst.getOperand(0).getReg(); + unsigned SReg = Inst.getOperand(1).getReg(); + unsigned TReg = Inst.getOperand(2).getReg(); + + ATReg = getATReg(Inst.getLoc()); + if (!ATReg) + return true; + + unsigned Opcode = Mips::NOP; + + (Inst.getOpcode() == Mips::MULOMacro) ? Opcode = Mips::MULT : Opcode = Mips::DMULT; + emitRR(Opcode, SReg, TReg, IDLoc, Instructions); + + emitR(Mips::MFLO, DReg, IDLoc, Instructions); + + (Inst.getOpcode() == Mips::MULOMacro) ? Opcode = Mips::SRA : Opcode = Mips::DSRA32; + emitRRI(Opcode, DReg, DReg, 0x1F, IDLoc, Instructions); + + emitR(Mips::MFHI, ATReg, IDLoc, Instructions); + if (useTraps()) { + emitRRI(Mips::TNE, DReg, ATReg, 6, IDLoc, Instructions); + } else { + emitRRI(Mips::BEQ, DReg, ATReg, 8, IDLoc, Instructions); + if (AssemblerOptions.back()->isReorder()) + createNop(false, IDLoc, Instructions); + emitII(Mips::BREAK,6, 0, IDLoc, Instructions); + } + emitR(Mips::MFLO, DReg, IDLoc, Instructions); + + return false; +} + +bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + unsigned ATReg = Mips::NoRegister; + unsigned DReg = Inst.getOperand(0).getReg(); + unsigned SReg = Inst.getOperand(1).getReg(); + unsigned TReg = Inst.getOperand(2).getReg(); + + ATReg = getATReg(Inst.getLoc()); + if (!ATReg) + return true; + + unsigned Opcode = Mips::NOP; + + (Inst.getOpcode() == Mips::MULOUMacro) ? Opcode = Mips::MULTu : Opcode = Mips::DMULTu; + emitRR(Opcode, SReg, TReg, IDLoc, Instructions); + + emitR(Mips::MFHI, ATReg, IDLoc, Instructions); + emitR(Mips::MFLO, DReg, IDLoc, Instructions); + if (useTraps()) { + emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, Instructions); + } else { + emitRRI(Mips::BEQ, ATReg, Mips::ZERO, 8, IDLoc, Instructions); + if (AssemblerOptions.back()->isReorder()) + createNop(false, IDLoc, Instructions); + emitII(Mips::BREAK, 6, 0, IDLoc, Instructions); + } + + return false; +} + void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc, SmallVectorImpl &Instructions) { if (hasShortDelaySlot) Index: lib/Target/Mips/AsmParser/MipsAsmParser.old.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.old.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.old.cpp @@ -236,6 +236,15 @@ bool expandAbs(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions); + bool expandMulImm(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions); + //bool expandMulO(MCInst &Inst, SMLoc IDLoc, + // SmallVectorImpl &Instructions); + bool expandMulO_(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions); + //bool expandMulOU(MCInst &Inst, SMLoc IDLoc, + // SmallVectorImpl &Instructions); + void createNop(bool hasShortDelaySlot, SMLoc IDLoc, SmallVectorImpl &Instructions); @@ -2093,6 +2102,20 @@ case Mips::ABSMacro: return expandAbs(Inst, IDLoc, Instructions) ? MER_Fail : MER_Success; + case Mips::MULImm: + case Mips::DMULImm: + return expandMulImm(Inst, IDLoc, Instructions) ? MER_Fail + : MER_Success; + case Mips::MULO: + case Mips::DMULO: + //return expandMulO(Inst, IDLoc, Instructions) ? MER_Fail + // : MER_Success; + case Mips::MULOU: + case Mips::DMULOU: + //return expandMulOU(Inst, IDLoc, Instructions) ? MER_Fail + // : MER_Success; + return expandMulO_(Inst, IDLoc, Instructions) ? MER_Fail + : MER_Success; } } @@ -3553,6 +3576,142 @@ return false; } +bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + unsigned ATReg = Mips::NoRegister; + unsigned DReg = Inst.getOperand(0).getReg(); + unsigned SReg = Inst.getOperand(1).getReg(); + int32_t ImmValue = Inst.getOperand(2).getImm(); + + ATReg = getATReg(Inst.getLoc()); + if (!ATReg) + return true; + + loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, Inst.getLoc(), Instructions); + if (Inst.getOpcode() == Mips::MULImm) + emitRR(Mips::MULT, SReg, ATReg, IDLoc, Instructions); + else + emitRR(Mips::DMULT, SReg, ATReg, IDLoc, Instructions); + emitR(Mips::MFLO, DReg, IDLoc, Instructions); + + return false; +} + +//bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, +// SmallVectorImpl &Instructions) { +// unsigned ATReg = Mips::NoRegister; +// unsigned DReg = Inst.getOperand(0).getReg(); +// unsigned SReg = Inst.getOperand(1).getReg(); +// unsigned TReg = Inst.getOperand(2).getReg(); +// +// ATReg = getATReg(Inst.getLoc()); +// if (!ATReg) +// return true; +// +// if (Inst.getOpcode() == Mips::MULO) +// emitRR(Mips::MULT, SReg, TReg, IDLoc, Instructions); +// else +// emitRR(Mips::DMULT, SReg, TReg, IDLoc, Instructions); +// emitR(Mips::MFLO, DReg, IDLoc, Instructions); +// if (Inst.getOpcode() == Mips::MULO) +// emitRRI(Mips::SRA, DReg, DReg, 0x1F, IDLoc, Instructions); +// else +// emitRRI(Mips::DSRA32, DReg, DReg, 0x1F, IDLoc, Instructions); +// emitR(Mips::MFHI, ATReg, IDLoc, Instructions); +// emitRRI(Mips::BEQ, DReg, ATReg, 8, IDLoc, Instructions); +// if (AssemblerOptions.back()->isReorder()) +// createNop(false, IDLoc, Instructions); +// emitII(Mips::BREAK,6, 0, IDLoc, Instructions); +// emitR(Mips::MFLO, DReg, IDLoc, Instructions); +// +// return false; +//} + +bool MipsAsmParser::expandMulO_(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + unsigned ATReg = Mips::NoRegister; + unsigned DReg = Inst.getOperand(0).getReg(); + unsigned SReg = Inst.getOperand(1).getReg(); + unsigned TReg = Inst.getOperand(2).getReg(); + + ATReg = getATReg(Inst.getLoc()); + if (!ATReg) + return true; + + switch (Inst.getOpcode()) { + default: + llvm_unreachable("unexpected instruction opcode"); + case Mips::MULO: + emitRR(Mips::MULT, SReg, TReg, IDLoc, Instructions); + break; + case Mips::MULOU: + emitRR(Mips::MULTu, SReg, TReg, IDLoc, Instructions); + emitR(Mips::MFHI, ATReg, IDLoc, Instructions); + break; + case Mips::DMULO: + emitRR(Mips::DMULT, SReg, TReg, IDLoc, Instructions); + break; + case Mips::DMULOU: + emitRR(Mips::DMULTu, SReg, TReg, IDLoc, Instructions); + emitR(Mips::MFHI, ATReg, IDLoc, Instructions); + break; + } + emitR(Mips::MFLO, DReg, IDLoc, Instructions); + + switch (Inst.getOpcode()) { + default: + llvm_unreachable("unexpected instruction opcode"); + case Mips::MULO: + emitRRI(Mips::SRA, DReg, DReg, 0x1F, IDLoc, Instructions); + emitR(Mips::MFHI, ATReg, IDLoc, Instructions); + emitRRI(Mips::BEQ, DReg, ATReg, 8, IDLoc, Instructions); + break; + case Mips::MULOU: + emitRRI(Mips::BEQ, ATReg, Mips::ZERO, 8, IDLoc, Instructions); + break; + case Mips::DMULO: + emitRRI(Mips::DSRA32, DReg, DReg, 0x1F, IDLoc, Instructions); + emitR(Mips::MFHI, ATReg, IDLoc, Instructions); + emitRRI(Mips::BEQ, DReg, ATReg, 8, IDLoc, Instructions); + break; + case Mips::DMULOU: + emitRRI(Mips::BEQ, ATReg, Mips::ZERO, 8, IDLoc, Instructions); + break; + } + + if (AssemblerOptions.back()->isReorder()) + createNop(false, IDLoc, Instructions); + emitII(Mips::BREAK,6, 0, IDLoc, Instructions); + emitR(Mips::MFLO, DReg, IDLoc, Instructions); + + return false; +} + +//bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, +// SmallVectorImpl &Instructions) { +// unsigned ATReg = Mips::NoRegister; +// unsigned DReg = Inst.getOperand(0).getReg(); +// unsigned SReg = Inst.getOperand(1).getReg(); +// unsigned TReg = Inst.getOperand(2).getReg(); +// +// ATReg = getATReg(Inst.getLoc()); +// if (!ATReg) +// return true; +// +// if (Inst.getOpcode() == Mips::MULOU) +// emitRR(Mips::MULTu, SReg, TReg, IDLoc, Instructions); +// else +// emitRR(Mips::DMULTu, SReg, TReg, IDLoc, Instructions); +// emitR(Mips::MFHI, ATReg, IDLoc, Instructions); +// emitR(Mips::MFLO, DReg, IDLoc, Instructions); +// emitRRI(Mips::BEQ, ATReg, Mips::ZERO, 8, IDLoc, Instructions); +// if (AssemblerOptions.back()->isReorder()) +// createNop(false, IDLoc, Instructions); +// emitII(Mips::BREAK, 6, 0, IDLoc, Instructions); +// +// return false; +//} + void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc, SmallVectorImpl &Instructions) { if (hasShortDelaySlot) Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1811,6 +1811,20 @@ def ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs), "abs\t$rd, $rs">; +def MULImm : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, simm16:$imm), + "mul\t$rd, $rs, $imm">; +def MULOMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, GPR32Opnd:$rt), + "mulo\t$rd, $rs, $rt">, ISA_MIPS1_NOT_32R6_64R6; +def MULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, GPR32Opnd:$rt), + "mulou\t$rd, $rs, $rt">, ISA_MIPS1_NOT_32R6_64R6; + +def DMULImm : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), + "dmul\t$rs, $rt, $imm">, ISA_MIPS1_NOT_32R6_64R6; +def DMULOMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), + "dmulo\t$rs, $rt, $rd">, ISA_MIPS1_NOT_32R6_64R6; +def DMULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd), + "dmulou\t$rs, $rt, $rd">, ISA_MIPS1_NOT_32R6_64R6; + //===----------------------------------------------------------------------===// // Instruction aliases //===----------------------------------------------------------------------===// @@ -1925,6 +1939,14 @@ def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6; def : MipsInstAlias<"sync", (SYNC 0), 1>, ISA_MIPS2; + +def : MipsInstAlias<"mulo $rs, $rt", + (MULOMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, + ISA_MIPS1_NOT_32R6_64R6; +def : MipsInstAlias<"mulou $rs, $rt", + (MULOUMacro GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, + ISA_MIPS1_NOT_32R6_64R6; + //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions //===----------------------------------------------------------------------===// Index: test/MC/Mips/mul-macro-variations.s =================================================================== --- test/MC/Mips/mul-macro-variations.s +++ test/MC/Mips/mul-macro-variations.s @@ -0,0 +1,150 @@ +# RUN: llvm-mc %s -triple mips-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s +# RUN: llvm-mc %s -triple mips-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s +# RUN: llvm-mc %s -triple mips-unknown-linux -show-encoding -mcpu=mips64r3 | FileCheck %s +# RUN: llvm-mc %s -triple mips-unknown-linux -show-encoding -mcpu=mips64r5 | FileCheck %s + +# RUN: llvm-mc %s -triple mips-unknown-linux -show-encoding -mattr=use-tcc-in-div -mcpu=mips64 | FileCheck %s --check-prefix=CHECK-TRAP +# RUN: llvm-mc %s -triple mips-unknown-linux -show-encoding -mattr=use-tcc-in-div -mcpu=mips64r2 | FileCheck %s --check-prefix=CHECK-TRAP +# RUN: llvm-mc %s -triple mips-unknown-linux -show-encoding -mattr=use-tcc-in-div -mcpu=mips64r3 | FileCheck %s --check-prefix=CHECK-TRAP +# RUN: llvm-mc %s -triple mips-unknown-linux -show-encoding -mattr=use-tcc-in-div -mcpu=mips64r5 | FileCheck %s --check-prefix=CHECK-TRAP + +.text +text_label: + + mul $4, $5 +# CHECK: mul $4, $4, $5 # encoding: [0x70,0x85,0x20,0x02] +# CHECK-TRAP: mul $4, $4, $5 # encoding: [0x70,0x85,0x20,0x02] + mul $4, $5, $6 +# CHECK: mul $4, $5, $6 # encoding: [0x70,0xa6,0x20,0x02] +# CHECK-TRAP: mul $4, $5, $6 # encoding: [0x70,0xa6,0x20,0x02] + mul $4, $5, 0 +# CHECK: addiu $1, $zero, 0 # encoding: [0x24,0x01,0x00,0x00] +# CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: addiu $1, $zero, 0 # encoding: [0x24,0x01,0x00,0x00] +# CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + mul $4, $5, 1 +# CHECK: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01] +# CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01] +# CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + mul $4, $5, 0x8000 +# CHECK: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00] +# CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00] +# CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + mul $4, $5, -0x8000 +# CHECK: addiu $1, $zero, -32768 # encoding: [0x24,0x01,0x80,0x00] +# CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: addiu $1, $zero, -32768 # encoding: [0x24,0x01,0x80,0x00] +# CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + mul $4, $5, 0x10000 +# CHECK: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + mul $4, $5, 0x1a5a5 +# CHECK: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK: ori $1, $1, 42405 # encoding: [0x34,0x21,0xa5,0xa5] +# CHECK: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01] +# CHECK-TRAP: ori $1, $1, 42405 # encoding: [0x34,0x21,0xa5,0xa5] +# CHECK-TRAP: mult $5, $1 # encoding: [0x00,0xa1,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + mulo $4, $5 +# CHECK: mult $4, $5 # encoding: [0x00,0x85,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK: sra $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc3] +# CHECK: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK: beq $4, $1, 8 # encoding: [0x10,0x81,0x00,0x02] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: break 6 # encoding: [0x00,0x06,0x00,0x0d] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: mult $4, $5 # encoding: [0x00,0x85,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: sra $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc3] +# CHECK-TRAP: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK-TRAP: tne $4, $1, 6 # encoding: [0x00,0x81,0x01,0xb6] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + + mulo $4, $5, $6 +# CHECK: mult $5, $6 # encoding: [0x00,0xa6,0x00,0x18] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK: sra $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc3] +# CHECK: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK: beq $4, $1, 8 # encoding: [0x10,0x81,0x00,0x02] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: break 6 # encoding: [0x00,0x06,0x00,0x0d] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: mult $5, $6 # encoding: [0x00,0xa6,0x00,0x18] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: sra $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc3] +# CHECK-TRAP: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK-TRAP: tne $4, $1, 6 # encoding: [0x00,0x81,0x01,0xb6] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + mulou $4,$5 +# CHECK: multu $4, $5 # encoding: [0x00,0x85,0x00,0x19] +# CHECK: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK: beqz $1, 8 # encoding: [0x10,0x20,0x00,0x02] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: break 6 # encoding: [0x00,0x06,0x00,0x0d] +# CHECK-TRAP: multu $4, $5 # encoding: [0x00,0x85,0x00,0x19] +# CHECK-TRAP: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: tne $1, $zero, 6 # encoding: [0x00,0x20,0x01,0xb6] + mulou $4, $5, $6 +# CHECK: multu $5, $6 # encoding: [0x00,0xa6,0x00,0x19] +# CHECK: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK: beqz $1, 8 # encoding: [0x10,0x20,0x00,0x02] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: break 6 # encoding: [0x00,0x06,0x00,0x0d] +# CHECK-TRAP: multu $5, $6 # encoding: [0x00,0xa6,0x00,0x19] +# CHECK-TRAP: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: tne $1, $zero, 6 # encoding: [0x00,0x20,0x01,0xb6] + + dmul $4, $5, 1 +# CHECK: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01] +# CHECK: dmult $5, $1 # encoding: [0x00,0xa1,0x00,0x1c] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01] +# CHECK-TRAP: dmult $5, $1 # encoding: [0x00,0xa1,0x00,0x1c] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + dmulo $4, $5, $6 +# CHECK: dmult $5, $6 # encoding: [0x00,0xa6,0x00,0x1c] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK: dsra32 $4, $4, 31 # encoding: [0x00,0x04,0x27,0xff] +# CHECK: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK: beq $4, $1, 8 # encoding: [0x10,0x81,0x00,0x02] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: break 6 # encoding: [0x00,0x06,0x00,0x0d] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: dmult $5, $6 # encoding: [0x00,0xa6,0x00,0x1c] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: dsra32 $4, $4, 31 # encoding: [0x00,0x04,0x27,0xff] +# CHECK-TRAP: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK-TRAP: tne $4, $1, 6 # encoding: [0x00,0x81,0x01,0xb6] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] + dmulou $4,$5,$6 +# CHECK: dmultu $5, $6 # encoding: [0x00,0xa6,0x00,0x1d] +# CHECK: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK: beqz $1, 8 # encoding: [0x10,0x20,0x00,0x02] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: break 6 # encoding: [0x00,0x06,0x00,0x0d] +# CHECK-TRAP: dmultu $5, $6 # encoding: [0x00,0xa6,0x00,0x1d] +# CHECK-TRAP: mfhi $1 # encoding: [0x00,0x00,0x08,0x10] +# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12] +# CHECK-TRAP: tne $1, $zero, 6 # encoding: [0x00,0x20,0x01,0xb6]