Index: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
===================================================================
--- lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -980,6 +980,8 @@
     if (!MO.isReg())
       continue;
     unsigned Reg = MO.getReg();
+    if (!Reg)
+      continue;
     if (MO.isDef()) {
       for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
         ModifiedRegs.set(*AI);
@@ -1496,15 +1498,14 @@
   // (inclusive) and the second insn.
   ModifiedRegs.reset();
   UsedRegs.reset();
-  --MBBI;
-  for (unsigned Count = 0; MBBI != B && Count < Limit; --MBBI) {
+  unsigned Count = 0;
+  do {
+    --MBBI;
     MachineInstr *MI = MBBI;
-    // Skip DBG_VALUE instructions.
-    if (MI->isDebugValue())
-      continue;
 
-    // Now that we know this is a real instruction, count it.
-    ++Count;
+    // Don't count DBG_VALUE instructions.
+    if (!MI->isDebugValue())
+      ++Count;
 
     // If we found a match, return it.
     if (isMatchingUpdateInsn(I, MI, BaseReg, Offset))
@@ -1517,7 +1518,7 @@
     // return early.
     if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
       return E;
-  }
+  } while (MBBI != B && Count < Limit);
   return E;
 }
 
Index: test/CodeGen/AArch64/arm64-nvcast.ll
===================================================================
--- test/CodeGen/AArch64/arm64-nvcast.ll
+++ test/CodeGen/AArch64/arm64-nvcast.ll
@@ -2,7 +2,7 @@
 
 ; CHECK-LABEL: _test:
 ; CHECK:  fmov.2d v0, #2.00000000
-; CHECK:  str  q0, [sp]
+; CHECK:  str  q0, [sp, #-16]!
 ; CHECK:  mov  x8, sp
 ; CHECK:  ldr s0, [x8, w1, sxtw #2]
 ; CHECK:  str  s0, [x0]
@@ -16,7 +16,7 @@
 
 ; CHECK-LABEL: _test2
 ; CHECK: movi.16b  v0, #0x3f
-; CHECK: str  q0, [sp]
+; CHECK: str  q0, [sp, #-16]!
 ; CHECK: mov  x8, sp
 ; CHECK: ldr s0, [x8, w1, sxtw #2]
 ; CHECK: str  s0, [x0]