Index: lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp =================================================================== --- lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp +++ lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp @@ -285,6 +285,7 @@ return isReg(MI, 0) && printAlias("jalr", MI, 1, OS); case Mips::NOR: case Mips::NOR_MM: + case Mips::NOR_MMR6: // nor $r0, $r1, $zero => not $r0, $r1 return isReg(MI, 2) && printAlias("not", MI, 0, 1, OS); case Mips::NOR64: Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrInfo.td +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -598,12 +598,12 @@ class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, udiv>; class MOD_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, srem>; class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, urem>; -class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>; +class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>; class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd>; -class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>; -class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>; +class NOR_MMR6_DESC : LogicNOR<"nor", GPR32Opnd>; +class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>; class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd>; -class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>; +class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>; class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd>; class SWE_MMR6_DESC_BASE, MMR6Arch<"addu16">; class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>, - MMR6Arch<"and16">; + MMR6Arch<"and16"> { + int AddedComplexity = 1; +} class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, MMR6Arch<"andi16">; class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">; class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, - MMR6Arch<"or16">; + MMR6Arch<"or16"> { + int AddedComplexity = 1; +} class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>, MMR6Arch<"sll16">; class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>, @@ -1022,7 +1026,9 @@ int AddedComplexity = 1; } class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>, - MMR6Arch<"xor16">; + MMR6Arch<"xor16"> { + int AddedComplexity = 1; +} class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst { dag OutOperandList = (outs GPR32Opnd:$rt); @@ -1501,6 +1507,27 @@ ISA_MICROMIPS32R6; def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6; def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6; +def : MipsInstAlias<"and $rs, $rt, $imm", + (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"and $rs, $imm", + (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"or $rs, $rt, $imm", + (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"or $rs, $imm", + (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"xor $rs, $rt, $imm", + (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"xor $rs, $imm", + (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"not $rt, $rs", + (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, + ISA_MICROMIPS32R6; //===----------------------------------------------------------------------===// // @@ -1512,3 +1539,14 @@ (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6; def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), (SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6; +def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm), + (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>, + ISA_MICROMIPS32R6; +def : MipsPat<(and GPR32:$src, immZExt16:$imm), + (ANDI_MMR6 GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS32R6; +def : MipsPat<(i32 immZExt16:$imm), + (XORI_MMR6 ZERO, immZExt16:$imm)>, ISA_MICROMIPS32R6; +def : MipsPat<(not GPRMM16:$in), + (NOT16_MMR6 GPRMM16:$in)>, ISA_MICROMIPS32R6; +def : MipsPat<(not GPR32:$in), + (NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6; Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -980,63 +980,66 @@ RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6; } -let Predicates = [InMicroMips] in { - //===----------------------------------------------------------------------===// // MicroMips arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// -def : MipsPat<(i32 immLi16:$imm), - (LI16_MM immLi16:$imm)>; -def : MipsPat<(i32 immSExt16:$imm), - (ADDiu_MM ZERO, immSExt16:$imm)>; -def : MipsPat<(i32 immZExt16:$imm), - (ORi_MM ZERO, immZExt16:$imm)>; -def : MipsPat<(not GPR32:$in), - (NOR_MM GPR32Opnd:$in, ZERO)>; - -def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm), - (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>; -def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm), - (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>; -def : MipsPat<(add GPR32:$src, immSExt16:$imm), - (ADDiu_MM GPR32:$src, immSExt16:$imm)>; - -def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm), - (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>; -def : MipsPat<(and GPR32:$src, immZExt16:$imm), - (ANDi_MM GPR32:$src, immZExt16:$imm)>; - -def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm), - (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>; -def : MipsPat<(shl GPR32:$src, immZExt5:$imm), - (SLL_MM GPR32:$src, immZExt5:$imm)>; -def : MipsPat<(shl GPR32:$lhs, GPR32:$rhs), - (SLLV_MM GPR32:$lhs, GPR32:$rhs)>; - -def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm), - (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>; -def : MipsPat<(srl GPR32:$src, immZExt5:$imm), - (SRL_MM GPR32:$src, immZExt5:$imm)>; -def : MipsPat<(srl GPR32:$lhs, GPR32:$rhs), - (SRLV_MM GPR32:$lhs, GPR32:$rhs)>; - -def : MipsPat<(sra GPR32:$src, immZExt5:$imm), - (SRA_MM GPR32:$src, immZExt5:$imm)>; -def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs), - (SRAV_MM GPR32:$lhs, GPR32:$rhs)>; - -def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr), - (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>; -def : MipsPat<(store GPR32:$src, addr:$addr), - (SW_MM GPR32:$src, addr:$addr)>; - -def : MipsPat<(load addrimm4lsl2:$addr), - (LW16_MM addrimm4lsl2:$addr)>; -def : MipsPat<(load addr:$addr), - (LW_MM addr:$addr)>; -def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), - (SUBu_MM GPR32:$lhs, GPR32:$rhs)>; +let Predicates = [InMicroMips] in { + def : MipsPat<(i32 immLi16:$imm), + (LI16_MM immLi16:$imm)>; + def : MipsPat<(i32 immSExt16:$imm), + (ADDiu_MM ZERO, immSExt16:$imm)>; + def : MipsPat<(i32 immZExt16:$imm), + (ORi_MM ZERO, immZExt16:$imm)>; + + def : MipsPat<(not GPRMM16:$in), + (NOT16_MM GPRMM16:$in)>; + def : MipsPat<(not GPR32:$in), + (NOR_MM GPR32Opnd:$in, ZERO)>; + + def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm), + (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>; + def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm), + (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>; + def : MipsPat<(add GPR32:$src, immSExt16:$imm), + (ADDiu_MM GPR32:$src, immSExt16:$imm)>; + + def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm), + (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>; + def : MipsPat<(and GPR32:$src, immZExt16:$imm), + (ANDi_MM GPR32:$src, immZExt16:$imm)>; + + def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm), + (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>; + def : MipsPat<(shl GPR32:$src, immZExt5:$imm), + (SLL_MM GPR32:$src, immZExt5:$imm)>; + def : MipsPat<(shl GPR32:$lhs, GPR32:$rhs), + (SLLV_MM GPR32:$lhs, GPR32:$rhs)>; + + def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm), + (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>; + def : MipsPat<(srl GPR32:$src, immZExt5:$imm), + (SRL_MM GPR32:$src, immZExt5:$imm)>; + def : MipsPat<(srl GPR32:$lhs, GPR32:$rhs), + (SRLV_MM GPR32:$lhs, GPR32:$rhs)>; + + def : MipsPat<(sra GPR32:$src, immZExt5:$imm), + (SRA_MM GPR32:$src, immZExt5:$imm)>; + def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs), + (SRAV_MM GPR32:$lhs, GPR32:$rhs)>; + + def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr), + (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>; + def : MipsPat<(store GPR32:$src, addr:$addr), + (SW_MM GPR32:$src, addr:$addr)>; + + def : MipsPat<(load addrimm4lsl2:$addr), + (LW16_MM addrimm4lsl2:$addr)>; + def : MipsPat<(load addr:$addr), + (LW_MM addr:$addr)>; + def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), + (SUBu_MM GPR32:$lhs, GPR32:$rhs)>; +} //===----------------------------------------------------------------------===// // MicroMips instruction aliases @@ -1048,50 +1051,62 @@ def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS; -def SDIV_MM_Pseudo : MultDivPseudo, ISA_MIPS1_NOT_32R6_64R6; -def UDIV_MM_Pseudo : MultDivPseudo, ISA_MIPS1_NOT_32R6_64R6; +let Predicates = [InMicroMips] in { + def SDIV_MM_Pseudo : MultDivPseudo, ISA_MIPS1_NOT_32R6_64R6; + def UDIV_MM_Pseudo : MultDivPseudo, ISA_MIPS1_NOT_32R6_64R6; def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>; def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>; def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>; -} - -let Predicates = [InMicroMips] in { -def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2; -def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MIPS32R2; -def : MipsInstAlias<"teq $rs, $rt", - (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; -def : MipsInstAlias<"tge $rs, $rt", - (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; -def : MipsInstAlias<"tgeu $rs, $rt", - (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; -def : MipsInstAlias<"tlt $rs, $rt", - (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; -def : MipsInstAlias<"tltu $rs, $rt", - (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; -def : MipsInstAlias<"tne $rs, $rt", - (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; -def : MipsInstAlias<"sll $rd, $rt, $rs", - (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; -def : MipsInstAlias<"sra $rd, $rt, $rs", - (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; -def : MipsInstAlias<"srl $rd, $rt, $rs", - (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; -def : MipsInstAlias<"sll $rd, $rt", - (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; -def : MipsInstAlias<"sra $rd, $rt", - (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; -def : MipsInstAlias<"srl $rd, $rt", - (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; -def : MipsInstAlias<"sll $rd, $shamt", - (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; -def : MipsInstAlias<"sra $rd, $shamt", - (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; -def : MipsInstAlias<"srl $rd, $shamt", - (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; -def : MipsInstAlias<"rotr $rt, $imm", - (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>; -def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>; + def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2; + def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MIPS32R2; + def : MipsInstAlias<"teq $rs, $rt", + (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; + def : MipsInstAlias<"tge $rs, $rt", + (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; + def : MipsInstAlias<"tgeu $rs, $rt", + (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; + def : MipsInstAlias<"tlt $rs, $rt", + (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; + def : MipsInstAlias<"tltu $rs, $rt", + (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; + def : MipsInstAlias<"tne $rs, $rt", + (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; + def : MipsInstAlias<"sll $rd, $rt, $rs", + (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; + def : MipsInstAlias<"sra $rd, $rt, $rs", + (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; + def : MipsInstAlias<"srl $rd, $rt, $rs", + (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; + def : MipsInstAlias<"sll $rd, $rt", + (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; + def : MipsInstAlias<"sra $rd, $rt", + (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; + def : MipsInstAlias<"srl $rd, $rt", + (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; + def : MipsInstAlias<"sll $rd, $shamt", + (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; + def : MipsInstAlias<"sra $rd, $shamt", + (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; + def : MipsInstAlias<"srl $rd, $shamt", + (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>; + def : MipsInstAlias<"rotr $rt, $imm", + (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>; + def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>; + def : MipsInstAlias<"and $rs, $rt, $imm", + (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; + def : MipsInstAlias<"and $rs, $imm", + (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; + def : MipsInstAlias<"or $rs, $rt, $imm", + (ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; + def : MipsInstAlias<"or $rs, $imm", + (ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; + def : MipsInstAlias<"xor $rs, $rt, $imm", + (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; + def : MipsInstAlias<"xor $rs, $imm", + (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; + def : MipsInstAlias<"not $rt, $rs", + (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; } Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1644,16 +1644,16 @@ def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, SLTI_FM<0xb>; let AdditionalPredicates = [NotInMicroMips] in { -def ANDi : MMRel, StdMMR6Rel, - ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>, - ADDI_FM<0xc>; -} -def ORi : MMRel, StdMMR6Rel, - ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>, - ADDI_FM<0xd>; -def XORi : MMRel, StdMMR6Rel, - ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>, - ADDI_FM<0xe>; + def ANDi : MMRel, StdMMR6Rel, + ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>, + ADDI_FM<0xc>; + def ORi : MMRel, StdMMR6Rel, + ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>, + ADDI_FM<0xd>; + def XORi : MMRel, StdMMR6Rel, + ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>, + ADDI_FM<0xe>; +} def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM; let AdditionalPredicates = [NotInMicroMips] in { /// Arithmetic Instructions (3-Operand, R-Type) @@ -1676,8 +1676,8 @@ ADD_FM<0, 0x25>; def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>; -} def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; +} /// Shift Instructions let AdditionalPredicates = [NotInMicroMips] in { @@ -2173,8 +2173,6 @@ def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; } def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32; -def : MipsInstAlias<"not $rt, $rs", - (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; def : MipsInstAlias<"neg $rt, $rs", (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; def : MipsInstAlias<"negu $rt", @@ -2187,20 +2185,29 @@ def : MipsInstAlias< "sltu $rt, $rs, $imm", (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>; -def : MipsInstAlias< +let AdditionalPredicates = [NotInMicroMips] in { + def : MipsInstAlias< + "and $rs, $rt, $imm", + (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; + def : MipsInstAlias< + "and $rs, $imm", + (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>; + def : MipsInstAlias< "xor $rs, $rt, $imm", (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; -def : MipsInstAlias< + def : MipsInstAlias< "xor $rs, $imm", (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>; -def : MipsInstAlias< + def : MipsInstAlias< "or $rs, $rt, $imm", (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; -def : MipsInstAlias< + def : MipsInstAlias< "or $rs, $imm", (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>; -let AdditionalPredicates = [NotInMicroMips] in { -def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; + def : MipsInstAlias< + "not $rt, $rs", + (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; + def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; } def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>; def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>; Index: test/CodeGen/Mips/llvm-ir/and.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/and.ll +++ test/CodeGen/Mips/llvm-ir/and.ll @@ -24,12 +24,23 @@ ; RUN: -check-prefix=ALL -check-prefix=GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM64 define signext i1 @and_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: and_i1: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $2, $4, $5 + + ; MMR6: and16 $[[T0:[0-9]+]], $5 + ; MMR6: move $2, $[[T0]] %r = and i1 %a, %b ret i1 %r @@ -39,7 +50,12 @@ entry: ; ALL-LABEL: and_i8: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $2, $4, $5 + + ; MMR6: and16 $[[T0:[0-9]+]], $5 + ; MMR6: move $2, $[[T0]] %r = and i8 %a, %b ret i8 %r @@ -49,7 +65,12 @@ entry: ; ALL-LABEL: and_i16: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $2, $4, $5 + + ; MMR6: and16 $[[T0:[0-9]+]], $5 + ; MMR6: move $2, $[[T0]] %r = and i16 %a, %b ret i16 %r @@ -64,6 +85,12 @@ ; GP64: and $[[T0:[0-9]+]], $4, $5 ; GP64: sll $2, $[[T0]], 0 + ; MM32: and16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: and $[[T0:[0-9]+]], $4, $5 + ; MM64: sll $2, $[[T0]], 0 + %r = and i32 %a, %b ret i32 %r } @@ -77,6 +104,13 @@ ; GP64: and $2, $4, $5 + ; MM32: and16 $[[T0:[0-9]+]], $6 + ; MM32: and16 $[[T1:[0-9]+]], $7 + ; MM32: move $2, $[[T0]] + ; MM32: move $3, $[[T1]] + + ; MM64: and $2, $4, $5 + %r = and i64 %a, %b ret i64 %r } @@ -97,6 +131,581 @@ ; GP64: and $2, $4, $6 ; GP64: and $3, $5, $7 + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: and16 $[[T1]], $4 + ; MM32: and16 $[[T0]], $5 + ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: and16 $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: and16 $[[T3]], $7 + + ; MM64: and $2, $4, $6 + ; MM64: and $3, $5, $7 + %r = and i128 %a, %b ret i128 %r } + +define signext i1 @and_i1_4(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_4: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MMR6: lui $2, 0 + + %r = and i1 4, %b + ret i1 %r +} + +define signext i8 @and_i8_4(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_4: + + ; GP32: andi $2, $4, 4 + + ; GP64: andi $2, $4, 4 + + ; MMR6: andi16 $2, $4, 4 + + %r = and i8 4, %b + ret i8 %r +} + +define signext i16 @and_i16_4(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_4: + + ; GP32: andi $2, $4, 4 + + ; GP64: andi $2, $4, 4 + + ; MMR6: andi16 $2, $4, 4 + + %r = and i16 4, %b + ret i16 %r +} + +define signext i32 @and_i32_4(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_4: + + ; GP32: andi $2, $4, 4 + + ; GP64: andi $2, $4, 4 + + ; MMR6: andi16 $2, $4, 4 + + %r = and i32 4, %b + ret i32 %r +} + +define signext i64 @and_i64_4(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_4: + + ; GP32: andi $3, $5, 4 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 4 + + ; MM32: andi16 $3, $5, 4 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 4 + + %r = and i64 4, %b + ret i64 %r +} + +define signext i128 @and_i128_4(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_4: + + ; GP32: andi $5, $7, 4 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 4 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 4 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 4 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 4, %b + ret i128 %r +} + +define signext i1 @and_i1_31(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_31: + + ; ALL: move $2, $4 + + %r = and i1 31, %b + ret i1 %r +} + +define signext i8 @and_i8_31(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_31: + + ; GP32: andi $2, $4, 31 + + ; GP64: andi $2, $4, 31 + + ; MMR6: andi16 $2, $4, 31 + + %r = and i8 31, %b + ret i8 %r +} + +define signext i16 @and_i16_31(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_31: + + ; GP32: andi $2, $4, 31 + + ; GP64: andi $2, $4, 31 + + ; MMR6: andi16 $2, $4, 31 + + %r = and i16 31, %b + ret i16 %r +} + +define signext i32 @and_i32_31(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_31: + + ; GP32: andi $2, $4, 31 + + ; GP64: andi $2, $4, 31 + + ; MMR6: andi16 $2, $4, 31 + + %r = and i32 31, %b + ret i32 %r +} + +define signext i64 @and_i64_31(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_31: + + ; GP32: andi $3, $5, 31 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 31 + + ; MM32: andi16 $3, $5, 31 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 31 + + %r = and i64 31, %b + ret i64 %r +} + +define signext i128 @and_i128_31(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_31: + + ; GP32: andi $5, $7, 31 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 31 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 31 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 31 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 31, %b + ret i128 %r +} + +define signext i1 @and_i1_255(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_255: + + ; ALL: move $2, $4 + + %r = and i1 255, %b + ret i1 %r +} + +define signext i8 @and_i8_255(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_255: + + ; ALL: move $2, $4 + + %r = and i8 255, %b + ret i8 %r +} + +define signext i16 @and_i16_255(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_255: + + ; GP32: andi $2, $4, 255 + + ; GP64: andi $2, $4, 255 + + ; MMR6: andi16 $2, $4, 255 + + %r = and i16 255, %b + ret i16 %r +} + +define signext i32 @and_i32_255(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_255: + + ; GP32: andi $2, $4, 255 + + ; GP64: andi $2, $4, 255 + + ; MMR6: andi16 $2, $4, 255 + + %r = and i32 255, %b + ret i32 %r +} + +define signext i64 @and_i64_255(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_255: + + ; GP32: andi $3, $5, 255 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 255 + + ; MM32: andi16 $3, $5, 255 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 255 + + %r = and i64 255, %b + ret i64 %r +} + +define signext i128 @and_i128_255(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_255: + + ; GP32: andi $5, $7, 255 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 255 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 255 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 255 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 255, %b + ret i128 %r +} + +define signext i1 @and_i1_32768(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_32768: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MMR6: lui $2, 0 + + %r = and i1 32768, %b + ret i1 %r +} + +define signext i8 @and_i8_32768(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_32768: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MMR6: lui $2, 0 + + %r = and i8 32768, %b + ret i8 %r +} + +define signext i16 @and_i16_32768(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_32768: + + ; GP32: addiu $[[T0:[0-9]+]], $zero, -32768 + ; GP32: and $2, $4, $[[T0]] + + ; GP64: addiu $[[T0:[0-9]+]], $zero, -32768 + ; GP64: and $2, $4, $[[T0]] + + ; MMR6: addiu $2, $zero, -32768 + ; MMR6: and16 $2, $4 + + %r = and i16 32768, %b + ret i16 %r +} + +define signext i32 @and_i32_32768(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_32768: + + ; GP32: andi $2, $4, 32768 + + ; GP64: andi $2, $4, 32768 + + ; MMR6: andi16 $2, $4, 32768 + + %r = and i32 32768, %b + ret i32 %r +} + +define signext i64 @and_i64_32768(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_32768: + + ; GP32: andi $3, $5, 32768 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 32768 + + ; MM32: andi16 $3, $5, 32768 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 32768 + + %r = and i64 32768, %b + ret i64 %r +} + +define signext i128 @and_i128_32768(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_32768: + + ; GP32: andi $5, $7, 32768 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 32768 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 32768 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 32768 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 32768, %b + ret i128 %r +} + +define signext i1 @and_i1_65(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_65: + + ; ALL: move $2, $4 + + %r = and i1 65, %b + ret i1 %r +} + +define signext i8 @and_i8_65(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_65: + + ; ALL: andi $2, $4, 65 + + %r = and i8 65, %b + ret i8 %r +} + +define signext i16 @and_i16_65(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_65: + + ; ALL: andi $2, $4, 65 + + %r = and i16 65, %b + ret i16 %r +} + +define signext i32 @and_i32_65(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_65: + + ; GP32: andi $2, $4, 65 + + ; GP64: andi $2, $4, 65 + + ; MMR6: andi $2, $4, 65 + + %r = and i32 65, %b + ret i32 %r +} + +define signext i64 @and_i64_65(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_65: + + ; GP32: andi $3, $5, 65 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 65 + + ; MM32: andi $3, $5, 65 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 65 + + %r = and i64 65, %b + ret i64 %r +} + +define signext i128 @and_i128_65(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_65: + + ; GP32: andi $5, $7, 65 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 65 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi $5, $7, 65 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 65 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 65, %b + ret i128 %r +} + +define signext i1 @and_i1_256(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_256: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MMR6: lui $2, 0 + + %r = and i1 256, %b + ret i1 %r +} + +define signext i8 @and_i8_256(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_256: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MMR6: lui $2, 0 + + %r = and i8 256, %b + ret i8 %r +} + +define signext i16 @and_i16_256(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_256: + + ; ALL: andi $2, $4, 256 + + %r = and i16 256, %b + ret i16 %r +} + +define signext i32 @and_i32_256(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_256: + + ; GP32: andi $2, $4, 256 + + ; GP64: andi $2, $4, 256 + + ; MMR6: andi $2, $4, 256 + + %r = and i32 256, %b + ret i32 %r +} + +define signext i64 @and_i64_256(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_256: + + ; GP32: andi $3, $5, 256 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 256 + + ; MM32: andi $3, $5, 256 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 256 + + %r = and i64 256, %b + ret i64 %r +} + +define signext i128 @and_i128_256(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_256: + + ; GP32: andi $5, $7, 256 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 256 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi $5, $7, 256 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 256 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 256, %b + ret i128 %r +} Index: test/CodeGen/Mips/llvm-ir/ashr.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/ashr.ll +++ test/CodeGen/Mips/llvm-ir/ashr.ll @@ -159,9 +159,9 @@ ; MMR6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]] ; MMR6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]] ; MMR6: srlv $[[T6:[0-9]+]], $5, $7 - ; MMR6: not $[[T7:[0-9]+]], $7 - ; MMR6: sll16 $[[T8:[0-9]+]], $4, 1 - ; MMR6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]] + ; MMR6: sll16 $[[T7:[0-9]+]], $4, 1 + ; MMR6: not16 $[[T8:[0-9]+]], $7 + ; MMR6: sllv $[[T9:[0-9]+]], $[[T7]], $[[T8]] ; MMR6: or16 $[[T10:[0-9]+]], $[[T6]] ; MMR6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]] ; MMR6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]] Index: test/CodeGen/Mips/llvm-ir/lshr.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/lshr.ll +++ test/CodeGen/Mips/llvm-ir/lshr.ll @@ -147,9 +147,9 @@ ; MMR3: movn $2, $[[T8]], $[[T6]] ; MMR6: srlv $[[T0:[0-9]+]], $5, $7 - ; MMR6: not $[[T1:[0-9]+]], $7 - ; MMR6: sll16 $[[T2:[0-9]+]], $4, 1 - ; MMR6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; MMR6: sll16 $[[T1:[0-9]+]], $4, 1 + ; MMR6: not16 $[[T2:[0-9]+]], $7 + ; MMR6: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]] ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]] ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32 ; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]] Index: test/CodeGen/Mips/llvm-ir/not.ll =================================================================== --- /dev/null +++ test/CodeGen/Mips/llvm-ir/not.ll @@ -0,0 +1,134 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM64 + +define signext i1 @not_i1(i1 signext %a) { +entry: +; ALL-LABEL: not_i1: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MMR6: not16 $2, $4 + + %r = xor i1 %a, -1 + ret i1 %r +} + +define signext i8 @not_i8(i8 signext %a) { +entry: +; ALL-LABEL: not_i8: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MMR6: not16 $2, $4 + + %r = xor i8 %a, -1 + ret i8 %r +} + +define signext i16 @not_i16(i16 signext %a) { +entry: +; ALL-LABEL: not_i16: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MMR6: not16 $2, $4 + + %r = xor i16 %a, -1 + ret i16 %r +} + +define signext i32 @not_i32(i32 signext %a) { +entry: +; ALL-LABEL: not_i32: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MMR6: not16 $2, $4 + + %r = xor i32 %a, -1 + ret i32 %r +} + +define signext i64 @not_i64(i64 signext %a) { +entry: +; ALL-LABEL: not_i64: + + ; GP32: not $2, $4 + ; GP32: not $3, $5 + + ; GP64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; GP64: xor $2, $4, $[[T0]] + + ; MM32: not16 $2, $4 + ; MM32: not16 $3, $5 + + ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; MM64: xor $2, $4, $[[T0]] + + %r = xor i64 %a, -1 + ret i64 %r +} + +define signext i128 @not_i128(i128 signext %a) { +entry: +; ALL-LABEL: not_i128: + + ; GP32: not $2, $4 + ; GP32: not $3, $5 + ; GP32: not $4, $6 + ; GP32: not $5, $7 + + ; GP64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; GP64: xor $2, $4, $[[T0]] + ; GP64: xor $3, $5, $[[T0]] + + ; MM32: not16 $2, $4 + ; MM32: not16 $3, $5 + ; MM32: not16 $4, $6 + ; MM32: not16 $5, $7 + + ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; MM64: xor $2, $4, $[[T0]] + ; MM64: xor $3, $5, $[[T0]] + + %r = xor i128 %a, -1 + ret i128 %r +} Index: test/CodeGen/Mips/llvm-ir/or.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/or.ll +++ test/CodeGen/Mips/llvm-ir/or.ll @@ -24,12 +24,23 @@ ; RUN: -check-prefix=ALL -check-prefix=GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM64 define signext i1 @or_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: or_i1: - ; ALL: or $2, $4, $5 + ; GP32: or $2, $4, $5 + + ; GP64: or $2, $4, $5 + + ; MMR6: or16 $[[T0:[0-9]+]], $5 + ; MMR6: move $2, $[[T0]] %r = or i1 %a, %b ret i1 %r @@ -39,7 +50,12 @@ entry: ; ALL-LABEL: or_i8: - ; ALL: or $2, $4, $5 + ; GP32: or $2, $4, $5 + + ; GP64: or $2, $4, $5 + + ; MMR6: or16 $[[T0:[0-9]+]], $5 + ; MMR6: move $2, $[[T0]] %r = or i8 %a, %b ret i8 %r @@ -49,7 +65,12 @@ entry: ; ALL-LABEL: or_i16: - ; ALL: or $2, $4, $5 + ; GP32: or $2, $4, $5 + + ; GP64: or $2, $4, $5 + + ; MMR6: or16 $[[T0:[0-9]+]], $5 + ; MMR6: move $2, $[[T0]] %r = or i16 %a, %b ret i16 %r @@ -59,12 +80,18 @@ entry: ; ALL-LABEL: or_i32: - ; GP32: or $2, $4, $5 + ; GP32: or $2, $4, $5 - ; GP64: or $[[T0:[0-9]+]], $4, $5 + ; GP64: or $[[T0:[0-9]+]], $4, $5 ; FIXME: The sll instruction below is redundant. ; GP64: sll $2, $[[T0]], 0 + ; MM32: or16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: or $[[T0:[0-9]+]], $4, $5 + ; MM64: sll $2, $[[T0]], 0 + %r = or i32 %a, %b ret i32 %r } @@ -73,10 +100,17 @@ entry: ; ALL-LABEL: or_i64: - ; GP32: or $2, $4, $6 - ; GP32: or $3, $5, $7 + ; GP32: or $2, $4, $6 + ; GP32: or $3, $5, $7 + + ; GP64: or $2, $4, $5 + + ; MM32: or16 $4, $6 + ; MM32: or16 $5, $7 + ; MM32: move $2, $4 + ; MM32: move $3, $5 - ; GP64: or $2, $4, $5 + ; MM64: or $2, $4, $5 %r = or i64 %a, %b ret i64 %r @@ -86,18 +120,667 @@ entry: ; ALL-LABEL: or_i128: - ; GP32: lw $[[T0:[0-9]+]], 24($sp) - ; GP32: lw $[[T1:[0-9]+]], 20($sp) - ; GP32: lw $[[T2:[0-9]+]], 16($sp) - ; GP32: or $2, $4, $[[T2]] - ; GP32: or $3, $5, $[[T1]] - ; GP32: or $4, $6, $[[T0]] - ; GP32: lw $[[T3:[0-9]+]], 28($sp) - ; GP32: or $5, $7, $[[T3]] + ; GP32: lw $[[T0:[0-9]+]], 24($sp) + ; GP32: lw $[[T1:[0-9]+]], 20($sp) + ; GP32: lw $[[T2:[0-9]+]], 16($sp) + ; GP32: or $2, $4, $[[T2]] + ; GP32: or $3, $5, $[[T1]] + ; GP32: or $4, $6, $[[T0]] + ; GP32: lw $[[T3:[0-9]+]], 28($sp) + ; GP32: or $5, $7, $[[T3]] - ; GP64: or $2, $4, $6 - ; GP64: or $3, $5, $7 + ; GP64: or $2, $4, $6 + ; GP64: or $3, $5, $7 + + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: or16 $[[T1]], $4 + ; MM32: or16 $[[T0]], $5 + ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: or16 $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: or16 $[[T3]], $7 + + ; MM64: or $2, $4, $6 + ; MM64: or $3, $5, $7 %r = or i128 %a, %b ret i128 %r } + +define signext i1 @or_i1_4(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_4: + + ; GP32: move $2, $4 + + ; GP64: move $2, $4 + + ; MMR6: move $2, $4 + + %r = or i1 4, %b + ret i1 %r +} + +define signext i8 @or_i8_4(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_4: + + ; GP32: ori $2, $4, 4 + + ; GP64: ori $2, $4, 4 + + ; MMR6: li16 $2, 4 + ; MMR6: or16 $2, $4 + + %r = or i8 4, %b + ret i8 %r +} + +define signext i16 @or_i16_4(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_4: + + ; GP32: ori $2, $4, 4 + + ; GP64: ori $2, $4, 4 + + ; MMR6: li16 $2, 4 + ; MMR6: or16 $2, $4 + + %r = or i16 4, %b + ret i16 %r +} + +define signext i32 @or_i32_4(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_4: + + ; GP32: ori $2, $4, 4 + + ; GP64: ori $2, $4, 4 + + ; MMR6: li16 $2, 4 + ; MMR6: or16 $2, $4 + + %r = or i32 4, %b + ret i32 %r +} + +define signext i64 @or_i64_4(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_4: + + ; GP32: ori $3, $5, 4 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 4 + + ; MM32: li16 $3, 4 + ; MM32: or16 $3, $5 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 4 + + %r = or i64 4, %b + ret i64 %r +} + +define signext i128 @or_i128_4(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_4: + + ; GP32: ori $[[T0:[0-9]+]], $7, 4 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 4 + ; GP64: move $2, $4 + + ; MM32: addiu $sp, $sp, -8 + ; MM32: sw $[[T0:[0-9]+]], 4($sp) + ; MM32: li16 $[[T0]], 4 + ; MM32: or16 $[[T0]], $7 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + ; MM32: lw $[[T0]], 4($sp) + ; MM32: addiu $sp, $sp, 8 + + ; MM64: ori $3, $5, 4 + ; MM64: move $2, $4 + + %r = or i128 4, %b + ret i128 %r +} + +define signext i1 @or_i1_31(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_31: + + ; GP32: addiu $2, $zero, -1 + + ; GP64: addiu $2, $zero, -1 + + ; MMR6: li16 $2, -1 + + %r = or i1 31, %b + ret i1 %r +} + +define signext i8 @or_i8_31(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_31: + + ; GP32: ori $2, $4, 31 + + ; GP64: ori $2, $4, 31 + + ; MMR6: li16 $2, 31 + ; MMR6: or16 $2, $4 + + %r = or i8 31, %b + ret i8 %r +} + +define signext i16 @or_i16_31(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_31: + + ; GP32: ori $2, $4, 31 + + ; GP64: ori $2, $4, 31 + + ; MMR6: li16 $2, 31 + ; MMR6: or16 $2, $4 + + %r = or i16 31, %b + ret i16 %r +} + +define signext i32 @or_i32_31(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_31: + + ; GP32: ori $2, $4, 31 + + ; GP64: ori $2, $4, 31 + + ; MMR6: li16 $2, 31 + ; MMR6: or16 $2, $4 + + %r = or i32 31, %b + ret i32 %r +} + +define signext i64 @or_i64_31(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_31: + + ; GP32: ori $3, $5, 31 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 31 + + ; MM32: li16 $3, 31 + ; MM32: or16 $3, $5 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 31 + + %r = or i64 31, %b + ret i64 %r +} + +define signext i128 @or_i128_31(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_31: + + ; GP32: ori $[[T0:[0-9]+]], $7, 31 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 31 + ; GP64: move $2, $4 + + ; MM32: addiu $sp, $sp, -8 + ; MM32: sw $[[T0:[0-9]+]], 4($sp) + ; MM32: li16 $[[T0]], 31 + ; MM32: or16 $[[T0]], $7 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + ; MM32: lw $[[T0]], 4($sp) + ; MM32: addiu $sp, $sp, 8 + + ; MM64: ori $3, $5, 31 + ; MM64: move $2, $4 + + %r = or i128 31, %b + ret i128 %r +} + +define signext i1 @or_i1_255(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_255: + + ; GP32: addiu $2, $zero, -1 + + ; GP64: addiu $2, $zero, -1 + + ; MMR6: li16 $2, -1 + + %r = or i1 255, %b + ret i1 %r +} + +define signext i8 @or_i8_255(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_255: + + ; GP32: addiu $2, $zero, -1 + + ; GP64: addiu $2, $zero, -1 + + ; MMR6: li16 $2, -1 + + %r = or i8 255, %b + ret i8 %r +} + +define signext i16 @or_i16_255(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_255: + + ; GP32: ori $2, $4, 255 + + ; GP64: ori $2, $4, 255 + + ; MMR6: addiu $2, $zero, 255 + ; MMR6: or16 $2, $4 + + %r = or i16 255, %b + ret i16 %r +} + +define signext i32 @or_i32_255(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_255: + + ; GP32: ori $2, $4, 255 + + ; GP64: ori $2, $4, 255 + + ; MMR6: addiu $2, $zero, 255 + ; MMR6: or16 $2, $4 + + %r = or i32 255, %b + ret i32 %r +} + +define signext i64 @or_i64_255(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_255: + + ; GP32: ori $3, $5, 255 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 255 + + ; MM32: addiu $3, $zero, 255 + ; MM32: or16 $3, $5 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 255 + + %r = or i64 255, %b + ret i64 %r +} + +define signext i128 @or_i128_255(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_255: + + ; GP32: ori $[[T0:[0-9]+]], $7, 255 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 255 + ; GP64: move $2, $4 + + ; MM32: addiu $sp, $sp, -8 + ; MM32: sw $[[T0:[0-9]+]], 4($sp) + ; MM32: addiu $[[T0]], $zero, 255 + ; MM32: or16 $[[T0]], $7 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + ; MM32: lw $[[T0]], 4($sp) + ; MM32: addiu $sp, $sp, 8 + + ; MM64: ori $3, $5, 255 + ; MM64: move $2, $4 + + %r = or i128 255, %b + ret i128 %r +} + +define signext i1 @or_i1_32768(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_32768: + + ; ALL: move $2, $4 + + %r = or i1 32768, %b + ret i1 %r +} + +define signext i8 @or_i8_32768(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_32768: + + ; ALL: move $2, $4 + + %r = or i8 32768, %b + ret i8 %r +} + +define signext i16 @or_i16_32768(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_32768: + + ; GP32: addiu $[[T0:[0-9]+]], $zero, -32768 + ; GP32: or $2, $4, $[[T0]] + + ; GP64: addiu $[[T0:[0-9]+]], $zero, -32768 + ; GP64: or $2, $4, $[[T0]] + + ; MMR6: addiu $2, $zero, -32768 + ; MMR6: or16 $2, $4 + + %r = or i16 32768, %b + ret i16 %r +} + +define signext i32 @or_i32_32768(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_32768: + + ; GP32: ori $2, $4, 32768 + + ; GP64: ori $2, $4, 32768 + + ; MMR6: ori $2, $zero, 32768 + ; MMR6: or16 $2, $4 + + %r = or i32 32768, %b + ret i32 %r +} + +define signext i64 @or_i64_32768(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_32768: + + ; GP32: ori $3, $5, 32768 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 32768 + + ; MM32: ori $3, $zero, 32768 + ; MM32: or16 $3, $5 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 32768 + + %r = or i64 32768, %b + ret i64 %r +} + +define signext i128 @or_i128_32768(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_32768: + + ; GP32: ori $[[T0:[0-9]+]], $7, 32768 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 32768 + ; GP64: move $2, $4 + + ; MM32: addiu $sp, $sp, -8 + ; MM32: sw $[[T0:[0-9]+]], 4($sp) + ; MM32: ori $[[T0]], $zero, 32768 + ; MM32: or16 $[[T0]], $7 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + ; MM32: lw $[[T0]], 4($sp) + ; MM32: addiu $sp, $sp, 8 + + ; MM64: ori $3, $5, 32768 + ; MM64: move $2, $4 + + %r = or i128 32768, %b + ret i128 %r +} + +define signext i1 @or_i1_65(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_65: + + ; GP32: addiu $2, $zero, -1 + + ; GP64: addiu $2, $zero, -1 + + ; MMR6: li16 $2, -1 + + %r = or i1 65, %b + ret i1 %r +} + +define signext i8 @or_i8_65(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_65: + + ; GP32: ori $2, $4, 65 + + ; GP64: ori $2, $4, 65 + + ; MMR6: li16 $2, 65 + ; MMR6: or16 $2, $4 + + %r = or i8 65, %b + ret i8 %r +} + +define signext i16 @or_i16_65(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_65: + + ; GP32: ori $2, $4, 65 + + ; GP64: ori $2, $4, 65 + + ; MMR6: li16 $2, 65 + ; MMR6: or16 $2, $4 + + %r = or i16 65, %b + ret i16 %r +} + +define signext i32 @or_i32_65(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_65: + + ; GP32: ori $2, $4, 65 + + ; GP64: ori $2, $4, 65 + + ; MMR6: li16 $2, 65 + ; MMR6: or16 $2, $4 + + %r = or i32 65, %b + ret i32 %r +} + +define signext i64 @or_i64_65(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_65: + + ; GP32: ori $3, $5, 65 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 65 + + ; MM32: li16 $3, 65 + ; MM32: or16 $3, $5 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 65 + + %r = or i64 65, %b + ret i64 %r +} + +define signext i128 @or_i128_65(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_65: + + ; GP32: ori $[[T0:[0-9]+]], $7, 65 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 65 + ; GP64: move $2, $4 + + ; MM32: addiu $sp, $sp, -8 + ; MM32: sw $[[T0:[0-9]+]], 4($sp) + ; MM32: li16 $[[T0]], 65 + ; MM32: or16 $[[T0]], $7 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + ; MM32: lw $[[T0]], 4($sp) + ; MM32: addiu $sp, $sp, 8 + + ; MM64: ori $3, $5, 65 + ; MM64: move $2, $4 + + %r = or i128 65, %b + ret i128 %r +} + +define signext i1 @or_i1_256(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_256: + + ; ALL: move $2, $4 + + %r = or i1 256, %b + ret i1 %r +} + +define signext i8 @or_i8_256(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_256: + + ; ALL: move $2, $4 + + %r = or i8 256, %b + ret i8 %r +} + +define signext i16 @or_i16_256(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_256: + + ; GP32: ori $2, $4, 256 + + ; GP64: ori $2, $4, 256 + + ; MMR6: addiu $2, $zero, 256 + ; MMR6: or16 $2, $4 + + %r = or i16 256, %b + ret i16 %r +} + +define signext i32 @or_i32_256(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_256: + + ; GP32: ori $2, $4, 256 + + ; GP64: ori $2, $4, 256 + + ; MMR6: addiu $2, $zero, 256 + ; MMR6: or16 $2, $4 + + %r = or i32 256, %b + ret i32 %r +} + +define signext i64 @or_i64_256(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_256: + + ; GP32: ori $3, $5, 256 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 256 + + ; MM32: addiu $3, $zero, 256 + ; MM32: or16 $3, $5 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 256 + + %r = or i64 256, %b + ret i64 %r +} + +define signext i128 @or_i128_256(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_256: + + ; GP32: ori $[[T0:[0-9]+]], $7, 256 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 256 + ; GP64: move $2, $4 + + ; MM32: addiu $sp, $sp, -8 + ; MM32: sw $[[T0:[0-9]+]], 4($sp) + ; MM32: addiu $[[T0]], $zero, 256 + ; MM32: or16 $[[T0]], $7 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + ; MM32: lw $[[T0]], 4($sp) + ; MM32: addiu $sp, $sp, 8 + + ; MM64: ori $3, $5, 256 + ; MM64: move $2, $4 + + %r = or i128 256, %b + ret i128 %r +} Index: test/CodeGen/Mips/llvm-ir/shl.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/shl.ll +++ test/CodeGen/Mips/llvm-ir/shl.ll @@ -163,9 +163,9 @@ ; MMR3: movn $3, $[[T8]], $[[T6]] ; MMR6: sllv $[[T0:[0-9]+]], $4, $7 - ; MMR6: not $[[T1:[0-9]+]], $7 - ; MMR6: srl16 $[[T2:[0-9]+]], $5, 1 - ; MMR6: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; MMR6: srl16 $[[T1:[0-9]+]], $5, 1 + ; MMR6: not16 $[[T2:[0-9]+]], $7 + ; MMR6: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]] ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]] ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32 ; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]] Index: test/CodeGen/Mips/llvm-ir/xor.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/xor.ll +++ test/CodeGen/Mips/llvm-ir/xor.ll @@ -24,12 +24,23 @@ ; RUN: -check-prefix=ALL -check-prefix=GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM64 define signext i1 @xor_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: xor_i1: - ; ALL: xor $2, $4, $5 + ; GP32: xor $2, $4, $5 + + ; GP64: xor $2, $4, $5 + + ; MMR6: xor16 $[[T0:[0-9]+]], $5 + ; MMR6: move $2, $[[T0]] %r = xor i1 %a, %b ret i1 %r @@ -39,7 +50,12 @@ entry: ; ALL-LABEL: xor_i8: - ; ALL: xor $2, $4, $5 + ; GP32: xor $2, $4, $5 + + ; GP64: xor $2, $4, $5 + + ; MMR6: xor16 $[[T0:[0-9]+]], $5 + ; MMR6: move $2, $[[T0]] %r = xor i8 %a, %b ret i8 %r @@ -49,7 +65,12 @@ entry: ; ALL-LABEL: xor_i16: - ; ALL: xor $2, $4, $5 + ; GP32: xor $2, $4, $5 + + ; GP64: xor $2, $4, $5 + + ; MMR6: xor16 $[[T0:[0-9]+]], $5 + ; MMR6: move $2, $[[T0]] %r = xor i16 %a, %b ret i16 %r @@ -64,6 +85,12 @@ ; GP64: xor $[[T0:[0-9]+]], $4, $5 ; GP64: sll $2, $[[T0]], 0 + ; MM32: xor16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: xor $[[T0:[0-9]+]], $4, $5 + ; MM64: sll $2, $[[T0]], 0 + %r = xor i32 %a, %b ret i32 %r } @@ -77,6 +104,13 @@ ; GP64: xor $2, $4, $5 + ; MM32: xor16 $[[T0:[0-9]+]], $6 + ; MM32: xor16 $[[T1:[0-9]+]], $7 + ; MM32: move $2, $[[T0]] + ; MM32: move $3, $[[T1]] + + ; MM64: xor $2, $4, $5 + %r = xor i64 %a, %b ret i64 %r } @@ -97,6 +131,127 @@ ; GP64: xor $2, $4, $6 ; GP64: xor $3, $5, $7 + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: xor16 $[[T1]], $4 + ; MM32: xor16 $[[T0]], $5 + ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: xor16 $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: xor16 $[[T3]], $7 + + ; MM64: xor $2, $4, $6 + ; MM64: xor $3, $5, $7 + %r = xor i128 %a, %b ret i128 %r } + +define signext i1 @xor_i1_4(i1 signext %b) { +entry: +; ALL-LABEL: xor_i1_4: + + ; GP32: move $2, $4 + + ; GP64: move $2, $4 + + ; MMR6: move $2, $4 + + %r = xor i1 4, %b + ret i1 %r +} + +define signext i8 @xor_i8_4(i8 signext %b) { +entry: +; ALL-LABEL: xor_i8_4: + + ; GP32: xori $2, $4, 4 + + ; GP64: xori $2, $4, 4 + + ; MMR6: li16 $2, 4 + ; MMR6: xor16 $2, $4 + + %r = xor i8 4, %b + ret i8 %r +} + +define signext i16 @xor_i16_4(i16 signext %b) { +entry: +; ALL-LABEL: xor_i16_4: + + ; GP32: xori $2, $4, 4 + + ; GP64: xori $2, $4, 4 + + ; MMR6: li16 $2, 4 + ; MMR6: xor16 $2, $4 + + %r = xor i16 4, %b + ret i16 %r +} + +define signext i32 @xor_i32_4(i32 signext %b) { +entry: +; ALL-LABEL: xor_i32_4: + + ; GP32: xori $2, $4, 4 + + ; GP64: xori $2, $4, 4 + + ; MMR6: li16 $2, 4 + ; MMR6: xor16 $2, $4 + + %r = xor i32 4, %b + ret i32 %r +} + +define signext i64 @xor_i64_4(i64 signext %b) { +entry: +; ALL-LABEL: xor_i64_4: + + ; GP32: xori $3, $5, 4 + ; GP32: move $2, $4 + + ; GP64: xori $2, $4, 4 + + ; MM32: li16 $3, 4 + ; MM32: xor16 $3, $5 + ; MM32: move $2, $4 + + ; MM64: xori $2, $4, 4 + + %r = xor i64 4, %b + ret i64 %r +} + +define signext i128 @xor_i128_4(i128 signext %b) { +entry: +; ALL-LABEL: xor_i128_4: + + ; GP32: xori $[[T0:[0-9]+]], $7, 4 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: xori $3, $5, 4 + ; GP64: move $2, $4 + + ; MM32: addiu $sp, $sp, -8 + ; MM32: sw $[[T0:[0-9]+]], 4($sp) + ; MM32: li16 $[[T0]], 4 + ; MM32: xor16 $[[T0]], $7 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + ; MM32: lw $[[T0]], 4($sp) + ; MM32: addiu $sp, $sp, 8 + + ; MM64: xori $3, $5, 4 + ; MM64: move $2, $4 + + %r = xor i128 4, %b + ret i128 %r +} Index: test/MC/Disassembler/Mips/micromips32r3/valid-el.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r3/valid-el.txt +++ test/MC/Disassembler/Mips/micromips32r3/valid-el.txt @@ -191,3 +191,7 @@ 0x44 0x60 0x08 0xac # CHECK: sce $2, 8($4) 0x00 0x00 0x7c 0x8b # CHECK: syscall 0x8c 0x01 0x7c 0x8b # CHECK: syscall 396 +0x64 0xd0 0x05 0x00 # CHECK: andi $3, $4, 5 +0x64 0x50 0x05 0x00 # CHECK: ori $3, $4, 5 +0x64 0x70 0x05 0x00 # CHECK: xori $3, $4, 5 +0x04 0x00 0xd0 0x1a # CHECK: not $3, $4 Index: test/MC/Disassembler/Mips/micromips32r3/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r3/valid.txt +++ test/MC/Disassembler/Mips/micromips32r3/valid.txt @@ -191,3 +191,7 @@ 0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4) 0x00 0x00 0x8b 0x7c # CHECK: syscall 0x01 0x8c 0x8b 0x7c # CHECK: syscall 396 +0xd0 0x64 0x00 0x05 # CHECK: andi $3, $4, 5 +0x50 0x64 0x00 0x05 # CHECK: ori $3, $4, 5 +0x70 0x64 0x00 0x05 # CHECK: xori $3, $4, 5 +0x00 0x04 0x1a 0xd0 # CHECK: not $3, $4 Index: test/MC/Disassembler/Mips/micromips32r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -309,3 +309,7 @@ 0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5 0x22 0x04 0x10 0x08 # CHECK: lwp $16, 8($4) 0x22 0x04 0x90 0x08 # CHECK: swp $16, 8($4) +0xd0 0x64 0x00 0x05 # CHECK: andi $3, $4, 5 +0x50 0x64 0x00 0x05 # CHECK: ori $3, $4, 5 +0x70 0x64 0x00 0x05 # CHECK: xori $3, $4, 5 +0x00 0x04 0x1a 0xd0 # CHECK: not $3, $4 Index: test/MC/Disassembler/Mips/micromips64r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -9,6 +9,8 @@ 0x4c 0x01 # CHECK: addiusp 1024 0x4c 0x03 # CHECK: addiusp 1028 0x4f 0xf9 # CHECK: addiusp -16 +0x44 0x21 # CHECK: and16 $16, $2 +0x2e 0x56 # CHECK: andi16 $4, $5, 8 0xcc 0x42 # CHECK: bc16 132 0x8f 0x0a # CHECK: beqzc16 $6, 20 0xaf 0x0a # CHECK: bnezc16 $6, 20 @@ -22,6 +24,7 @@ 0x45 0x23 # CHECK: jrc16 $9 0x44 0xb3 # CHECK: jrcaddiusp 20 0x84 0x34 # CHECK: movep $5, $6, $2, $3 +0x45 0xf9 # CHECK: or16 $3, $7 0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4) 0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4) 0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27) @@ -265,3 +268,11 @@ 0x58 0xa6 0x20 0x10 # CHECK: dsllv $4, $5, $6 0x58 0x85 0x28 0x80 # CHECK: dsra $4, $5, 5 0x58 0xa6 0x20 0x90 # CHECK: dsrav $4, $5, $6 +0x00 0xa4 0x1a 0x50 # CHECK: and $3, $4, $5 +0xd0 0x64 0x04 0xd2 # CHECK: andi $3, $4, 1234 +0x00 0xa4 0x1a 0x90 # CHECK: or $3, $4, $5 +0x50 0x64 0x04 0xd2 # CHECK: ori $3, $4, 1234 +0x00 0xa4 0x1b 0x10 # CHECK: xor $3, $4, $5 +0x70 0x64 0x04 0xd2 # CHECK: xori $3, $4, 1234 +0x00 0xa4 0x1a 0xd0 # CHECK: nor $3, $4, $5 +0x00 0x04 0x1a 0xd0 # CHECK: not $3, $4 Index: test/MC/Mips/micromips-alu-instructions.s =================================================================== --- test/MC/Mips/micromips-alu-instructions.s +++ test/MC/Mips/micromips-alu-instructions.s @@ -41,6 +41,14 @@ # CHECK-EL: addiupc $2, 20 # encoding: [0x00,0x79,0x05,0x00] # CHECK-EL: addiupc $7, 16777212 # encoding: [0xbf,0x7b,0xff,0xff] # CHECK-EL: addiupc $7, -16777216 # encoding: [0xc0,0x7b,0x00,0x00] +# CHECK-EL: andi $3, $4, 5 # encoding: [0x64,0xd0,0x05,0x00] +# CHECK-EL: andi $3, $3, 5 # encoding: [0x63,0xd0,0x05,0x00] +# CHECK-EL: ori $3, $4, 5 # encoding: [0x64,0x50,0x05,0x00] +# CHECK-EL: ori $3, $3, 5 # encoding: [0x63,0x50,0x05,0x00] +# CHECK-EL: xori $3, $4, 5 # encoding: [0x64,0x70,0x05,0x00] +# CHECK-EL: xori $3, $3, 5 # encoding: [0x63,0x70,0x05,0x00] +# CHECK-EL: not $3, $4 # encoding: [0x04,0x00,0xd0,0x1a] + #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -78,6 +86,14 @@ # CHECK-EB: addiupc $2, 20 # encoding: [0x79,0x00,0x00,0x05] # CHECK-EB: addiupc $7, 16777212 # encoding: [0x7b,0xbf,0xff,0xff] # CHECK-EB: addiupc $7, -16777216 # encoding: [0x7b,0xc0,0x00,0x00] +# CHECK-EB: andi $3, $4, 5 # encoding: [0xd0,0x64,0x00,0x05] +# CHECK-EB: andi $3, $3, 5 # encoding: [0xd0,0x63,0x00,0x05] +# CHECK-EB: ori $3, $4, 5 # encoding: [0x50,0x64,0x00,0x05] +# CHECK-EB: ori $3, $3, 5 # encoding: [0x50,0x63,0x00,0x05] +# CHECK-EB: xori $3, $4, 5 # encoding: [0x70,0x64,0x00,0x05] +# CHECK-EB: xori $3, $3, 5 # encoding: [0x70,0x63,0x00,0x05] +# CHECK-EB: not $3, $4 # encoding: [0x00,0x04,0x1a,0xd0] + add $9, $6, $7 add $9, $6, 17767 addu $9, $6, -15001 @@ -113,3 +129,10 @@ addiupc $2, 20 addiupc $7, 16777212 addiupc $7, -16777216 + and $3, $4, 5 + and $3, 5 + or $3, $4, 5 + or $3, 5 + xor $3, $4, 5 + xor $3, 5 + not $3, $4 Index: test/MC/Mips/micromips/invalid.s =================================================================== --- test/MC/Mips/micromips/invalid.s +++ test/MC/Mips/micromips/invalid.s @@ -91,3 +91,15 @@ swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset + andi $3, $4, -1 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate + andi $3, $4, 65536 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate + andi $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate + andi $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate + ori $3, $4, -1 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate + ori $3, $4, 65536 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate + ori $3, -1 # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate + ori $3, 65536 # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate + xori $3, $4, -1 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate + xori $3, $4, 65536 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate + xori $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate + xori $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate Index: test/MC/Mips/micromips32r6/invalid.s =================================================================== --- test/MC/Mips/micromips32r6/invalid.s +++ test/MC/Mips/micromips32r6/invalid.s @@ -196,3 +196,15 @@ swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset + andi $3, $4, -1 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate + andi $3, $4, 65536 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate + andi $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate + andi $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate + ori $3, $4, -1 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate + ori $3, $4, 65536 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate + ori $3, -1 # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate + ori $3, 65536 # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate + xori $3, $4, -1 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate + xori $3, $4, 65536 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate + xori $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate + xori $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate Index: test/MC/Mips/micromips32r6/valid.s =================================================================== --- test/MC/Mips/micromips32r6/valid.s +++ test/MC/Mips/micromips32r6/valid.s @@ -329,3 +329,10 @@ srl $3, 7 # CHECK: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40] lwp $16, 8($4) # CHECK: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08] swp $16, 8($4) # CHECK: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08] + and $3, 5 # CHECK: andi $3, $3, 5 # encoding: [0xd0,0x63,0x00,0x05] + and $3, $4, 5 # CHECK: andi $3, $4, 5 # encoding: [0xd0,0x64,0x00,0x05] + not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x04,0x1a,0xd0] + or $3, 5 # CHECK: ori $3, $3, 5 # encoding: [0x50,0x63,0x00,0x05] + or $3, $4, 5 # CHECK: ori $3, $4, 5 # encoding: [0x50,0x64,0x00,0x05] + xor $3, 5 # CHECK: xori $3, $3, 5 # encoding: [0x70,0x63,0x00,0x05] + xor $3, $4, 5 # CHECK: xori $3, $4, 5 # encoding: [0x70,0x64,0x00,0x05] Index: test/MC/Mips/micromips64r6/invalid.s =================================================================== --- test/MC/Mips/micromips64r6/invalid.s +++ test/MC/Mips/micromips64r6/invalid.s @@ -236,3 +236,15 @@ dsra $4, $5, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate dsra32 $4, $5, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate dsra32 $4, $5, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate + andi $3, $4, -1 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate + andi $3, $4, 65536 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate + andi $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate + andi $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate + ori $3, $4, -1 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate + ori $3, $4, 65536 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate + ori $3, -1 # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate + ori $3, 65536 # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate + xori $3, $4, -1 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate + xori $3, $4, 65536 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate + xori $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate + xori $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate Index: test/MC/Mips/micromips64r6/valid.s =================================================================== --- test/MC/Mips/micromips64r6/valid.s +++ test/MC/Mips/micromips64r6/valid.s @@ -10,6 +10,8 @@ addiusp 1024 # CHECK: addiusp 1024 # encoding: [0x4c,0x01] addiusp 1028 # CHECK: addiusp 1028 # encoding: [0x4c,0x03] addiusp -16 # CHECK: addiusp -16 # encoding: [0x4f,0xf9] + and16 $16, $2 # CHECK: and16 $16, $2 # encoding: [0x44,0x21] + andi16 $4, $5, 8 # CHECK: andi16 $4, $5, 8 # encoding: [0x2e,0x56] b 132 # CHECK: bc16 132 # encoding: [0xcc,0x42] bc16 132 # CHECK: bc16 132 # encoding: [0xcc,0x42] beqzc16 $6, 20 # CHECK: beqzc16 $6, 20 # encoding: [0x8f,0x0a] @@ -29,6 +31,7 @@ lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94] lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f] movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34] + or16 $3, $7 # CHECK: or16 $3, $7 # encoding: [0x45,0xf9] ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08] lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08] lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08] @@ -269,5 +272,20 @@ dsra $4, $5, 5 # CHECK: dsra $4, $5, 5 # encoding: [0x58,0x85,0x28,0x80] dsra32 $4, $5, 5 # CHECK: dsra32 $4, $5, 5 # encoding: [0x58,0x85,0x28,0x84] dsrav $4, $5, $6 # CHECK: dsrav $4, $5, $6 # encoding: [0x58,0xa6,0x20,0x90] + and $3, 5 # CHECK: andi $3, $3, 5 # encoding: [0xd0,0x63,0x00,0x05] + and $3, $4, 5 # CHECK: andi $3, $4, 5 # encoding: [0xd0,0x64,0x00,0x05] + and $3, $4, $5 # CHECK: and $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x50] + andi $3, $4, 1234 # CHECK: andi $3, $4, 1234 # encoding: [0xd0,0x64,0x04,0xd2] + nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0] + not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x04,0x1a,0xd0] + or $3, 5 # CHECK: ori $3, $3, 5 # encoding: [0x50,0x63,0x00,0x05] + or $3, $4, 5 # CHECK: ori $3, $4, 5 # encoding: [0x50,0x64,0x00,0x05] + or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90] + ori $3, $4, 1234 # CHECK: ori $3, $4, 1234 # encoding: [0x50,0x64,0x04,0xd2] + xor $3, 5 # CHECK: xori $3, $3, 5 # encoding: [0x70,0x63,0x00,0x05] + xor $3, $4, 5 # CHECK: xori $3, $4, 5 # encoding: [0x70,0x64,0x00,0x05] + xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10] + xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2] + 1: