Index: lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp =================================================================== --- lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp +++ lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp @@ -325,6 +325,7 @@ return isReg(MI, 0) && printAlias("jalr", MI, 1, OS); case Mips::NOR: case Mips::NOR_MM: + case Mips::NOR_MMR6: // nor $r0, $r1, $zero => not $r0, $r1 return isReg(MI, 2) && printAlias("not", MI, 0, 1, OS); case Mips::NOR64: Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrInfo.td +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -504,12 +504,12 @@ class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>; class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>; class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>; -class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>; -class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>; +class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd>; +class NOR_MMR6_DESC : LogicNOR<"nor", GPR32Opnd>; class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>; -class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>; +class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd>; class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>; -class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>; +class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd>; class SWE_MMR6_DESC_BASE, ISA_MICROMIPS32R6; +def : MipsInstAlias<"and $rs, $rt, $imm", + (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"and $rs, $imm", + (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"or $rs, $rt, $imm", + (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"or $rs, $imm", + (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"xor $rs, $rt, $imm", + (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"xor $rs, $imm", + (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"not $rt, $rs", + (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, + ISA_MICROMIPS32R6; //===----------------------------------------------------------------------===// // @@ -1231,3 +1252,15 @@ def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr), (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6; + +def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm), + (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>, + ISA_MICROMIPS32R6; +def : MipsPat<(and GPR32:$src, immZExt16:$imm), + (ANDI_MMR6 GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS32R6; +def : MipsPat<(i32 immZExt16:$imm), + (XORI_MMR6 ZERO, immZExt16:$imm)>, ISA_MICROMIPS32R6; +def : MipsPat<(not GPRMM16:$in), + (NOT16_MMR6 GPRMM16:$in)>, ISA_MICROMIPS32R6; +def : MipsPat<(not GPR32:$in), + (NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6; Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -954,20 +954,23 @@ RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6; } -let Predicates = [InMicroMips] in { - //===----------------------------------------------------------------------===// // MicroMips arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// +def : MipsPat<(not GPRMM16:$in), + (NOT16_MM GPRMM16:$in)>, ISA_MICROMIPS32_NOT_MIPS32R6; +def : MipsPat<(not GPR32:$in), + (NOR_MM GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32_NOT_MIPS32R6; + +let Predicates = [InMicroMips] in { + def : MipsPat<(i32 immLi16:$imm), (LI16_MM immLi16:$imm)>; def : MipsPat<(i32 immSExt16:$imm), (ADDiu_MM ZERO, immSExt16:$imm)>; def : MipsPat<(i32 immZExt16:$imm), (ORi_MM ZERO, immZExt16:$imm)>; -def : MipsPat<(not GPR32:$in), - (NOR_MM GPR32Opnd:$in, ZERO)>; def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm), (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>; @@ -1031,4 +1034,18 @@ (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : MipsInstAlias<"tne $rs, $rt", (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; +def : MipsInstAlias<"and $rs, $rt, $imm", + (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; +def : MipsInstAlias<"and $rs, $imm", + (ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; +def : MipsInstAlias<"or $rs, $rt, $imm", + (ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; +def : MipsInstAlias<"or $rs, $imm", + (ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; +def : MipsInstAlias<"xor $rs, $rt, $imm", + (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; +def : MipsInstAlias<"xor $rs, $imm", + (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; +def : MipsInstAlias<"not $rt, $rs", + (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; } Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1340,16 +1340,16 @@ def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, SLTI_FM<0xb>; let AdditionalPredicates = [NotInMicroMips] in { -def ANDi : MMRel, StdMMR6Rel, - ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>, - ADDI_FM<0xc>; -} -def ORi : MMRel, StdMMR6Rel, - ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>, - ADDI_FM<0xd>; -def XORi : MMRel, StdMMR6Rel, - ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>, - ADDI_FM<0xe>; + def ANDi : MMRel, StdMMR6Rel, + ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>, + ADDI_FM<0xc>; + def ORi : MMRel, StdMMR6Rel, + ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>, + ADDI_FM<0xd>; + def XORi : MMRel, StdMMR6Rel, + ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>, + ADDI_FM<0xe>; +} def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; let AdditionalPredicates = [NotInMicroMips] in { /// Arithmetic Instructions (3-Operand, R-Type) @@ -1372,8 +1372,8 @@ ADD_FM<0, 0x25>; def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>; -} def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; +} /// Shift Instructions let AdditionalPredicates = [NotInMicroMips] in { @@ -1833,17 +1833,11 @@ def : MipsInstAlias<"add $rs, $imm", (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6; -def : MipsInstAlias<"and $rs, $rt, $imm", - (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; -def : MipsInstAlias<"and $rs, $imm", - (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; let Predicates = [NotInMicroMips] in { def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; } def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32; -def : MipsInstAlias<"not $rt, $rs", - (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; def : MipsInstAlias<"neg $rt, $rs", (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; def : MipsInstAlias<"negu $rt", @@ -1854,16 +1848,22 @@ (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; def : MipsInstAlias<"sltu $rt, $rs, $imm", (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>; -def : MipsInstAlias<"xor $rs, $rt, $imm", - (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; -def : MipsInstAlias<"xor $rs, $imm", - (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; -def : MipsInstAlias<"or $rs, $rt, $imm", - (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; -def : MipsInstAlias<"or $rs, $imm", - (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; -let AdditionalPredicates = [NotInMicroMips] in { -def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; +let Predicates = [NotInMicroMips] in { + def : MipsInstAlias<"and $rs, $rt, $imm", + (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; + def : MipsInstAlias<"and $rs, $imm", + (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; + def : MipsInstAlias<"xor $rs, $rt, $imm", + (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; + def : MipsInstAlias<"xor $rs, $imm", + (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; + def : MipsInstAlias<"or $rs, $rt, $imm", + (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>; + def : MipsInstAlias<"or $rs, $imm", + (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; + def : MipsInstAlias<"not $rt, $rs", + (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; + def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; } def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>; def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>; Index: test/CodeGen/Mips/llvm-ir/and.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/and.ll +++ test/CodeGen/Mips/llvm-ir/and.ll @@ -24,12 +24,25 @@ ; RUN: -check-prefix=ALL -check-prefix=GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM64 define signext i1 @and_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: and_i1: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $2, $4, $5 + + ; MMR6: and16 $[[T0:[0-9]+]], $5 + ; MMR6: move $2, $[[T0]] + + ; MM64: nop %r = and i1 %a, %b ret i1 %r @@ -39,7 +52,14 @@ entry: ; ALL-LABEL: and_i8: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $2, $4, $5 + + ; MMR6: and16 $[[T0:[0-9]+]], $5 + ; MMR6: move $2, $[[T0]] + + ; MM64: nop %r = and i8 %a, %b ret i8 %r @@ -49,7 +69,14 @@ entry: ; ALL-LABEL: and_i16: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $2, $4, $5 + + ; MMR6: and16 $[[T0:[0-9]+]], $5 + ; MMR6: move $2, $[[T0]] + + ; MM64: nop %r = and i16 %a, %b ret i16 %r @@ -64,6 +91,12 @@ ; GP64: and $[[T0:[0-9]+]], $4, $5 ; GP64: sll $2, $[[T0]], 0 + ; MM32: and16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: and $[[T0:[0-9]+]], $4, $5 + ; MM64: sll $2, $[[T0]], 0 + %r = and i32 %a, %b ret i32 %r } @@ -77,6 +110,13 @@ ; GP64: and $2, $4, $5 + ; MM32: and16 $[[T0:[0-9]+]], $6 + ; MM32: and16 $[[T1:[0-9]+]], $7 + ; MM32: move $2, $[[T0]] + ; MM32: move $3, $[[T1]] + + ; MM64: and $2, $4, $5 + %r = and i64 %a, %b ret i64 %r } @@ -97,6 +137,116 @@ ; GP64: and $2, $4, $6 ; GP64: and $3, $5, $7 + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: and16 $[[T1]], $4 + ; MM32: and16 $[[T0]], $5 + ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: and16 $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: and16 $[[T3]], $7 + + ; MM64: and $2, $4, $6 + ; MM64: and $3, $5, $7 + %r = and i128 %a, %b ret i128 %r } + +define signext i1 @and_i1_4(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_4: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MMR6: lui $2, 0 + + %r = and i1 4, %b + ret i1 %r +} + +define signext i8 @and_i8_4(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_4: + + ; GP32: andi $2, $4, 4 + + ; GP64: andi $2, $4, 4 + + ; MMR6: andi16 $2, $4, 4 + + %r = and i8 4, %b + ret i8 %r +} + +define signext i16 @and_i16_4(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_4: + + ; GP32: andi $2, $4, 4 + + ; GP64: andi $2, $4, 4 + + ; MMR6: andi16 $2, $4, 4 + + %r = and i16 4, %b + ret i16 %r +} + +define signext i32 @and_i32_4(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_4: + + ; GP32: andi $2, $4, 4 + + ; GP64: andi $2, $4, 4 + + ; MMR6: andi16 $2, $4, 4 + + %r = and i32 4, %b + ret i32 %r +} + +define signext i64 @and_i64_4(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_4: + + ; GP32: andi $3, $5, 4 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 4 + + ; MM32: andi16 $3, $5, 4 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 4 + + %r = and i64 4, %b + ret i64 %r +} + +define signext i128 @and_i128_4(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_4: + + ; GP32: andi $5, $7, 4 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 4 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 4 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 4 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 4, %b + ret i128 %r +} Index: test/CodeGen/Mips/llvm-ir/not.ll =================================================================== --- /dev/null +++ test/CodeGen/Mips/llvm-ir/not.ll @@ -0,0 +1,134 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM64 + +define signext i1 @not_i1(i1 signext %a) { +entry: +; ALL-LABEL: not_i1: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MMR6: not16 $2, $4 + + %r = xor i1 %a, -1 + ret i1 %r +} + +define signext i8 @not_i8(i8 signext %a) { +entry: +; ALL-LABEL: not_i8: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MMR6: not16 $2, $4 + + %r = xor i8 %a, -1 + ret i8 %r +} + +define signext i16 @not_i16(i16 signext %a) { +entry: +; ALL-LABEL: not_i16: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MMR6: not16 $2, $4 + + %r = xor i16 %a, -1 + ret i16 %r +} + +define signext i32 @not_i32(i32 signext %a) { +entry: +; ALL-LABEL: not_i32: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MMR6: not16 $2, $4 + + %r = xor i32 %a, -1 + ret i32 %r +} + +define signext i64 @not_i64(i64 signext %a) { +entry: +; ALL-LABEL: not_i64: + + ; GP32: not $2, $4 + ; GP32: not $3, $5 + + ; GP64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; GP64: xor $2, $4, $[[T0]] + + ; MM32: not16 $2, $4 + ; MM32: not16 $3, $5 + + ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; MM64: xor $2, $4, $[[T0]] + + %r = xor i64 %a, -1 + ret i64 %r +} + +define signext i128 @not_i128(i128 signext %a) { +entry: +; ALL-LABEL: not_i128: + + ; GP32: not $2, $4 + ; GP32: not $3, $5 + ; GP32: not $4, $6 + ; GP32: not $5, $7 + + ; GP64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; GP64: xor $2, $4, $[[T0]] + ; GP64: xor $3, $5, $[[T0]] + + ; MM32: not16 $2, $4 + ; MM32: not16 $3, $5 + ; MM32: not16 $4, $6 + ; MM32: not16 $5, $7 + + ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; MM64: xor $2, $4, $[[T0]] + ; MM64: xor $3, $5, $[[T0]] + + %r = xor i128 %a, -1 + ret i128 %r +} Index: test/CodeGen/Mips/llvm-ir/or.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/or.ll +++ test/CodeGen/Mips/llvm-ir/or.ll @@ -24,12 +24,25 @@ ; RUN: -check-prefix=ALL -check-prefix=GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM64 define signext i1 @or_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: or_i1: - ; ALL: or $2, $4, $5 + ; GP32: or $2, $4, $5 + + ; GP64: or $2, $4, $5 + + ; MMR6: or16 $[[T0:[0-9]+]], $5 + ; MMR6: move $2, $[[T0]] + + ; MM64: nop %r = or i1 %a, %b ret i1 %r @@ -39,7 +52,14 @@ entry: ; ALL-LABEL: or_i8: - ; ALL: or $2, $4, $5 + ; GP32: or $2, $4, $5 + + ; GP64: or $2, $4, $5 + + ; MMR6: or16 $[[T0:[0-9]+]], $5 + ; MMR6: move $2, $[[T0]] + + ; MM64: nop %r = or i8 %a, %b ret i8 %r @@ -49,7 +69,14 @@ entry: ; ALL-LABEL: or_i16: - ; ALL: or $2, $4, $5 + ; GP32: or $2, $4, $5 + + ; GP64: or $2, $4, $5 + + ; MMR6: or16 $[[T0:[0-9]+]], $5 + ; MMR6: move $2, $[[T0]] + + ; MM64: nop %r = or i16 %a, %b ret i16 %r @@ -59,12 +86,18 @@ entry: ; ALL-LABEL: or_i32: - ; GP32: or $2, $4, $5 + ; GP32: or $2, $4, $5 - ; GP64: or $[[T0:[0-9]+]], $4, $5 + ; GP64: or $[[T0:[0-9]+]], $4, $5 ; FIXME: The sll instruction below is redundant. ; GP64: sll $2, $[[T0]], 0 + ; MM32: or16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: or $[[T0:[0-9]+]], $4, $5 + ; MM64: sll $2, $[[T0]], 0 + %r = or i32 %a, %b ret i32 %r } @@ -73,10 +106,17 @@ entry: ; ALL-LABEL: or_i64: - ; GP32: or $2, $4, $6 - ; GP32: or $3, $5, $7 + ; GP32: or $2, $4, $6 + ; GP32: or $3, $5, $7 + + ; GP64: or $2, $4, $5 + + ; MM32: or16 $4, $6 + ; MM32: or16 $5, $7 + ; MM32: move $2, $4 + ; MM32: move $3, $5 - ; GP64: or $2, $4, $5 + ; MM64: or $2, $4, $5 %r = or i64 %a, %b ret i64 %r @@ -86,18 +126,141 @@ entry: ; ALL-LABEL: or_i128: - ; GP32: lw $[[T0:[0-9]+]], 24($sp) - ; GP32: lw $[[T1:[0-9]+]], 20($sp) - ; GP32: lw $[[T2:[0-9]+]], 16($sp) - ; GP32: or $2, $4, $[[T2]] - ; GP32: or $3, $5, $[[T1]] - ; GP32: or $4, $6, $[[T0]] - ; GP32: lw $[[T3:[0-9]+]], 28($sp) - ; GP32: or $5, $7, $[[T3]] + ; GP32: lw $[[T0:[0-9]+]], 24($sp) + ; GP32: lw $[[T1:[0-9]+]], 20($sp) + ; GP32: lw $[[T2:[0-9]+]], 16($sp) + ; GP32: or $2, $4, $[[T2]] + ; GP32: or $3, $5, $[[T1]] + ; GP32: or $4, $6, $[[T0]] + ; GP32: lw $[[T3:[0-9]+]], 28($sp) + ; GP32: or $5, $7, $[[T3]] - ; GP64: or $2, $4, $6 - ; GP64: or $3, $5, $7 + ; GP64: or $2, $4, $6 + ; GP64: or $3, $5, $7 + + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: or16 $[[T1]], $4 + ; MM32: or16 $[[T0]], $5 + ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: or16 $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: or16 $[[T3]], $7 + + ; MM64: or $2, $4, $6 + ; MM64: or $3, $5, $7 %r = or i128 %a, %b ret i128 %r } + +define signext i1 @or_i1_4(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_4: + + ; GP32: move $2, $4 + + ; GP64: move $2, $4 + + ; MMR6: move $2, $4 + + ; MM64: nop + + %r = or i1 4, %b + ret i1 %r +} + +define signext i8 @or_i8_4(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_4: + + ; GP32: ori $2, $4, 4 + + ; GP64: ori $2, $4, 4 + + ; MMR6: li16 $2, 4 + ; MMR6: or16 $2, $4 + + %r = or i8 4, %b + ret i8 %r +} + +define signext i16 @or_i16_4(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_4: + + ; GP32: ori $2, $4, 4 + + ; GP64: ori $2, $4, 4 + + ; MMR6: li16 $2, 4 + ; MMR6: or16 $2, $4 + + %r = or i16 4, %b + ret i16 %r +} + +define signext i32 @or_i32_4(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_4: + + ; GP32: ori $2, $4, 4 + + ; GP64: ori $2, $4, 4 + + ; MMR6: li16 $2, 4 + ; MMR6: or16 $2, $4 + + %r = or i32 4, %b + ret i32 %r +} + +define signext i64 @or_i64_4(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_4: + + ; GP32: ori $3, $5, 4 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 4 + + ; MM32: li16 $3, 4 + ; MM32: or16 $3, $5 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 4 + + %r = or i64 4, %b + ret i64 %r +} + +define signext i128 @or_i128_4(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_4: + + ; GP32: ori $[[T0:[0-9]+]], $7, 4 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 4 + ; GP64: move $2, $4 + + ; MM32: addiu $sp, $sp, -8 + ; MM32: sw $[[T0:[0-9]+]], 4($sp) + ; MM32: li16 $[[T0]], 4 + ; MM32: or16 $[[T0]], $7 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + ; MM32: lw $[[T0]], 4($sp) + ; MM32: addiu $sp, $sp, 8 + + ; MM64: ori $3, $5, 4 + ; MM64: move $2, $4 + + %r = or i128 4, %b + ret i128 %r +} Index: test/CodeGen/Mips/llvm-ir/xor.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/xor.ll +++ test/CodeGen/Mips/llvm-ir/xor.ll @@ -24,12 +24,27 @@ ; RUN: -check-prefix=ALL -check-prefix=GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM64 define signext i1 @xor_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: xor_i1: - ; ALL: xor $2, $4, $5 + ; GP32: xor $2, $4, $5 + + ; GP64: xor $2, $4, $5 + + ; MM32: xor16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: xor16 $4, $5 + ; MM64: move $2, $4 + ; MM64: nop %r = xor i1 %a, %b ret i1 %r @@ -39,7 +54,16 @@ entry: ; ALL-LABEL: xor_i8: - ; ALL: xor $2, $4, $5 + ; GP32: xor $2, $4, $5 + + ; GP64: xor $2, $4, $5 + + ; MM32: xor16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: xor16 $4, $5 + ; MM64: move $2, $4 + ; MM64: nop %r = xor i8 %a, %b ret i8 %r @@ -49,7 +73,16 @@ entry: ; ALL-LABEL: xor_i16: - ; ALL: xor $2, $4, $5 + ; GP32: xor $2, $4, $5 + + ; GP64: xor $2, $4, $5 + + ; MM32: xor16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: xor16 $4, $5 + ; MM64: move $2, $4 + ; MM64: nop %r = xor i16 %a, %b ret i16 %r @@ -64,6 +97,12 @@ ; GP64: xor $[[T0:[0-9]+]], $4, $5 ; GP64: sll $2, $[[T0]], 0 + ; MM32: xor16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: xor $[[T0:[0-9]+]], $4, $5 + ; MM64: sll $2, $[[T0]], 0 + %r = xor i32 %a, %b ret i32 %r } @@ -77,6 +116,13 @@ ; GP64: xor $2, $4, $5 + ; MM32: xor16 $[[T0:[0-9]+]], $6 + ; MM32: xor16 $[[T1:[0-9]+]], $7 + ; MM32: move $2, $[[T0]] + ; MM32: move $3, $[[T1]] + + ; MM64: xor $2, $4, $5 + %r = xor i64 %a, %b ret i64 %r } @@ -97,6 +143,129 @@ ; GP64: xor $2, $4, $6 ; GP64: xor $3, $5, $7 + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: xor16 $[[T1]], $4 + ; MM32: xor16 $[[T0]], $5 + ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: xor16 $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: xor16 $[[T3]], $7 + + ; MM64: xor $2, $4, $6 + ; MM64: xor $3, $5, $7 + %r = xor i128 %a, %b ret i128 %r } + +define signext i1 @xor_i1_4(i1 signext %b) { +entry: +; ALL-LABEL: xor_i1_4: + + ; GP32: move $2, $4 + + ; GP64: move $2, $4 + + ; MMR6: move $2, $4 + + ; MM64: nop + + %r = xor i1 4, %b + ret i1 %r +} + +define signext i8 @xor_i8_4(i8 signext %b) { +entry: +; ALL-LABEL: xor_i8_4: + + ; GP32: xori $2, $4, 4 + + ; GP64: xori $2, $4, 4 + + ; MMR6: li16 $2, 4 + ; MMR6: xor16 $2, $4 + + %r = xor i8 4, %b + ret i8 %r +} + +define signext i16 @xor_i16_4(i16 signext %b) { +entry: +; ALL-LABEL: xor_i16_4: + + ; GP32: xori $2, $4, 4 + + ; GP64: xori $2, $4, 4 + + ; MMR6: li16 $2, 4 + ; MMR6: xor16 $2, $4 + + %r = xor i16 4, %b + ret i16 %r +} + +define signext i32 @xor_i32_4(i32 signext %b) { +entry: +; ALL-LABEL: xor_i32_4: + + ; GP32: xori $2, $4, 4 + + ; GP64: xori $2, $4, 4 + + ; MMR6: li16 $2, 4 + ; MMR6: xor16 $2, $4 + + %r = xor i32 4, %b + ret i32 %r +} + +define signext i64 @xor_i64_4(i64 signext %b) { +entry: +; ALL-LABEL: xor_i64_4: + + ; GP32: xori $3, $5, 4 + ; GP32: move $2, $4 + + ; GP64: xori $2, $4, 4 + + ; MM32: li16 $3, 4 + ; MM32: xor16 $3, $5 + ; MM32: move $2, $4 + + ; MM64: xori $2, $4, 4 + + %r = xor i64 4, %b + ret i64 %r +} + +define signext i128 @xor_i128_4(i128 signext %b) { +entry: +; ALL-LABEL: xor_i128_4: + + ; GP32: xori $[[T0:[0-9]+]], $7, 4 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: xori $3, $5, 4 + ; GP64: move $2, $4 + + ; MM32: addiu $sp, $sp, -8 + ; MM32: sw $[[T0:[0-9]+]], 4($sp) + ; MM32: li16 $[[T0]], 4 + ; MM32: xor16 $[[T0]], $7 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + ; MM32: lw $[[T0]], 4($sp) + ; MM32: addiu $sp, $sp, 8 + + ; MM64: xori $3, $5, 4 + ; MM64: move $2, $4 + + %r = xor i128 4, %b + ret i128 %r +} Index: test/MC/Disassembler/Mips/micromips32r3/valid-el.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r3/valid-el.txt +++ test/MC/Disassembler/Mips/micromips32r3/valid-el.txt @@ -189,3 +189,10 @@ 0x04 0x63 0x02 0x64 # CHECK: lwle $24, 2($4) 0x44 0x60 0x08 0x6c # CHECK: lle $2, 8($4) 0x44 0x60 0x08 0xac # CHECK: sce $2, 8($4) +0x64 0xd0 0x05 0x00 # CHECK: andi $3, $4, 5 +0x63 0xd0 0x05 0x00 # CHECK: andi $3, $3, 5 +0x64 0x50 0x05 0x00 # CHECK: ori $3, $4, 5 +0x63 0x50 0x05 0x00 # CHECK: ori $3, $3, 5 +0x64 0x70 0x05 0x00 # CHECK: xori $3, $4, 5 +0x63 0x70 0x05 0x00 # CHECK: xori $3, $3, 5 +0x04 0x00 0xd0 0x1a # CHECK: not $3, $4 Index: test/MC/Disassembler/Mips/micromips32r3/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r3/valid.txt +++ test/MC/Disassembler/Mips/micromips32r3/valid.txt @@ -189,3 +189,10 @@ 0x63 0x04 0x64 0x02 # CHECK: lwle $24, 2($4) 0x60 0x44 0x6c 0x08 # CHECK: lle $2, 8($4) 0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4) +0xd0 0x64 0x00 0x05 # CHECK: andi $3, $4, 5 +0xd0 0x63 0x00 0x05 # CHECK: andi $3, $3, 5 +0x50 0x64 0x00 0x05 # CHECK: ori $3, $4, 5 +0x50 0x63 0x00 0x05 # CHECK: ori $3, $3, 5 +0x70 0x64 0x00 0x05 # CHECK: xori $3, $4, 5 +0x70 0x63 0x00 0x05 # CHECK: xori $3, $3, 5 +0x00 0x04 0x1a 0xd0 # CHECK: not $3, $4 Index: test/MC/Disassembler/Mips/micromips32r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -256,3 +256,10 @@ 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4 0x00 0x00 0x47 0x7c # CHECK: di 0x00 0x0f 0x47 0x7c # CHECK: di $15 +0xd0 0x64 0x00 0x05 # CHECK: andi $3, $4, 5 +0xd0 0x63 0x00 0x05 # CHECK: andi $3, $3, 5 +0x50 0x64 0x00 0x05 # CHECK: ori $3, $4, 5 +0x50 0x63 0x00 0x05 # CHECK: ori $3, $3, 5 +0x70 0x64 0x00 0x05 # CHECK: xori $3, $4, 5 +0x70 0x63 0x00 0x05 # CHECK: xori $3, $3, 5 +0x00 0x04 0x1a 0xd0 # CHECK: not $3, $4 Index: test/MC/Disassembler/Mips/micromips64r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -169,3 +169,20 @@ 0x00 0x00 0xe3 0x7c # CHECK: deret 0x00 0x00 0x47 0x7c # CHECK: di 0x00 0x0f 0x47 0x7c # CHECK: di $15 +0x44 0x21 # CHECK: and16 $16, $2 +0x2e 0x56 # CHECK: andi16 $4, $5, 8 +0x00 0xa4 0x1a 0x50 # CHECK: and $3, $4, $5 +0xd0 0x64 0x04 0xd2 # CHECK: andi $3, $4, 1234 +0x45 0xf9 # CHECK: or16 $3, $7 +0x00 0xa4 0x1a 0x90 # CHECK: or $3, $4, $5 +0x50 0x64 0x04 0xd2 # CHECK: ori $3, $4, 1234 +0x00 0xa4 0x1b 0x10 # CHECK: xor $3, $4, $5 +0x70 0x64 0x04 0xd2 # CHECK: xori $3, $4, 1234 +0xd0 0x64 0x00 0x05 # CHECK: andi $3, $4, 5 +0xd0 0x63 0x00 0x05 # CHECK: andi $3, $3, 5 +0x50 0x64 0x00 0x05 # CHECK: ori $3, $4, 5 +0x50 0x63 0x00 0x05 # CHECK: ori $3, $3, 5 +0x70 0x64 0x00 0x05 # CHECK: xori $3, $4, 5 +0x70 0x63 0x00 0x05 # CHECK: xori $3, $3, 5 +0x00 0xa4 0x1a 0xd0 # CHECK: nor $3, $4, $5 +0x00 0x04 0x1a 0xd0 # CHECK: not $3, $4 Index: test/MC/Mips/micromips-alu-instructions.s =================================================================== --- test/MC/Mips/micromips-alu-instructions.s +++ test/MC/Mips/micromips-alu-instructions.s @@ -41,6 +41,14 @@ # CHECK-EL: addiupc $2, 20 # encoding: [0x00,0x79,0x05,0x00] # CHECK-EL: addiupc $7, 16777212 # encoding: [0xbf,0x7b,0xff,0xff] # CHECK-EL: addiupc $7, -16777216 # encoding: [0xc0,0x7b,0x00,0x00] +# CHECK-EL: andi $3, $4, 5 # encoding: [0x64,0xd0,0x05,0x00] +# CHECK-EL: andi $3, $3, 5 # encoding: [0x63,0xd0,0x05,0x00] +# CHECK-EL: ori $3, $4, 5 # encoding: [0x64,0x50,0x05,0x00] +# CHECK-EL: ori $3, $3, 5 # encoding: [0x63,0x50,0x05,0x00] +# CHECK-EL: xori $3, $4, 5 # encoding: [0x64,0x70,0x05,0x00] +# CHECK-EL: xori $3, $3, 5 # encoding: [0x63,0x70,0x05,0x00] +# CHECK-EL: not $3, $4 # encoding: [0x04,0x00,0xd0,0x1a] + #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -78,6 +86,14 @@ # CHECK-EB: addiupc $2, 20 # encoding: [0x79,0x00,0x00,0x05] # CHECK-EB: addiupc $7, 16777212 # encoding: [0x7b,0xbf,0xff,0xff] # CHECK-EB: addiupc $7, -16777216 # encoding: [0x7b,0xc0,0x00,0x00] +# CHECK-EB: andi $3, $4, 5 # encoding: [0xd0,0x64,0x00,0x05] +# CHECK-EB: andi $3, $3, 5 # encoding: [0xd0,0x63,0x00,0x05] +# CHECK-EB: ori $3, $4, 5 # encoding: [0x50,0x64,0x00,0x05] +# CHECK-EB: ori $3, $3, 5 # encoding: [0x50,0x63,0x00,0x05] +# CHECK-EB: xori $3, $4, 5 # encoding: [0x70,0x64,0x00,0x05] +# CHECK-EB: xori $3, $3, 5 # encoding: [0x70,0x63,0x00,0x05] +# CHECK-EB: not $3, $4 # encoding: [0x00,0x04,0x1a,0xd0] + add $9, $6, $7 add $9, $6, 17767 addu $9, $6, -15001 @@ -113,3 +129,10 @@ addiupc $2, 20 addiupc $7, 16777212 addiupc $7, -16777216 + and $3, $4, 5 + and $3, 5 + or $3, $4, 5 + or $3, 5 + xor $3, $4, 5 + xor $3, 5 + not $3, $4 Index: test/MC/Mips/micromips32r6/valid.s =================================================================== --- test/MC/Mips/micromips32r6/valid.s +++ test/MC/Mips/micromips32r6/valid.s @@ -250,3 +250,10 @@ class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60] deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c] + and $3, $4, 5 # CHECK: andi $3, $4, 5 # encoding: [0xd0,0x64,0x00,0x05] + and $3, 5 # CHECK: andi $3, $3, 5 # encoding: [0xd0,0x63,0x00,0x05] + or $3, $4, 5 # CHECK: ori $3, $4, 5 # encoding: [0x50,0x64,0x00,0x05] + or $3, 5 # CHECK: ori $3, $3, 5 # encoding: [0x50,0x63,0x00,0x05] + xor $3, $4, 5 # CHECK: xori $3, $4, 5 # encoding: [0x70,0x64,0x00,0x05] + xor $3, 5 # CHECK: xori $3, $3, 5 # encoding: [0x70,0x63,0x00,0x05] + not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x04,0x1a,0xd0] Index: test/MC/Mips/micromips64r6/valid.s =================================================================== --- test/MC/Mips/micromips64r6/valid.s +++ test/MC/Mips/micromips64r6/valid.s @@ -150,5 +150,22 @@ di # CHECK: di # encoding: [0x00,0x00,0x47,0x7c] di $0 # CHECK: di # encoding: [0x00,0x00,0x47,0x7c] di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c] + and16 $16, $2 # CHECK: and16 $16, $2 # encoding: [0x44,0x21] + andi16 $4, $5, 8 # CHECK: andi16 $4, $5, 8 # encoding: [0x2e,0x56] + and $3, $4, $5 # CHECK: and $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x50] + andi $3, $4, 1234 # CHECK: andi $3, $4, 1234 # encoding: [0xd0,0x64,0x04,0xd2] + or16 $3, $7 # CHECK: or16 $3, $7 # encoding: [0x45,0xf9] + or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90] + ori $3, $4, 1234 # CHECK: ori $3, $4, 1234 # encoding: [0x50,0x64,0x04,0xd2] + xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10] + xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2] + and $3, $4, 5 # CHECK: andi $3, $4, 5 # encoding: [0xd0,0x64,0x00,0x05] + and $3, 5 # CHECK: andi $3, $3, 5 # encoding: [0xd0,0x63,0x00,0x05] + or $3, $4, 5 # CHECK: ori $3, $4, 5 # encoding: [0x50,0x64,0x00,0x05] + or $3, 5 # CHECK: ori $3, $3, 5 # encoding: [0x50,0x63,0x00,0x05] + xor $3, $4, 5 # CHECK: xori $3, $4, 5 # encoding: [0x70,0x64,0x00,0x05] + xor $3, 5 # CHECK: xori $3, $3, 5 # encoding: [0x70,0x63,0x00,0x05] + nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0] + not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x04,0x1a,0xd0] 1: