Removed incorrect FeatureVFPOnlySP for Cortex-R7

[SjoerdMeijer]

Summary

Removed incorrect FeatureVFPOnlySP from the Cortex-R7 processor model description and changed the regression test accordingly.

[SjoerdMeijer]

Adding Renato

[rengolin]

Those are just the default values, and we tend to use default values for the most common platforms.

I'm adding Richard and Alexandros, that have been working on architecture support, and know better than I do what's the right choice.

cheers,
--renato

[bsmith]

The default configuration of a Cortex-R7 is to implement the VFPv3-D16 architecture, the feature line as it is is too restrictive. I believe the intention of the targets in this file is to have them as maximal, hence this change looks good it me.

[SjoerdMeijer]

Committed revision 259480.

lib/Target/ARM/ARM.td

def : ProcessorModel<"cortex-r5",   CortexA8Model,      [ARMv7r, ProcR5,
                                                          FeatureHasSlowFPVMLx,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureT2XtPk]>;
 
 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
 def : ProcessorModel<"cortex-r7",   CortexA8Model,      [ARMv7r, ProcR7,
                                                          FeatureHasRAS,
                                                          FeatureVFP3,
-                                                         FeatureVFPOnlySP,
                                                          FeatureD16,
                                                          FeatureFP16,
                                                          FeatureMP,
                                                          FeatureSlowFPBrcc,
                                                          FeatureHWDivARM,
                                                          FeatureHasSlowFPVMLx,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureT2XtPk]>;

test/CodeGen/ARM/build-attributes.ll

 ; CORTEX-R5-FAST-NOT:  .eabi_attribute 22
 ; CORTEX-R5-FAST:  .eabi_attribute 23, 1
 
 ; CORTEX-R7:  .cpu cortex-r7
 ; CORTEX-R7:  .eabi_attribute 6, 10
 ; CORTEX-R7:  .eabi_attribute 7, 82
 ; CORTEX-R7:  .eabi_attribute 8, 1
 ; CORTEX-R7:  .eabi_attribute 9, 2
-; CORTEX-R7:  .fpu vfpv3xd
+; CORTEX-R7:  .fpu vfpv3-d16-fp16
 ; CORTEX-R7-NOT:   .eabi_attribute 19
 ;; We default to IEEE 754 compliance
 ; CORTEX-R7:  .eabi_attribute 20, 1
 ; CORTEX-R7:  .eabi_attribute 21, 1
 ; CORTEX-R7-NOT:  .eabi_attribute 22
 ; CORTEX-R7:  .eabi_attribute 23, 3
 ; CORTEX-R7:  .eabi_attribute 24, 1
 ; CORTEX-R7:  .eabi_attribute 25, 1
-; CORTEX-R7:  .eabi_attribute 27, 1
 ; CORTEX-R7-NOT:  .eabi_attribute 28
 ; CORTEX-R7:  .eabi_attribute 36, 1
 ; CORTEX-R7:  .eabi_attribute 38, 1
 ; CORTEX-R7:  .eabi_attribute 42, 1
 ; CORTEX-R7:  .eabi_attribute 44, 2
 ; CORTEX-R7-NOT:  .eabi_attribute 68
 
 ; CORTEX-R7-FAST-NOT:   .eabi_attribute 19