Index: lib/Target/AMDGPU/R600ISelLowering.cpp =================================================================== --- lib/Target/AMDGPU/R600ISelLowering.cpp +++ lib/Target/AMDGPU/R600ISelLowering.cpp @@ -661,47 +661,47 @@ return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32, SDValue(interp, 0), SDValue(interp, 1)); } - case AMDGPUIntrinsic::R600_tex: - case AMDGPUIntrinsic::R600_texc: - case AMDGPUIntrinsic::R600_txl: - case AMDGPUIntrinsic::R600_txlc: - case AMDGPUIntrinsic::R600_txb: - case AMDGPUIntrinsic::R600_txbc: - case AMDGPUIntrinsic::R600_txf: - case AMDGPUIntrinsic::R600_txq: - case AMDGPUIntrinsic::R600_ddx: - case AMDGPUIntrinsic::R600_ddy: + case AMDGPUIntrinsic::r600_tex: + case AMDGPUIntrinsic::r600_texc: + case AMDGPUIntrinsic::r600_txl: + case AMDGPUIntrinsic::r600_txlc: + case AMDGPUIntrinsic::r600_txb: + case AMDGPUIntrinsic::r600_txbc: + case AMDGPUIntrinsic::r600_txf: + case AMDGPUIntrinsic::r600_txq: + case AMDGPUIntrinsic::r600_ddx: + case AMDGPUIntrinsic::r600_ddy: case AMDGPUIntrinsic::R600_ldptr: { unsigned TextureOp; switch (IntrinsicID) { - case AMDGPUIntrinsic::R600_tex: + case AMDGPUIntrinsic::r600_tex: TextureOp = 0; break; - case AMDGPUIntrinsic::R600_texc: + case AMDGPUIntrinsic::r600_texc: TextureOp = 1; break; - case AMDGPUIntrinsic::R600_txl: + case AMDGPUIntrinsic::r600_txl: TextureOp = 2; break; - case AMDGPUIntrinsic::R600_txlc: + case AMDGPUIntrinsic::r600_txlc: TextureOp = 3; break; - case AMDGPUIntrinsic::R600_txb: + case AMDGPUIntrinsic::r600_txb: TextureOp = 4; break; - case AMDGPUIntrinsic::R600_txbc: + case AMDGPUIntrinsic::r600_txbc: TextureOp = 5; break; - case AMDGPUIntrinsic::R600_txf: + case AMDGPUIntrinsic::r600_txf: TextureOp = 6; break; - case AMDGPUIntrinsic::R600_txq: + case AMDGPUIntrinsic::r600_txq: TextureOp = 7; break; - case AMDGPUIntrinsic::R600_ddx: + case AMDGPUIntrinsic::r600_ddx: TextureOp = 8; break; - case AMDGPUIntrinsic::R600_ddy: + case AMDGPUIntrinsic::r600_ddy: TextureOp = 9; break; case AMDGPUIntrinsic::R600_ldptr: Index: lib/Target/AMDGPU/R600Intrinsics.td =================================================================== --- lib/Target/AMDGPU/R600Intrinsics.td +++ lib/Target/AMDGPU/R600Intrinsics.td @@ -11,6 +11,7 @@ // //===----------------------------------------------------------------------===// +// FIXME: Should migrate to using TargetPrefix that matches triple arch name. let TargetPrefix = "R600", isTarget = 1 in { class TextureIntrinsicFloatInput : Intrinsic<[llvm_v4f32_ty], [ @@ -39,25 +40,16 @@ llvm_i32_ty // coord_type_w ], [IntrNoMem]>; + def int_R600_ldptr : TextureIntrinsicInt32Input; + def int_R600_interp_const : Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], [IntrNoMem]>; -def int_R600_interp_xy : + def int_R600_interp_xy : Intrinsic<[llvm_v2f32_ty], [llvm_i32_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>; -def int_R600_interp_zw : + def int_R600_interp_zw : Intrinsic<[llvm_v2f32_ty], [llvm_i32_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>; def int_R600_load_texbuf : Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; - def int_R600_tex : TextureIntrinsicFloatInput; - def int_R600_texc : TextureIntrinsicFloatInput; - def int_R600_txl : TextureIntrinsicFloatInput; - def int_R600_txlc : TextureIntrinsicFloatInput; - def int_R600_txb : TextureIntrinsicFloatInput; - def int_R600_txbc : TextureIntrinsicFloatInput; - def int_R600_txf : TextureIntrinsicInt32Input; - def int_R600_ldptr : TextureIntrinsicInt32Input; - def int_R600_txq : TextureIntrinsicInt32Input; - def int_R600_ddx : TextureIntrinsicFloatInput; - def int_R600_ddy : TextureIntrinsicFloatInput; def int_R600_store_swizzle : Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>; def int_R600_store_stream_output : @@ -68,4 +60,17 @@ Intrinsic<[], [llvm_float_ty], []>; def int_R600_store_dummy : Intrinsic<[], [llvm_i32_ty], []>; +} // End TargetPrefix = "R600", isTarget = 1 + +let TargetPrefix = "r600", isTarget = 1 in { + def int_r600_tex : TextureIntrinsicFloatInput; + def int_r600_texc : TextureIntrinsicFloatInput; + def int_r600_txl : TextureIntrinsicFloatInput; + def int_r600_txlc : TextureIntrinsicFloatInput; + def int_r600_txb : TextureIntrinsicFloatInput; + def int_r600_txbc : TextureIntrinsicFloatInput; + def int_r600_txf : TextureIntrinsicInt32Input; + def int_r600_txq : TextureIntrinsicInt32Input; + def int_r600_ddx : TextureIntrinsicFloatInput; + def int_r600_ddy : TextureIntrinsicFloatInput; } Index: lib/Target/AMDGPU/R600TextureIntrinsicsReplacer.cpp =================================================================== --- lib/Target/AMDGPU/R600TextureIntrinsicsReplacer.cpp +++ lib/Target/AMDGPU/R600TextureIntrinsicsReplacer.cpp @@ -263,15 +263,15 @@ StringRef Name = I.getCalledFunction()->getName(); if (Name == "llvm.AMDGPU.tex") { - ReplaceTexIntrinsic(I, false, TexSign, "llvm.R600.tex", "llvm.R600.texc"); + ReplaceTexIntrinsic(I, false, TexSign, "llvm.r600.tex", "llvm.r600.texc"); return; } if (Name == "llvm.AMDGPU.txl") { - ReplaceTexIntrinsic(I, true, TexSign, "llvm.R600.txl", "llvm.R600.txlc"); + ReplaceTexIntrinsic(I, true, TexSign, "llvm.r600.txl", "llvm.r600.txlc"); return; } if (Name == "llvm.AMDGPU.txb") { - ReplaceTexIntrinsic(I, true, TexSign, "llvm.R600.txb", "llvm.R600.txbc"); + ReplaceTexIntrinsic(I, true, TexSign, "llvm.r600.txb", "llvm.r600.txbc"); return; } if (Name == "llvm.AMDGPU.txf") { @@ -279,15 +279,15 @@ return; } if (Name == "llvm.AMDGPU.txq") { - ReplaceTexIntrinsic(I, false, TexQSign, "llvm.R600.txq", "llvm.R600.txq"); + ReplaceTexIntrinsic(I, false, TexQSign, "llvm.r600.txq", "llvm.r600.txq"); return; } if (Name == "llvm.AMDGPU.ddx") { - ReplaceTexIntrinsic(I, false, TexSign, "llvm.R600.ddx", "llvm.R600.ddx"); + ReplaceTexIntrinsic(I, false, TexSign, "llvm.r600.ddx", "llvm.r600.ddx"); return; } if (Name == "llvm.AMDGPU.ddy") { - ReplaceTexIntrinsic(I, false, TexSign, "llvm.R600.ddy", "llvm.R600.ddy"); + ReplaceTexIntrinsic(I, false, TexSign, "llvm.r600.ddy", "llvm.r600.ddy"); return; } } Index: test/CodeGen/AMDGPU/tex-clause-antidep.ll =================================================================== --- test/CodeGen/AMDGPU/tex-clause-antidep.ll +++ test/CodeGen/AMDGPU/tex-clause-antidep.ll @@ -12,14 +12,14 @@ %6 = insertelement <4 x float> %5, float %2, i32 1 %7 = insertelement <4 x float> %6, float %3, i32 2 %8 = insertelement <4 x float> %7, float %4, i32 3 - %9 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) - %10 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %9 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %10 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %11 = fadd <4 x float> %9, %10 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 0, i32 0) ret void } -declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone +declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) -attributes #0 = { "ShaderType"="1" } \ No newline at end of file +attributes #0 = { "ShaderType"="1" } Index: test/CodeGen/AMDGPU/texture-input-merge.ll =================================================================== --- test/CodeGen/AMDGPU/texture-input-merge.ll +++ test/CodeGen/AMDGPU/texture-input-merge.ll @@ -16,16 +16,16 @@ %11 = insertelement <4 x float> undef, float %7, i32 0 %12 = insertelement <4 x float> %11, float %5, i32 1 %13 = insertelement <4 x float> undef, float %8, i32 0 - %14 = call <4 x float> @llvm.R600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) - %15 = call <4 x float> @llvm.R600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) - %16 = call <4 x float> @llvm.R600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %14 = call <4 x float> @llvm.r600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %15 = call <4 x float> @llvm.r600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %16 = call <4 x float> @llvm.r600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %17 = fadd <4 x float> %14, %15 %18 = fadd <4 x float> %17, %16 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 0) ret void } -declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone +declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) -attributes #0 = { "ShaderType"="1" } \ No newline at end of file +attributes #0 = { "ShaderType"="1" }