Index: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp =================================================================== --- lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -780,7 +780,8 @@ .addOperand(getLdStRegOp(RtMI)) .addOperand(getLdStRegOp(Rt2MI)) .addOperand(BaseRegOp) - .addImm(OffsetImm); + .addImm(OffsetImm) + .setMemRefs(I->mergeMemRefsWith(*Paired)); } (void)MIB; @@ -1264,7 +1265,8 @@ .addOperand(getLdStRegOp(Update)) .addOperand(getLdStRegOp(I)) .addOperand(getLdStBaseOp(I)) - .addImm(Value); + .addImm(Value) + .setMemRefs(I->memoperands_begin(), I->memoperands_end()); } else { // Paired instruction. int Scale = getMemScale(I); @@ -1273,7 +1275,8 @@ .addOperand(getLdStRegOp(I, 0)) .addOperand(getLdStRegOp(I, 1)) .addOperand(getLdStBaseOp(I)) - .addImm(Value / Scale); + .addImm(Value / Scale) + .setMemRefs(I->memoperands_begin(), I->memoperands_end()); } (void)MIB; Index: test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll =================================================================== --- test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll +++ test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A57 --check-prefix CHECK-EVEN -; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A57 --check-prefix CHECK-ODD -; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-EVEN -; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-ODD +; RUN: llc < %s -mcpu=cortex-a57 -enable-misched=false -enable-post-misched=false -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A57 --check-prefix CHECK-EVEN +; RUN: llc < %s -mcpu=cortex-a57 -enable-misched=false -enable-post-misched=false -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A57 --check-prefix CHECK-ODD +; RUN: llc < %s -mcpu=cortex-a53 -enable-misched=false -enable-post-misched=false -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-EVEN +; RUN: llc < %s -mcpu=cortex-a53 -enable-misched=false -enable-post-misched=false -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-ODD ; Test the AArch64A57FPLoadBalancing pass. This pass relies heavily on register allocation, so ; our test strategy is to: