Index: lib/Target/AMDGPU/AMDGPUISelLowering.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -991,19 +991,6 @@ return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1), Op.getOperand(2)); - case AMDGPUIntrinsic::AMDGPU_imax: - return DAG.getNode(ISD::SMAX, DL, VT, Op.getOperand(1), - Op.getOperand(2)); - case AMDGPUIntrinsic::AMDGPU_umax: - return DAG.getNode(ISD::UMAX, DL, VT, Op.getOperand(1), - Op.getOperand(2)); - case AMDGPUIntrinsic::AMDGPU_imin: - return DAG.getNode(ISD::SMIN, DL, VT, Op.getOperand(1), - Op.getOperand(2)); - case AMDGPUIntrinsic::AMDGPU_umin: - return DAG.getNode(ISD::UMIN, DL, VT, Op.getOperand(1), - Op.getOperand(2)); - case AMDGPUIntrinsic::AMDGPU_umul24: return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT, Op.getOperand(1), Op.getOperand(2)); @@ -3167,21 +3154,6 @@ return SDValue(); } -static void computeKnownBitsForMinMax(const SDValue Op0, - const SDValue Op1, - APInt &KnownZero, - APInt &KnownOne, - const SelectionDAG &DAG, - unsigned Depth) { - APInt Op0Zero, Op0One; - APInt Op1Zero, Op1One; - DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth); - DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth); - - KnownZero = Op0Zero & Op1Zero; - KnownOne = Op0One & Op1One; -} - void AMDGPUTargetLowering::computeKnownBitsForTargetNode( const SDValue Op, APInt &KnownZero, @@ -3198,22 +3170,6 @@ switch (Opc) { default: break; - case ISD::INTRINSIC_WO_CHAIN: { - // FIXME: The intrinsic should just use the node. - switch (cast(Op.getOperand(0))->getZExtValue()) { - case AMDGPUIntrinsic::AMDGPU_imax: - case AMDGPUIntrinsic::AMDGPU_umax: - case AMDGPUIntrinsic::AMDGPU_imin: - case AMDGPUIntrinsic::AMDGPU_umin: - computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2), - KnownZero, KnownOne, DAG, Depth); - break; - default: - break; - } - - break; - } case AMDGPUISD::CARRY: case AMDGPUISD::BORROW: { KnownZero = APInt::getHighBitsSet(32, 31); Index: lib/Target/AMDGPU/AMDGPUIntrinsics.td =================================================================== --- lib/Target/AMDGPU/AMDGPUIntrinsics.td +++ lib/Target/AMDGPU/AMDGPUIntrinsics.td @@ -50,10 +50,6 @@ def int_AMDGPU_trunc : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>; def int_AMDGPU_ddx : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_AMDGPU_ddy : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; - def int_AMDGPU_imax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; - def int_AMDGPU_imin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; - def int_AMDGPU_umax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; - def int_AMDGPU_umin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_AMDGPU_umul24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_AMDGPU_imul24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_AMDGPU_imad24 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; Index: test/CodeGen/AMDGPU/llvm.AMDGPU.imax.ll =================================================================== --- test/CodeGen/AMDGPU/llvm.AMDGPU.imax.ll +++ /dev/null @@ -1,33 +0,0 @@ -; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=SI %s - -; SI-LABEL: {{^}}vector_imax: -; SI: v_max_i32_e32 -define void @vector_imax(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 { -main_body: - %load = load i32, i32 addrspace(1)* %in, align 4 - %max = call i32 @llvm.AMDGPU.imax(i32 %p0, i32 %load) - %bc = bitcast i32 %max to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; SI-LABEL: {{^}}scalar_imax: -; SI: s_max_i32 -define void @scalar_imax(i32 %p0, i32 %p1) #0 { -entry: - %max = call i32 @llvm.AMDGPU.imax(i32 %p0, i32 %p1) - %bc = bitcast i32 %max to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; Function Attrs: readnone -declare i32 @llvm.AMDGPU.imax(i32, i32) #1 - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) - -attributes #0 = { nounwind } -attributes #1 = { nounwind readnone } - -!0 = !{!"const", null, i32 1} Index: test/CodeGen/AMDGPU/llvm.AMDGPU.imin.ll =================================================================== --- test/CodeGen/AMDGPU/llvm.AMDGPU.imin.ll +++ /dev/null @@ -1,33 +0,0 @@ -; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=SI %s - -; SI-LABEL: {{^}}vector_imin: -; SI: v_min_i32_e32 -define void @vector_imin(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 { -main_body: - %load = load i32, i32 addrspace(1)* %in, align 4 - %min = call i32 @llvm.AMDGPU.imin(i32 %p0, i32 %load) - %bc = bitcast i32 %min to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; SI-LABEL: {{^}}scalar_imin: -; SI: s_min_i32 -define void @scalar_imin(i32 %p0, i32 %p1) #0 { -entry: - %min = call i32 @llvm.AMDGPU.imin(i32 %p0, i32 %p1) - %bc = bitcast i32 %min to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; Function Attrs: readnone -declare i32 @llvm.AMDGPU.imin(i32, i32) #1 - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) - -attributes #0 = { nounwind } -attributes #1 = { nounwind readnone } - -!0 = !{!"const", null, i32 1} Index: test/CodeGen/AMDGPU/llvm.AMDGPU.umax.ll =================================================================== --- test/CodeGen/AMDGPU/llvm.AMDGPU.umax.ll +++ /dev/null @@ -1,48 +0,0 @@ -; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=SI %s - -; SI-LABEL: {{^}}vector_umax: -; SI: v_max_u32_e32 -define void @vector_umax(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 { -main_body: - %load = load i32, i32 addrspace(1)* %in, align 4 - %max = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %load) - %bc = bitcast i32 %max to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; SI-LABEL: {{^}}scalar_umax: -; SI: s_max_u32 -define void @scalar_umax(i32 %p0, i32 %p1) #0 { -entry: - %max = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %p1) - %bc = bitcast i32 %max to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; SI-LABEL: {{^}}trunc_zext_umax: -; SI: buffer_load_ubyte [[VREG:v[0-9]+]], -; SI: v_max_u32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]] -; SI-NOT: and -; SI: buffer_store_short [[RESULT]], -define void @trunc_zext_umax(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind { - %tmp5 = load i8, i8 addrspace(1)* %src, align 1 - %tmp2 = zext i8 %tmp5 to i32 - %tmp3 = tail call i32 @llvm.AMDGPU.umax(i32 %tmp2, i32 0) nounwind readnone - %tmp4 = trunc i32 %tmp3 to i8 - %tmp6 = zext i8 %tmp4 to i16 - store i16 %tmp6, i16 addrspace(1)* %out, align 2 - ret void -} - -; Function Attrs: readnone -declare i32 @llvm.AMDGPU.umax(i32, i32) #1 - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) - -attributes #0 = { nounwind } -attributes #1 = { nounwind readnone } - -!0 = !{!"const", null, i32 1} Index: test/CodeGen/AMDGPU/llvm.AMDGPU.umin.ll =================================================================== --- test/CodeGen/AMDGPU/llvm.AMDGPU.umin.ll +++ /dev/null @@ -1,48 +0,0 @@ -; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=SI %s - -; SI-LABEL: {{^}}vector_umin: -; SI: v_min_u32_e32 -define void @vector_umin(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 { -main_body: - %load = load i32, i32 addrspace(1)* %in, align 4 - %min = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %load) - %bc = bitcast i32 %min to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; SI-LABEL: {{^}}scalar_umin: -; SI: s_min_u32 -define void @scalar_umin(i32 %p0, i32 %p1) #0 { -entry: - %min = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %p1) - %bc = bitcast i32 %min to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; SI-LABEL: {{^}}trunc_zext_umin: -; SI: buffer_load_ubyte [[VREG:v[0-9]+]], -; SI: v_min_u32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]] -; SI-NOT: and -; SI: buffer_store_short [[RESULT]], -define void @trunc_zext_umin(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind { - %tmp5 = load i8, i8 addrspace(1)* %src, align 1 - %tmp2 = zext i8 %tmp5 to i32 - %tmp3 = tail call i32 @llvm.AMDGPU.umin(i32 %tmp2, i32 0) nounwind readnone - %tmp4 = trunc i32 %tmp3 to i8 - %tmp6 = zext i8 %tmp4 to i16 - store i16 %tmp6, i16 addrspace(1)* %out, align 2 - ret void -} - -; Function Attrs: readnone -declare i32 @llvm.AMDGPU.umin(i32, i32) #1 - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) - -attributes #0 = { nounwind } -attributes #1 = { nounwind readnone } - -!0 = !{!"const", null, i32 1} Index: test/CodeGen/AMDGPU/sext-in-reg.ll =================================================================== --- test/CodeGen/AMDGPU/sext-in-reg.ll +++ test/CodeGen/AMDGPU/sext-in-reg.ll @@ -458,7 +458,8 @@ define void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind { %tmp5 = load i8, i8 addrspace(1)* %src, align 1 %tmp2 = sext i8 %tmp5 to i32 - %tmp3 = tail call i32 @llvm.AMDGPU.imax(i32 %tmp2, i32 0) nounwind readnone + %tmp2.5 = icmp sgt i32 %tmp2, 0 + %tmp3 = select i1 %tmp2.5, i32 %tmp2, i32 0 %tmp4 = trunc i32 %tmp3 to i8 %tmp6 = sext i8 %tmp4 to i16 store i16 %tmp6, i16 addrspace(1)* %out, align 2