Index: lib/Target/Mips/MicroMipsDSPInstrFormats.td =================================================================== --- lib/Target/Mips/MicroMipsDSPInstrFormats.td +++ lib/Target/Mips/MicroMipsDSPInstrFormats.td @@ -242,3 +242,61 @@ let Inst{13-6} = op; let Inst{5-0} = 0b111100; } + +class POOL32A_2RBP_FMT : MMDSPInst { + bits<5> rt; + bits<5> rs; + bits<2> bp; + + let Inst{31-26} = 0; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-14} = bp; + let Inst{13-6} = 0b00100010; + let Inst{5-0} = 0b111100; +} + +class POOL32I_IMMB0_FMT op> : MMDSPInst { + bits<16> offset; + + let Inst{31-26} = 0b010000; + let Inst{25-21} = op; + let Inst{20-16} = 0; + let Inst{15-0} = offset; +} + +class POOL32A_2RB0_FMT op> : MMDSPInst { + bits<5> rt; + bits<5> rs; + + let Inst{31-26} = 0; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-10} = 0; + let Inst{9-0} = op; +} + +class POOL32S_3RB0_FMT op> : MMDSPInst { + bits<5> rt; + bits<5> rs; + bits<5> rd; + + let Inst{31-26} = 0b010110; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-11} = rd; + let Inst{10} = 0b0; + let Inst{9-0} = op; +} + +class POOL32A_2R2B0_FMT op> : MMDSPInst { + bits<5> rt; + bits<5> rs; + + let Inst{31-26} = 0; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-11} = 0; + let Inst{10} = 0; + let Inst{9-0} = op; +} Index: lib/Target/Mips/MicroMipsDSPInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsDSPInstrInfo.td +++ lib/Target/Mips/MicroMipsDSPInstrInfo.td @@ -155,6 +155,21 @@ class SHILO_MM_ENC : POOL32A_4B0SHIFT6AC4B0_FMT<"shilo", 0b0000011101>; class SHILOV_MM_ENC : POOL32A_5B01RAC_FMT<"shilov", 0b01001001>; class WRDSP_MM_ENC : POOL32A_1RMASK7_FMT<"wrdsp", 0b01011001>; +class BITREV_MM_ENC : POOL32A_2R_FMT<"bitrev", 0b0011000100>; +class BALIGN_MMR2_ENC : POOL32A_2RBP_FMT<"balign">; +class BPOSGE32_MM_ENC : POOL32I_IMMB0_FMT<"bposge32", 0b11011>; +class CMP_EQ_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.eq.ph", 0b0010000101>; +class CMP_LT_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.lt.ph", 0b0001000101>; +class CMP_LE_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.le.ph", 0b0000000101>; +class CMPGDU_EQ_QB_MMR2_ENC : POOL32A_3RB0_FMT<"cmpgdu.eq.qb", 0b0110000101>; +class CMPGDU_LT_QB_MMR2_ENC : POOL32A_3RB0_FMT<"cmpgdu.lt.qb", 0b0111000101>; +class CMPGDU_LE_QB_MMR2_ENC : POOL32A_3RB0_FMT<"cmpgdu.le.qb", 0b1000000101>; +class CMPGU_EQ_QB_MM_ENC : POOL32S_3RB0_FMT<"cmpgu.eq.qb", 0b0011000101>; +class CMPGU_LT_QB_MM_ENC : POOL32S_3RB0_FMT<"cmpgu.lt.qb", 0b0100000101>; +class CMPGU_LE_QB_MM_ENC : POOL32S_3RB0_FMT<"cmpgu.le.qb", 0b0101000101>; +class CMPU_EQ_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.eq.qb", 0b1001000101>; +class CMPU_LT_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.lt.qb", 0b1010000101>; +class CMPU_LE_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.le.qb", 0b1011000101>; // Instruction desc. class ABSQ_S_PH_MM_R2_DESC_BASE Pattern = [(set GPR32Opnd:$rt, (int_mips_balign GPR32Opnd:$src, + GPR32Opnd:$rs, + immZExt2:$bp))]; + InstrItinClass Itinerary = NoItinerary; + string Constraints = "$src = $rt"; +} + +class BITREV_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"bitrev", int_mips_bitrev, + NoItinerary, GPR32Opnd>; + +class BPOSGE32_MM_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget_mm, + NoItinerary>; + // Instruction defs. // microMIPS DSP Rev 1 def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC; @@ -472,6 +504,18 @@ def SHILO_MM : DspMMRel, SHILO_MM_ENC, SHILO_DESC; def SHILOV_MM : DspMMRel, SHILOV_MM_ENC, SHILOV_DESC; def WRDSP_MM : DspMMRel, WRDSP_MM_ENC, WRDSP_MM_DESC; +def BITREV_MM : DspMMRel, BITREV_MM_ENC, BITREV_MM_DESC; +def BPOSGE32_MM : DspMMRel, BPOSGE32_MM_ENC, BPOSGE32_MM_DESC, + ISA_MIPS1_NOT_32R6_64R6; +def CMP_EQ_PH_MM : DspMMRel, CMP_EQ_PH_MM_ENC, CMP_EQ_PH_DESC; +def CMP_LT_PH_MM : DspMMRel, CMP_LT_PH_MM_ENC, CMP_LT_PH_DESC; +def CMP_LE_PH_MM : DspMMRel, CMP_LE_PH_MM_ENC, CMP_LE_PH_DESC; +def CMPGU_EQ_QB_MM : DspMMRel, CMPGU_EQ_QB_MM_ENC, CMPGU_EQ_QB_DESC; +def CMPGU_LT_QB_MM : DspMMRel, CMPGU_LT_QB_MM_ENC, CMPGU_LT_QB_DESC; +def CMPGU_LE_QB_MM : DspMMRel, CMPGU_LE_QB_MM_ENC, CMPGU_LE_QB_DESC; +def CMPU_EQ_QB_MM : DspMMRel, CMPU_EQ_QB_MM_ENC, CMPU_EQ_QB_DESC; +def CMPU_LT_QB_MM : DspMMRel, CMPU_LT_QB_MM_ENC, CMPU_LT_QB_DESC; +def CMPU_LE_QB_MM : DspMMRel, CMPU_LE_QB_MM_ENC, CMPU_LE_QB_DESC; // microMIPS DSP Rev 2 def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC, ISA_DSPR2; @@ -495,6 +539,13 @@ def SHRAV_QB_MMR2 : DspMMRel, SHRAV_QB_MMR2_ENC, SHRAV_QB_MMR2_DESC, ISA_DSPR2; def SHRAV_R_QB_MMR2 : DspMMRel, SHRAV_R_QB_MMR2_ENC, SHRAV_R_QB_MMR2_DESC, ISA_DSPR2; +def BALIGN_MMR2 : DspMMRel, BALIGN_MMR2_ENC, BALIGN_MMR2_DESC, ISA_DSPR2; +def CMPGDU_EQ_QB_MMR2 : DspMMRel, CMPGDU_EQ_QB_MMR2_ENC, CMPGDU_EQ_QB_DESC, + ISA_DSPR2; +def CMPGDU_LT_QB_MMR2 : DspMMRel, CMPGDU_LT_QB_MMR2_ENC, CMPGDU_LT_QB_DESC, + ISA_DSPR2; +def CMPGDU_LE_QB_MMR2 : DspMMRel, CMPGDU_LE_QB_MMR2_ENC, CMPGDU_LE_QB_DESC, + ISA_DSPR2; def SHRL_PH_MMR2 : DspMMRel, SHRL_PH_MMR2_ENC, SHRL_PH_MMR2_DESC, ISA_DSPR2; def SHRLV_PH_MMR2 : DspMMRel, SHRLV_PH_MMR2_ENC, SHRLV_PH_MMR2_DESC, ISA_DSPR2; def SUBQH_PH_MMR2 : DspMMRel, SUBQH_PH_MMR2_ENC, SUBQH_PH_DESC, ISA_DSPR2; Index: lib/Target/Mips/MipsDSPInstrInfo.td =================================================================== --- lib/Target/Mips/MipsDSPInstrInfo.td +++ lib/Target/Mips/MipsDSPInstrInfo.td @@ -286,6 +286,7 @@ string AsmString = !strconcat(instr_asm, "\t$rs, $rt"); list Pattern = [(OpNode ROS:$rs, ROT:$rt)]; InstrItinClass Itinerary = itin; + string BaseOpcode = instr_asm; } class CMP_EQ_QB_R3_DESC_BASE { +class BPOSGE32_DESC_BASE { dag OutOperandList = (outs); - dag InOperandList = (ins brtarget:$offset); + dag InOperandList = (ins opnd:$offset); string AsmString = !strconcat(instr_asm, "\t$offset"); InstrItinClass Itinerary = itin; bit isBranch = 1; bit isTerminator = 1; bit hasDelaySlot = 1; + string BaseOpcode = instr_asm; } class INSV_DESC_BASE; -class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>; +class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget, NoItinerary>; // Extr class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>, @@ -1177,16 +1180,16 @@ def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC; def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC; def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC; -def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC; -def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC; -def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC; -def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC; -def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC; -def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC; -def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC; -def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC; -def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC; -def BITREV : BITREV_ENC, BITREV_DESC; +def CMPU_EQ_QB : DspMMRel, CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC; +def CMPU_LT_QB : DspMMRel, CMPU_LT_QB_ENC, CMPU_LT_QB_DESC; +def CMPU_LE_QB : DspMMRel, CMPU_LE_QB_ENC, CMPU_LE_QB_DESC; +def CMPGU_EQ_QB : DspMMRel, CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC; +def CMPGU_LT_QB : DspMMRel, CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC; +def CMPGU_LE_QB : DspMMRel, CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC; +def CMP_EQ_PH : DspMMRel, CMP_EQ_PH_ENC, CMP_EQ_PH_DESC; +def CMP_LT_PH : DspMMRel, CMP_LT_PH_ENC, CMP_LT_PH_DESC; +def CMP_LE_PH : DspMMRel, CMP_LE_PH_ENC, CMP_LE_PH_DESC; +def BITREV : DspMMRel, BITREV_ENC, BITREV_DESC; def PACKRL_PH : DspMMRel, PACKRL_PH_ENC, PACKRL_PH_DESC; def REPL_QB : DspMMRel, REPL_QB_ENC, REPL_QB_DESC; def REPL_PH : DspMMRel, REPL_PH_ENC, REPL_PH_DESC; @@ -1197,7 +1200,9 @@ def LWX : DspMMRel, LWX_ENC, LWX_DESC; def LHX : DspMMRel, LHX_ENC, LHX_DESC; def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC; -def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC; +let AdditionalPredicates = [NotInMicroMips] in { + def BPOSGE32 : DspMMRel, BPOSGE32_ENC, BPOSGE32_DESC; +} def INSV : DspMMRel, INSV_ENC, INSV_DESC; def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC; def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC; @@ -1224,9 +1229,9 @@ def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC, ISA_DSPR2; def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC, ISA_DSPR2; def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC, ISA_DSPR2; -def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC, ISA_DSPR2; -def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC, ISA_DSPR2; -def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC, ISA_DSPR2; +def CMPGDU_EQ_QB : DspMMRel, CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC, ISA_DSPR2; +def CMPGDU_LT_QB : DspMMRel, CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC, ISA_DSPR2; +def CMPGDU_LE_QB : DspMMRel, CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC, ISA_DSPR2; def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC, ISA_DSPR2; def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC, ISA_DSPR2; def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC, ISA_DSPR2; @@ -1264,7 +1269,7 @@ def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC, ISA_DSPR2; def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC, ISA_DSPR2; def APPEND : APPEND_ENC, APPEND_DESC, ISA_DSPR2; -def BALIGN : BALIGN_ENC, BALIGN_DESC, ISA_DSPR2; +def BALIGN : DspMMRel, BALIGN_ENC, BALIGN_DESC, ISA_DSPR2; def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC, ISA_DSPR2; // Pseudos. Index: test/MC/Disassembler/Mips/micromips-dsp/valid-micromips32r3.txt =================================================================== --- /dev/null +++ test/MC/Disassembler/Mips/micromips-dsp/valid-micromips32r3.txt @@ -0,0 +1,3 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r3 -mattr=micromips -mattr=+dsp | FileCheck %s + +0x43 0x60 0x00 0xab # CHECK: bposge32 342 Index: test/MC/Disassembler/Mips/micromips-dsp/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips-dsp/valid.txt +++ test/MC/Disassembler/Mips/micromips-dsp/valid.txt @@ -101,3 +101,13 @@ 0x00 0x01 0x82 0x7c # CHECK: mthlip $1, $ac2 0x00 0xa7 0xd6 0x7c # CHECK: wrdsp $5 0x00 0xa0 0x96 0x7c # CHECK: wrdsp $5, 2 +0x00 0x43 0x31 0x3c # CHECK: bitrev $2, $3 +0x00 0x62 0x00 0x85 # CHECK: cmp.eq.ph $2, $3 +0x00 0x62 0x00 0x45 # CHECK: cmp.lt.ph $2, $3 +0x00 0x62 0x00 0x05 # CHECK: cmp.le.ph $2, $3 +0x58 0x62 0x08 0xc5 # CHECK: cmpgu.eq.qb $1, $2, $3 +0x58 0x62 0x09 0x05 # CHECK: cmpgu.lt.qb $1, $2, $3 +0x58 0x62 0x09 0x45 # CHECK: cmpgu.le.qb $1, $2, $3 +0x00 0x41 0x02 0x45 # CHECK: cmpu.eq.qb $1, $2 +0x00 0x41 0x02 0x85 # CHECK: cmpu.lt.qb $1, $2 +0x00 0x41 0x02 0xc5 # CHECK: cmpu.le.qb $1, $2 Index: test/MC/Disassembler/Mips/micromips-dspr2/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips-dspr2/valid.txt +++ test/MC/Disassembler/Mips/micromips-dspr2/valid.txt @@ -123,3 +123,17 @@ 0x00 0x22 0x1a 0x55 # CHECK: prepend $1, $2, 3 0x00 0xa7 0xd6 0x7c # CHECK: wrdsp $5 0x00 0xa0 0x96 0x7c # CHECK: wrdsp $5, 2 +0x00 0x43 0xc8 0xbc # CHECK: balign $2, $3, 3 +0x00 0x43 0x31 0x3c # CHECK: bitrev $2, $3 +0x00 0x62 0x00 0x85 # CHECK: cmp.eq.ph $2, $3 +0x00 0x62 0x00 0x45 # CHECK: cmp.lt.ph $2, $3 +0x00 0x62 0x00 0x05 # CHECK: cmp.le.ph $2, $3 +0x00 0x62 0x09 0x85 # CHECK: cmpgdu.eq.qb $1, $2, $3 +0x00 0x62 0x09 0xc5 # CHECK: cmpgdu.lt.qb $1, $2, $3 +0x00 0x62 0x0a 0x05 # CHECK: cmpgdu.le.qb $1, $2, $3 +0x58 0x62 0x08 0xc5 # CHECK: cmpgu.eq.qb $1, $2, $3 +0x58 0x62 0x09 0x05 # CHECK: cmpgu.lt.qb $1, $2, $3 +0x58 0x62 0x09 0x45 # CHECK: cmpgu.le.qb $1, $2, $3 +0x00 0x41 0x02 0x45 # CHECK: cmpu.eq.qb $1, $2 +0x00 0x41 0x02 0x85 # CHECK: cmpu.lt.qb $1, $2 +0x00 0x41 0x02 0xc5 # CHECK: cmpu.le.qb $1, $2 Index: test/MC/Mips/micromips-dsp/invalid.s =================================================================== --- test/MC/Mips/micromips-dsp/invalid.s +++ test/MC/Mips/micromips-dsp/invalid.s @@ -21,3 +21,5 @@ shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shilo $ac1, 64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate shilo $ac1, -64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate + # bposge32 is microMIPS DSP instruction but it is removed in Release 6 + bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled Index: test/MC/Mips/micromips-dsp/valid-micromips32r3.s =================================================================== --- /dev/null +++ test/MC/Mips/micromips-dsp/valid-micromips32r3.s @@ -0,0 +1,4 @@ +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 -mattr=micromips -mattr=+dsp | FileCheck %s + + .set noat + bposge32 342 # CHECK: bposge32 342 # encoding: [0x43,0x60,0x00,0xab] Index: test/MC/Mips/micromips-dsp/valid.s =================================================================== --- test/MC/Mips/micromips-dsp/valid.s +++ test/MC/Mips/micromips-dsp/valid.s @@ -103,3 +103,13 @@ wrdsp $5 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c] wrdsp $5, 2 # CHECK: wrdsp $5, 2 # encoding: [0x00,0xa0,0x96,0x7c] wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c] + bitrev $2, $3 # CHECK: bitrev $2, $3 # encoding: [0x00,0x43,0x31,0x3c] + cmp.eq.ph $2, $3 # CHECK: cmp.eq.ph $2, $3 # encoding: [0x00,0x62,0x00,0x85] + cmp.lt.ph $2, $3 # CHECK: cmp.lt.ph $2, $3 # encoding: [0x00,0x62,0x00,0x45] + cmp.le.ph $2, $3 # CHECK: cmp.le.ph $2, $3 # encoding: [0x00,0x62,0x00,0x05] + cmpgu.eq.qb $1, $2, $3 # CHECK: cmpgu.eq.qb $1, $2, $3 # encoding: [0x58,0x62,0x08,0xc5] + cmpgu.lt.qb $1, $2, $3 # CHECK: cmpgu.lt.qb $1, $2, $3 # encoding: [0x58,0x62,0x09,0x05] + cmpgu.le.qb $1, $2, $3 # CHECK: cmpgu.le.qb $1, $2, $3 # encoding: [0x58,0x62,0x09,0x45] + cmpu.eq.qb $1, $2 # CHECK: cmpu.eq.qb $1, $2 # encoding: [0x00,0x41,0x02,0x45] + cmpu.lt.qb $1, $2 # CHECK: cmpu.lt.qb $1, $2 # encoding: [0x00,0x41,0x02,0x85] + cmpu.le.qb $1, $2 # CHECK: cmpu.le.qb $1, $2 # encoding: [0x00,0x41,0x02,0xc5] Index: test/MC/Mips/micromips-dspr2/invalid.s =================================================================== --- test/MC/Mips/micromips-dspr2/invalid.s +++ test/MC/Mips/micromips-dspr2/invalid.s @@ -1,9 +1,13 @@ # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 2>%t1 # RUN: FileCheck %s < %t1 + balign $2, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate + balign $2, $3, 4 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate shra.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shra.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shra_r.qb $3, $4, 8 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate shra_r.qb $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate shrl.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate shrl.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate + # bposge32 is microMIPS DSP instruction but it is removed in Release 6 + bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled Index: test/MC/Mips/micromips-dspr2/valid.s =================================================================== --- test/MC/Mips/micromips-dspr2/valid.s +++ test/MC/Mips/micromips-dspr2/valid.s @@ -125,3 +125,17 @@ wrdsp $5 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c] wrdsp $5, 2 # CHECK: wrdsp $5, 2 # encoding: [0x00,0xa0,0x96,0x7c] wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c] + balign $2, $3, 3 # CHECK: balign $2, $3, 3 # encoding: [0x00,0x43,0xc8,0xbc] + bitrev $2, $3 # CHECK: bitrev $2, $3 # encoding: [0x00,0x43,0x31,0x3c] + cmp.eq.ph $2, $3 # CHECK: cmp.eq.ph $2, $3 # encoding: [0x00,0x62,0x00,0x85] + cmp.lt.ph $2, $3 # CHECK: cmp.lt.ph $2, $3 # encoding: [0x00,0x62,0x00,0x45] + cmp.le.ph $2, $3 # CHECK: cmp.le.ph $2, $3 # encoding: [0x00,0x62,0x00,0x05] + cmpgdu.eq.qb $1, $2, $3 # CHECK: cmpgdu.eq.qb $1, $2, $3 # encoding: [0x00,0x62,0x09,0x85] + cmpgdu.lt.qb $1, $2, $3 # CHECK: cmpgdu.lt.qb $1, $2, $3 # encoding: [0x00,0x62,0x09,0xc5] + cmpgdu.le.qb $1, $2, $3 # CHECK: cmpgdu.le.qb $1, $2, $3 # encoding: [0x00,0x62,0x0a,0x05] + cmpgu.eq.qb $1, $2, $3 # CHECK: cmpgu.eq.qb $1, $2, $3 # encoding: [0x58,0x62,0x08,0xc5] + cmpgu.lt.qb $1, $2, $3 # CHECK: cmpgu.lt.qb $1, $2, $3 # encoding: [0x58,0x62,0x09,0x05] + cmpgu.le.qb $1, $2, $3 # CHECK: cmpgu.le.qb $1, $2, $3 # encoding: [0x58,0x62,0x09,0x45] + cmpu.eq.qb $1, $2 # CHECK: cmpu.eq.qb $1, $2 # encoding: [0x00,0x41,0x02,0x45] + cmpu.lt.qb $1, $2 # CHECK: cmpu.lt.qb $1, $2 # encoding: [0x00,0x41,0x02,0x85] + cmpu.le.qb $1, $2 # CHECK: cmpu.le.qb $1, $2 # encoding: [0x00,0x41,0x02,0xc5] Index: test/MC/Mips/micromips32r6/invalid.s =================================================================== --- test/MC/Mips/micromips32r6/invalid.s +++ test/MC/Mips/micromips32r6/invalid.s @@ -196,3 +196,5 @@ swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset + # bposge32 is microMIPS DSP instruction + bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled Index: test/MC/Mips/micromips64r6/invalid.s =================================================================== --- test/MC/Mips/micromips64r6/invalid.s +++ test/MC/Mips/micromips64r6/invalid.s @@ -236,3 +236,5 @@ dsra $4, $5, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate dsra32 $4, $5, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate dsra32 $4, $5, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate + # bposge32 is microMIPS DSP instruction + bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled