Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp =================================================================== --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -1803,7 +1803,16 @@ unsigned Offset, uint64_t Address, const void *Decoder) { - int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; + int32_t BranchOffset; + switch(Inst.getOpcode()) { + default: + BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; + break; + case Mips::BPOSGE32_MM: + BranchOffset = (SignExtend32<16>(Offset) * 2); + break; + } + Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -224,6 +224,13 @@ const MCOperand &MO = MI.getOperand(OpNo); + if (MO.isImm()) { + if (MI.getOpcode() == Mips::BPOSGE32_MM) + return MO.getImm() >> 1; + else + return MO.getImm() >> 2; + } + // If the destination is an immediate, divide by 4. if (MO.isImm()) return MO.getImm() >> 2; Index: lib/Target/Mips/MicroMipsDSPInstrFormats.td =================================================================== --- lib/Target/Mips/MicroMipsDSPInstrFormats.td +++ lib/Target/Mips/MicroMipsDSPInstrFormats.td @@ -242,3 +242,62 @@ let Inst{13-6} = op; let Inst{5-0} = 0b111100; } + +class POOL32A_2RBP_FMT : MMDSPInst { + bits<5> rt; + bits<5> rs; + bits<2> bp; + + let Inst{31-26} = 0; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-14} = bp; + let Inst{13-6} = 0b00100010; + let Inst{5-0} = 0b111100; +} + +class POOL32I_IMMB0_FMT op> : MMDSPInst { + bits<16> offset; + + let Inst{31-26} = 0b010000; + let Inst{25-21} = op; + let Inst{20-16} = 0; + let Inst{15-0} = offset; +} + +class POOL32A_2RB0_FMT op> : MMDSPInst { + bits<5> rt; + bits<5> rs; + + let Inst{31-26} = 0; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-10} = 0; + let Inst{9-0} = op; +} + +class POOL32_3RB0POOL_FMT pool, bits<10> op> + : MMDSPInst { + bits<5> rt; + bits<5> rs; + bits<5> rd; + + let Inst{31-26} = pool; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-11} = rd; + let Inst{10} = 0b0; + let Inst{9-0} = op; +} + +class POOL32A_2R2B0_FMT op> : MMDSPInst { + bits<5> rt; + bits<5> rs; + + let Inst{31-26} = 0; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-11} = 0; + let Inst{10} = 0; + let Inst{9-0} = op; +} Index: lib/Target/Mips/MicroMipsDSPInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsDSPInstrInfo.td +++ lib/Target/Mips/MicroMipsDSPInstrInfo.td @@ -155,6 +155,27 @@ class SHILO_MM_ENC : POOL32A_4B0SHIFT6AC4B0_FMT<"shilo", 0b0000011101>; class SHILOV_MM_ENC : POOL32A_5B01RAC_FMT<"shilov", 0b01001001>; class WRDSP_MM_ENC : POOL32A_1RMASK7_FMT<"wrdsp", 0b01011001>; +class BITREV_MM_ENC : POOL32A_2R_FMT<"bitrev", 0b0011000100>; +class BALIGN_MMR2_ENC : POOL32A_2RBP_FMT<"balign">; +class BPOSGE32_MM_ENC : POOL32I_IMMB0_FMT<"bposge32", 0b11011>; +class CMP_EQ_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.eq.ph", 0b0010000101>; +class CMP_LT_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.lt.ph", 0b0001000101>; +class CMP_LE_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.le.ph", 0b0000000101>; +class CMPGDU_EQ_QB_MMR2_ENC + : POOL32_3RB0POOL_FMT<"cmpgdu.eq.qb", 0, 0b0110000101>; +class CMPGDU_LT_QB_MMR2_ENC + : POOL32_3RB0POOL_FMT<"cmpgdu.lt.qb", 0, 0b0111000101>; +class CMPGDU_LE_QB_MMR2_ENC + : POOL32_3RB0POOL_FMT<"cmpgdu.le.qb", 0, 0b1000000101>; +class CMPGU_EQ_QB_MM_ENC + : POOL32_3RB0POOL_FMT<"cmpgu.eq.qb", 0b010110, 0b0011000101>; +class CMPGU_LT_QB_MM_ENC + : POOL32_3RB0POOL_FMT<"cmpgu.lt.qb", 0b010110, 0b0100000101>; +class CMPGU_LE_QB_MM_ENC + : POOL32_3RB0POOL_FMT<"cmpgu.le.qb", 0b010110, 0b0101000101>; +class CMPU_EQ_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.eq.qb", 0b1001000101>; +class CMPU_LT_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.lt.qb", 0b1010000101>; +class CMPU_LE_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.le.qb", 0b1011000101>; // Instruction desc. class ABSQ_S_PH_MM_R2_DESC_BASE { + dag OutOperandList = (outs GPR32Opnd:$rt); + dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$bp, GPR32Opnd:$src); + string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $bp"); + list Pattern = [(set GPR32Opnd:$rt, + (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, Imm:$bp))]; + InstrItinClass Itinerary = itin; + string Constraints = "$src = $rt"; +} + +class BALIGN_MMR2_DESC : BALIGN_MM_R2_DESC_BASE<"balign", int_mips_balign, + uimm2, immZExt2, NoItinerary>; + +class BITREV_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"bitrev", int_mips_bitrev, + NoItinerary, GPR32Opnd>; + +class BPOSGE32_MM_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>; + // Instruction defs. // microMIPS DSP Rev 1 def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC; @@ -472,6 +513,17 @@ def SHILO_MM : DspMMRel, SHILO_MM_ENC, SHILO_DESC; def SHILOV_MM : DspMMRel, SHILOV_MM_ENC, SHILOV_DESC; def WRDSP_MM : DspMMRel, WRDSP_MM_ENC, WRDSP_MM_DESC; +def BITREV_MM : DspMMRel, BITREV_MM_ENC, BITREV_MM_DESC; +def BPOSGE32_MM : DspMMRel, BPOSGE32_MM_ENC, BPOSGE32_MM_DESC; +def CMP_EQ_PH_MM : DspMMRel, CMP_EQ_PH_MM_ENC, CMP_EQ_PH_DESC; +def CMP_LT_PH_MM : DspMMRel, CMP_LT_PH_MM_ENC, CMP_LT_PH_DESC; +def CMP_LE_PH_MM : DspMMRel, CMP_LE_PH_MM_ENC, CMP_LE_PH_DESC; +def CMPGU_EQ_QB_MM : DspMMRel, CMPGU_EQ_QB_MM_ENC, CMPGU_EQ_QB_DESC; +def CMPGU_LT_QB_MM : DspMMRel, CMPGU_LT_QB_MM_ENC, CMPGU_LT_QB_DESC; +def CMPGU_LE_QB_MM : DspMMRel, CMPGU_LE_QB_MM_ENC, CMPGU_LE_QB_DESC; +def CMPU_EQ_QB_MM : DspMMRel, CMPU_EQ_QB_MM_ENC, CMPU_EQ_QB_DESC; +def CMPU_LT_QB_MM : DspMMRel, CMPU_LT_QB_MM_ENC, CMPU_LT_QB_DESC; +def CMPU_LE_QB_MM : DspMMRel, CMPU_LE_QB_MM_ENC, CMPU_LE_QB_DESC; // microMIPS DSP Rev 2 def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC, ISA_DSPR2; @@ -495,6 +547,13 @@ def SHRAV_QB_MMR2 : DspMMRel, SHRAV_QB_MMR2_ENC, SHRAV_QB_MMR2_DESC, ISA_DSPR2; def SHRAV_R_QB_MMR2 : DspMMRel, SHRAV_R_QB_MMR2_ENC, SHRAV_R_QB_MMR2_DESC, ISA_DSPR2; +def BALIGN_MMR2 : DspMMRel, BALIGN_MMR2_ENC, BALIGN_MMR2_DESC, ISA_DSPR2; +def CMPGDU_EQ_QB_MMR2 : DspMMRel, CMPGDU_EQ_QB_MMR2_ENC, CMPGDU_EQ_QB_DESC, + ISA_DSPR2; +def CMPGDU_LT_QB_MMR2 : DspMMRel, CMPGDU_LT_QB_MMR2_ENC, CMPGDU_LT_QB_DESC, + ISA_DSPR2; +def CMPGDU_LE_QB_MMR2 : DspMMRel, CMPGDU_LE_QB_MMR2_ENC, CMPGDU_LE_QB_DESC, + ISA_DSPR2; def SHRL_PH_MMR2 : DspMMRel, SHRL_PH_MMR2_ENC, SHRL_PH_MMR2_DESC, ISA_DSPR2; def SHRLV_PH_MMR2 : DspMMRel, SHRLV_PH_MMR2_ENC, SHRLV_PH_MMR2_DESC, ISA_DSPR2; def SUBQH_PH_MMR2 : DspMMRel, SUBQH_PH_MMR2_ENC, SUBQH_PH_DESC, ISA_DSPR2; Index: lib/Target/Mips/MipsDSPInstrInfo.td =================================================================== --- lib/Target/Mips/MipsDSPInstrInfo.td +++ lib/Target/Mips/MipsDSPInstrInfo.td @@ -287,6 +287,7 @@ string AsmString = !strconcat(instr_asm, "\t$rs, $rt"); list Pattern = [(OpNode ROS:$rs, ROT:$rt)]; InstrItinClass Itinerary = itin; + string BaseOpcode = instr_asm; } class CMP_EQ_QB_R3_DESC_BASE%t1 # RUN: FileCheck %s < %t1 + balign $2, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate + balign $2, $3, 4 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate shra.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shra.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shra_r.qb $3, $4, 8 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate Index: test/MC/Mips/micromips-dspr2/valid.s =================================================================== --- test/MC/Mips/micromips-dspr2/valid.s +++ test/MC/Mips/micromips-dspr2/valid.s @@ -125,3 +125,18 @@ wrdsp $5 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c] wrdsp $5, 2 # CHECK: wrdsp $5, 2 # encoding: [0x00,0xa0,0x96,0x7c] wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c] + bitrev $2, $3 # CHECK: bitrev $2, $3 # encoding: [0x00,0x43,0x31,0x3c] + bposge32 342 # CHECK: bposge32 342 # encoding: [0x43,0x60,0x00,0xab] + cmp.eq.ph $2, $3 # CHECK: cmp.eq.ph $2, $3 # encoding: [0x00,0x62,0x00,0x85] + cmp.lt.ph $2, $3 # CHECK: cmp.lt.ph $2, $3 # encoding: [0x00,0x62,0x00,0x45] + cmp.le.ph $2, $3 # CHECK: cmp.le.ph $2, $3 # encoding: [0x00,0x62,0x00,0x05] + cmpgu.eq.qb $1, $2, $3 # CHECK: cmpgu.eq.qb $1, $2, $3 # encoding: [0x58,0x62,0x08,0xc5] + cmpgu.lt.qb $1, $2, $3 # CHECK: cmpgu.lt.qb $1, $2, $3 # encoding: [0x58,0x62,0x09,0x05] + cmpgu.le.qb $1, $2, $3 # CHECK: cmpgu.le.qb $1, $2, $3 # encoding: [0x58,0x62,0x09,0x45] + cmpu.eq.qb $1, $2 # CHECK: cmpu.eq.qb $1, $2 # encoding: [0x00,0x41,0x02,0x45] + cmpu.lt.qb $1, $2 # CHECK: cmpu.lt.qb $1, $2 # encoding: [0x00,0x41,0x02,0x85] + cmpu.le.qb $1, $2 # CHECK: cmpu.le.qb $1, $2 # encoding: [0x00,0x41,0x02,0xc5] + balign $2, $3, 3 # CHECK: balign $2, $3, 3 # encoding: [0x00,0x43,0xc8,0xbc] + cmpgdu.eq.qb $1, $2, $3 # CHECK: cmpgdu.eq.qb $1, $2, $3 # encoding: [0x00,0x62,0x09,0x85] + cmpgdu.lt.qb $1, $2, $3 # CHECK: cmpgdu.lt.qb $1, $2, $3 # encoding: [0x00,0x62,0x09,0xc5] + cmpgdu.le.qb $1, $2, $3 # CHECK: cmpgdu.le.qb $1, $2, $3 # encoding: [0x00,0x62,0x0a,0x05]