Index: lib/Target/PowerPC/PPC.td
===================================================================
--- lib/Target/PowerPC/PPC.td
+++ lib/Target/PowerPC/PPC.td
@@ -124,6 +124,9 @@
 def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
                                         "Enable POWER8 vector instructions",
                                         [FeatureVSX, FeatureP8Altivec]>;
+def FeatureP9        : SubtargetFeature<"power9", "IsP9", "true",
+                                        "Enable POWER9 instructions",
+                                        [FeatureP8Crypto, FeatureP8Vector]>;
 def FeatureDirectMove :
   SubtargetFeature<"direct-move", "HasDirectMove", "true",
                    "Enable Power8 direct move instructions",
Index: lib/Target/PowerPC/PPCInstrFormats.td
===================================================================
--- lib/Target/PowerPC/PPCInstrFormats.td
+++ lib/Target/PowerPC/PPCInstrFormats.td
@@ -678,6 +678,14 @@
   let Inst{31}    = RC;
 }
 
+// [PO VRT XO VRB XO /]
+// [PO VRT XO VRB XO RC]
+class XForm_44<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
+               string asmstr, InstrItinClass itin, list<dag> pattern>
+  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
+  let A = xo2;
+}
+
 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
               InstrItinClass itin, list<dag> pattern>
   : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
Index: lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- lib/Target/PowerPC/PPCInstrVSX.td
+++ lib/Target/PowerPC/PPCInstrVSX.td
@@ -1216,6 +1216,64 @@
 } // AddedComplexity = 400
 } // HasP8Vector
 
+// The following VSX instructions were introduced in Power ISA 3.0
+def P9Instrs : Predicate<"PPCSubTarget->isP9()">;
+let Predicates = [P9Instrs] in {
+  // Scalar Copy Sign Quad-Precision
+  def XSCPSGNQP : XForm_18<63, 100,
+                      (outs vrrc:$vT), (ins vrrc:$vA, vrrc:$vB),
+                      "xscpsgnqp $vT, $vA, $vB", IIC_VecFP,
+                      []>; // TODO: map to llvm fcopysign?
+
+  // X44 is used for: Scalar Move, FP-FP Conversion Instructions
+  // TODO: Add intrinsic support, like "class VX1_Int_Ty" in PPCInstrAltivec.td
+  class X44<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc>
+    : XForm_44<opcode, xo2, xo, (outs vrrc:$vT), (ins vrrc:$vB),
+               !strconcat(opc, " $vT, $vB"), IIC_VecFP, []>;
+
+  // Scalar Absolute/Negative Absolute/Negate Quad-Precision
+  def XSABSQP   : X44<63,  0, 804, "xsabsqp">;
+  def XSNABSQP  : X44<63,  8, 804, "xsnabsqp">;
+  def XSNEGQP   : X44<63, 16, 804, "xsnegqp">;
+
+  //----------------------------------------------------------------------------
+  // Floating-Point Arithmetic Instructions:
+
+  // X1 is used for: Scalar Quad-Precision Elementary/Multiply-Add Arithmetic
+  // TODO: Add intrinsic support, or map to llvm instruction
+  class X1<bits<6> opcode, bits<10> xo, string opc>
+    : XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vA, vrrc:$vB),
+              !strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, []>;
+
+  class X1Ro<bits<6> opcode, bits<10> xo, string opc>
+    : XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vA, vrrc:$vB),
+              !strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, []> {
+    let RC = 1;
+  }
+
+  // Scalar Add/Divide/Multiply/Square-Root/Subtract Quad-Precision
+  def XSADDQP   : X1  <63,   4, "xsaddqp">;
+  def XSADDQPO  : X1Ro<63,   4, "xsaddqpo">;
+  def XSDIVQP   : X1  <63, 548, "xsdivqp">;
+  def XSDIVQPO  : X1Ro<63, 548, "xsdivqpo">;
+  def XSMULQP   : X1  <63,  36, "xsmulqp">;
+  def XSMULQPO  : X1Ro<63,  36, "xsmulqpo">;
+  def XSSQRTQP  : X1  <63, 804, "xssqrtqp">;
+  def XSSQRTQPO : X1Ro<63, 804, "xssqrtqpo">;
+  def XSSUBQP   : X1  <63, 516, "xssubqp">;
+  def XSSUBQPO  : X1Ro<63, 516, "xssubqpo">;
+
+  // Scalar (Negative) Multiply-Add/Subtract Quad-Precision
+  def XSMADDQP  : X1  <63, 388, "xsmaddqp">;
+  def XSMADDQPO : X1Ro<63, 388, "xsmaddqpo">;
+  def XSMSUBQP  : X1  <63, 420, "xsmsubqp">;
+  def XSMSUBQPO : X1Ro<63, 420, "xsmsubqpo">;
+  def XSNMADDQP : X1  <63, 452, "xsnmaddqp">;
+  def XSNMADDQPO: X1Ro<63, 452, "xsnmaddqpo">;
+  def XSNMSUBQP : X1  <63, 484, "xsnmsubqp">;
+  def XSNMSUBQPO: X1Ro<63, 484, "xsnmsubqpo">;
+}
+
 let Predicates = [HasDirectMove, HasVSX] in {
   // VSX direct move instructions
   def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
Index: lib/Target/PowerPC/PPCSubtarget.h
===================================================================
--- lib/Target/PowerPC/PPCSubtarget.h
+++ lib/Target/PowerPC/PPCSubtarget.h
@@ -111,6 +111,7 @@
   bool IsE500;
   bool IsPPC4xx;
   bool IsPPC6xx;
+  bool IsP9;
   bool FeatureMFTB;
   bool DeprecatedDST;
   bool HasLazyResolverStubs;
@@ -241,6 +242,7 @@
   bool isPPC4xx() const { return IsPPC4xx; }
   bool isPPC6xx() const { return IsPPC6xx; }
   bool isE500() const { return IsE500; }
+  bool isP9() const { return IsP9; }
   bool isFeatureMFTB() const { return FeatureMFTB; }
   bool isDeprecatedDST() const { return DeprecatedDST; }
   bool hasICBT() const { return HasICBT; }
Index: lib/Target/PowerPC/PPCSubtarget.cpp
===================================================================
--- lib/Target/PowerPC/PPCSubtarget.cpp
+++ lib/Target/PowerPC/PPCSubtarget.cpp
@@ -92,6 +92,7 @@
   IsPPC4xx = false;
   IsPPC6xx = false;
   IsE500 = false;
+  IsP9 = false;
   FeatureMFTB = false;
   DeprecatedDST = false;
   HasLazyResolverStubs = false;
Index: test/MC/Disassembler/PowerPC/vsx.txt
===================================================================
--- test/MC/Disassembler/PowerPC/vsx.txt
+++ test/MC/Disassembler/PowerPC/vsx.txt
@@ -539,3 +539,71 @@
 
 # CHECK: mtvsrwz 0, 3
 0x7c 0x03 0x01 0xe6
+
+# Power9 Instructions:
+
+# CHECK: xscpsgnqp 7, 31, 27
+0xfc 0xff 0xd8 0xc8
+
+# CHECK: xsabsqp 7, 27
+0xfc 0xe0 0xde 0x48
+
+# CHECK: xsnegqp 7, 27
+0xfc 0xf0 0xde 0x48
+
+# CHECK: xsnabsqp 7, 27
+0xfc 0xe8 0xde 0x48
+
+# CHECK: xsaddqp 7, 31, 27
+0xfc 0xff 0xd8 0x08
+
+# CHECK: xsaddqpo 7, 31, 27
+0xfc 0xff 0xd8 0x09
+
+# CHECK: xsdivqp 7, 31, 27
+0xfc 0xff 0xdc 0x48
+
+# CHECK: xsdivqpo 7, 31, 27
+0xfc 0xff 0xdc 0x49
+
+# CHECK: xsmulqp 7, 31, 27
+0xfc 0xff 0xd8 0x48
+
+# CHECK: xsmulqpo 7, 31, 27
+0xfc 0xff 0xd8 0x49
+
+# CHECK: xssqrtqp 7, 31, 27
+0xfc 0xff 0xde 0x48
+
+# CHECK: xssqrtqpo 7, 31, 27
+0xfc 0xff 0xde 0x49
+
+# CHECK: xssubqp 7, 31, 27
+0xfc 0xff 0xdc 0x08
+
+# CHECK: xssubqpo 7, 31, 27
+0xfc 0xff 0xdc 0x09
+
+# CHECK: xsmaddqp 7, 31, 27
+0xfc 0xff 0xdb 0x08
+
+# CHECK: xsmaddqpo 7, 31, 27
+0xfc 0xff 0xdb 0x09
+
+# CHECK: xsmsubqp 7, 31, 27
+0xfc 0xff 0xdb 0x48
+
+# CHECK: xsmsubqpo 7, 31, 27
+0xfc 0xff 0xdb 0x49
+
+# CHECK: xsnmaddqp 7, 31, 27
+0xfc 0xff 0xdb 0x88
+
+# CHECK: xsnmaddqpo 7, 31, 27
+0xfc 0xff 0xdb 0x89
+
+# CHECK: xsnmsubqp 7, 31, 27
+0xfc 0xff 0xdb 0xc8
+
+# CHECK: xsnmsubqpo 7, 31, 27
+0xfc 0xff 0xdb 0xc9
Index: test/MC/PowerPC/vsx.s
===================================================================
--- test/MC/PowerPC/vsx.s
+++ test/MC/PowerPC/vsx.s
@@ -547,3 +547,71 @@
 # CHECK-BE: mtvsrwz 0, 3                       # encoding: [0x7c,0x03,0x01,0xe6]
 # CHECK-LE: mtvsrwz 0, 3                       # encoding: [0xe6,0x01,0x03,0x7c]
             mtvsrwz 0, 3
+
+# Power9 Instructions:
+# CHECK-BE: xscpsgnqp 7, 31, 27                # encoding: [0xfc,0xff,0xd8,0xc8]
+# CHECK-LE: xscpsgnqp 7, 31, 27                # encoding: [0xc8,0xd8,0xff,0xfc]
+            xscpsgnqp 7, 31, 27
+# CHECK-BE: xsabsqp 7, 27                      # encoding: [0xfc,0xe0,0xde,0x48]
+# CHECK-LE: xsabsqp 7, 27                      # encoding: [0x48,0xde,0xe0,0xfc]
+            xsabsqp 7, 27
+# CHECK-BE: xsnegqp 7, 27                      # encoding: [0xfc,0xf0,0xde,0x48]
+# CHECK-LE: xsnegqp 7, 27                      # encoding: [0x48,0xde,0xf0,0xfc]
+            xsnegqp 7, 27
+# CHECK-BE: xsnabsqp 7, 27                     # encoding: [0xfc,0xe8,0xde,0x48]
+# CHECK-LE: xsnabsqp 7, 27                     # encoding: [0x48,0xde,0xe8,0xfc]
+            xsnabsqp 7, 27
+# CHECK-BE: xsaddqp 7, 31, 27                  # encoding: [0xfc,0xff,0xd8,0x08]
+# CHECK-LE: xsaddqp 7, 31, 27                  # encoding: [0x08,0xd8,0xff,0xfc]
+            xsaddqp 7, 31, 27
+# CHECK-BE: xsaddqpo 7, 31, 27                 # encoding: [0xfc,0xff,0xd8,0x09]
+# CHECK-LE: xsaddqpo 7, 31, 27                 # encoding: [0x09,0xd8,0xff,0xfc]
+            xsaddqpo 7, 31, 27
+# CHECK-BE: xsdivqp 7, 31, 27                  # encoding: [0xfc,0xff,0xdc,0x48]
+# CHECK-LE: xsdivqp 7, 31, 27                  # encoding: [0x48,0xdc,0xff,0xfc]
+            xsdivqp 7, 31, 27
+# CHECK-BE: xsdivqpo 7, 31, 27                 # encoding: [0xfc,0xff,0xdc,0x49]
+# CHECK-LE: xsdivqpo 7, 31, 27                 # encoding: [0x49,0xdc,0xff,0xfc]
+            xsdivqpo 7, 31, 27
+# CHECK-BE: xsmulqp 7, 31, 27                  # encoding: [0xfc,0xff,0xd8,0x48]
+# CHECK-LE: xsmulqp 7, 31, 27                  # encoding: [0x48,0xd8,0xff,0xfc]
+            xsmulqp 7, 31, 27
+# CHECK-BE: xsmulqpo 7, 31, 27                 # encoding: [0xfc,0xff,0xd8,0x49]
+# CHECK-LE: xsmulqpo 7, 31, 27                 # encoding: [0x49,0xd8,0xff,0xfc]
+            xsmulqpo 7, 31, 27
+# CHECK-BE: xssqrtqp 7, 31, 27                 # encoding: [0xfc,0xff,0xde,0x48]
+# CHECK-LE: xssqrtqp 7, 31, 27                 # encoding: [0x48,0xde,0xff,0xfc]
+            xssqrtqp 7, 31, 27
+# CHECK-BE: xssqrtqpo 7, 31, 27                # encoding: [0xfc,0xff,0xde,0x49]
+# CHECK-LE: xssqrtqpo 7, 31, 27                # encoding: [0x49,0xde,0xff,0xfc]
+            xssqrtqpo 7, 31, 27
+# CHECK-BE: xssubqp 7, 31, 27                  # encoding: [0xfc,0xff,0xdc,0x08]
+# CHECK-LE: xssubqp 7, 31, 27                  # encoding: [0x08,0xdc,0xff,0xfc]
+            xssubqp 7, 31, 27
+# CHECK-BE: xssubqpo 7, 31, 27                 # encoding: [0xfc,0xff,0xdc,0x09]
+# CHECK-LE: xssubqpo 7, 31, 27                 # encoding: [0x09,0xdc,0xff,0xfc]
+            xssubqpo 7, 31, 27
+# CHECK-BE: xsmaddqp 7, 31, 27                 # encoding: [0xfc,0xff,0xdb,0x08]
+# CHECK-LE: xsmaddqp 7, 31, 27                 # encoding: [0x08,0xdb,0xff,0xfc]
+            xsmaddqp 7, 31, 27
+# CHECK-BE: xsmaddqpo 7, 31, 27                # encoding: [0xfc,0xff,0xdb,0x09]
+# CHECK-LE: xsmaddqpo 7, 31, 27                # encoding: [0x09,0xdb,0xff,0xfc]
+            xsmaddqpo 7, 31, 27
+# CHECK-BE: xsmsubqp 7, 31, 27                 # encoding: [0xfc,0xff,0xdb,0x48]
+# CHECK-LE: xsmsubqp 7, 31, 27                 # encoding: [0x48,0xdb,0xff,0xfc]
+            xsmsubqp 7, 31, 27
+# CHECK-BE: xsmsubqpo 7, 31, 27                # encoding: [0xfc,0xff,0xdb,0x49]
+# CHECK-LE: xsmsubqpo 7, 31, 27                # encoding: [0x49,0xdb,0xff,0xfc]
+            xsmsubqpo 7, 31, 27
+# CHECK-BE: xsnmaddqp 7, 31, 27                # encoding: [0xfc,0xff,0xdb,0x88]
+# CHECK-LE: xsnmaddqp 7, 31, 27                # encoding: [0x88,0xdb,0xff,0xfc]
+            xsnmaddqp 7, 31, 27
+# CHECK-BE: xsnmaddqpo 7, 31, 27               # encoding: [0xfc,0xff,0xdb,0x89]
+# CHECK-LE: xsnmaddqpo 7, 31, 27               # encoding: [0x89,0xdb,0xff,0xfc]
+            xsnmaddqpo 7, 31, 27
+# CHECK-BE: xsnmsubqp 7, 31, 27                # encoding: [0xfc,0xff,0xdb,0xc8]
+# CHECK-LE: xsnmsubqp 7, 31, 27                # encoding: [0xc8,0xdb,0xff,0xfc]
+            xsnmsubqp 7, 31, 27
+# CHECK-BE: xsnmsubqpo 7, 31, 27               # encoding: [0xfc,0xff,0xdb,0xc9]
+# CHECK-LE: xsnmsubqpo 7, 31, 27               # encoding: [0xc9,0xdb,0xff,0xfc]
+            xsnmsubqpo 7, 31, 27