diff --git a/llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll --- a/llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll @@ -87,3 +87,51 @@ %4 = trunc i64 %3 to i32 ret i32 %4 } + +define @demanded_bits_lo(i64 %x) { +; CHECK-LABEL: demanded_bits_lo: +; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 4(sp) +; CHECK-NEXT: sw a0, 0(sp) +; CHECK-NEXT: mv a0, sp +; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; CHECK-NEXT: vlse64.v v8, (a0), zero +; CHECK-NEXT: sw zero, 12(sp) +; CHECK-NEXT: li a0, -1 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vand.vv v8, v8, v10 +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: ret + %1 = insertelement poison, i64 %x, i32 0 + %2 = shufflevector %1, poison, zeroinitializer + %3 = and %2, shufflevector( insertelement( poison, i64 u0xffffffff, i32 0), poison, zeroinitializer) + ret %3 +} + +define @demanded_bits_hi(i64 %x) { +; CHECK-LABEL: demanded_bits_hi: +; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sw a1, 4(sp) +; CHECK-NEXT: sw a0, 0(sp) +; CHECK-NEXT: mv a0, sp +; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; CHECK-NEXT: vlse64.v v8, (a0), zero +; CHECK-NEXT: li a0, -1 +; CHECK-NEXT: sw a0, 12(sp) +; CHECK-NEXT: sw zero, 8(sp) +; CHECK-NEXT: addi a0, sp, 8 +; CHECK-NEXT: vlse64.v v10, (a0), zero +; CHECK-NEXT: vand.vv v8, v8, v10 +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: ret + %1 = insertelement poison, i64 %x, i32 0 + %2 = shufflevector %1, poison, zeroinitializer + %3 = and %2, shufflevector( insertelement( poison, i64 u0xffffffff00000000, i32 0), poison, zeroinitializer) + ret %3 +}