diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -3143,7 +3143,7 @@ int sew, string Constraint = "", bit Commutable = 0> { - let VLMul = MInfo.value in { + let VLMul = MInfo.value, SEW=sew in { defvar mx = MInfo.MX; let isCommutable = Commutable in def "_" # mx # "_E" # sew : VPseudoTernaryNoMaskWithPolicy; @@ -3158,7 +3158,7 @@ int sew, string Constraint = "", bit Commutable = 0> { - let VLMul = MInfo.value in { + let VLMul = MInfo.value, SEW=sew in { defvar mx = MInfo.MX; let isCommutable = Commutable in def "_" # mx # "_E" # sew diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/reductions.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/reductions.s new file mode 100644 --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/reductions.s @@ -0,0 +1,293 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s + +# Single-Width Integer Reductions, Vector Widening Integer Reductions, +# and Vector Single-Width FP Reductions +vsetvli zero, zero, e8, m1, tu, mu +vredsum.vs v4, v8, v12 +vsetvli zero, zero, e8, m2, tu, mu +vredmaxu.vs v4, v8, v12 +vsetvli zero, zero, e8, m4, tu, mu +vredmax.vs v4, v8, v12 +vsetvli zero, zero, e8, m8, tu, mu +vredmax.vs v4, v8, v12 +vsetvli zero, zero, e16, m1, tu, mu +vredminu.vs v4, v8, v12 +vsetvli zero, zero, e16, m2, tu, mu +vredmin.vs v4, v8, v12 +vsetvli zero, zero, e16, m4, tu, mu +vredand.vs v4, v8, v12 +vsetvli zero, zero, e16, m8, tu, mu +vredor.vs v4, v8, v12 +vsetvli zero, zero, e32, m1, tu, mu +vredxor.vs v4, v8, v12 +vsetvli zero, zero, e32, m2, tu, mu +vwredsumu.vs v4, v8, v12 +vsetvli zero, zero, e32, m4, tu, mu +vwredsum.vs v4, v8, v12 +vsetvli zero, zero, e32, m8, tu, mu +vfredosum.vs v4, v8, v12 +vsetvli zero, zero, e64, m1, tu, mu +vfredusum.vs v4, v8, v12 +vsetvli zero, zero, e64, m2, tu, mu +vfredmax.vs v4, v8, v12 +vsetvli zero, zero, e64, m4, tu, mu +vfredmin.vs v4, v8, v12 +vsetvli zero, zero, e64, m8, tu, mu +vfredmin.vs v4, v8, v12 +vsetvli zero, zero, e8, mf2, tu, mu +vredsum.vs v4, v8, v12 +vsetvli zero, zero, e8, mf4, tu, mu +vredmaxu.vs v4, v8, v12 +vsetvli zero, zero, e8, mf8, tu, mu +vredmax.vs v4, v8, v12 +vsetvli zero, zero, e16, mf2, tu, mu +vredminu.vs v4, v8, v12 +vsetvli zero, zero, e16, mf4, tu, mu +vredmin.vs v4, v8, v12 +vsetvli zero, zero, e16, mf8, tu, mu +vredand.vs v4, v8, v12 +vsetvli zero, zero, e32, mf2, tu, mu +vredxor.vs v4, v8, v12 +vsetvli zero, zero, e32, mf4, tu, mu +vwredsumu.vs v4, v8, v12 +vsetvli zero, zero, e32, mf8, tu, mu +vwredsum.vs v4, v8, v12 +vsetvli zero, zero, e64, mf2, tu, mu +vfredusum.vs v4, v8, v12 +vsetvli zero, zero, e64, mf4, tu, mu +vfredmax.vs v4, v8, v12 +vsetvli zero, zero, e64, mf8, tu, mu + +# Vector Single-Width FP Reduction Instructions +vsetvli zero, zero, e32, m1, tu, mu +vfwredosum.vs v4, v8, v12 +vsetvli zero, zero, e32, m2, tu, mu +vfwredusum.vs v4, v8, v12 +vsetvli zero, zero, e32, m4, tu, mu +vfwredosum.vs v4, v8, v12 +vsetvli zero, zero, e32, m8, tu, mu +vfwredusum.vs v4, v8, v12 +vsetvli zero, zero, e64, m1, tu, mu +vfwredosum.vs v4, v8, v12 +vsetvli zero, zero, e64, m2, tu, mu +vfwredusum.vs v4, v8, v12 +vsetvli zero, zero, e64, m4, tu, mu +vfwredosum.vs v4, v8, v12 +vsetvli zero, zero, e64, m8, tu, mu +vfwredusum.vs v4, v8, v12 +vsetvli zero, zero, e32, mf2, tu, mu +vfwredosum.vs v4, v8, v12 +vsetvli zero, zero, e32, mf4, tu, mu +vfwredusum.vs v4, v8, v12 +vsetvli zero, zero, e32, mf8, tu, mu +vfwredosum.vs v4, v8, v12 +vsetvli zero, zero, e64, mf2, tu, mu +vfwredosum.vs v4, v8, v12 +vsetvli zero, zero, e64, mf4, tu, mu +vfwredusum.vs v4, v8, v12 +vsetvli zero, zero, e64, mf8, tu, mu +vfwredosum.vs v4, v8, v12 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 83 +# CHECK-NEXT: Total Cycles: 8409 +# CHECK-NEXT: Total uOps: 83 + +# CHECK: Dispatch Width: 2 +# CHECK-NEXT: uOps Per Cycle: 0.01 +# CHECK-NEXT: IPC: 0.01 +# CHECK-NEXT: Block RThroughput: 8405.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu +# CHECK-NEXT: 1 45 45.00 vredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu +# CHECK-NEXT: 1 45 45.00 vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu +# CHECK-NEXT: 1 45 45.00 vredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu +# CHECK-NEXT: 1 45 45.00 vredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu +# CHECK-NEXT: 1 40 40.00 vredminu.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu +# CHECK-NEXT: 1 40 40.00 vredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu +# CHECK-NEXT: 1 40 40.00 vredand.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu +# CHECK-NEXT: 1 40 40.00 vredor.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: 1 35 35.00 vredxor.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: 1 35 35.00 vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: 1 35 35.00 vwredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: 1 640 640.00 vfredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu +# CHECK-NEXT: 1 30 30.00 vfredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu +# CHECK-NEXT: 1 30 30.00 vfredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu +# CHECK-NEXT: 1 30 30.00 vfredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu +# CHECK-NEXT: 1 30 30.00 vfredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu +# CHECK-NEXT: 1 45 45.00 vredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu +# CHECK-NEXT: 1 45 45.00 vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu +# CHECK-NEXT: 1 45 45.00 vredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu +# CHECK-NEXT: 1 45 45.00 vredminu.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu +# CHECK-NEXT: 1 40 40.00 vredmin.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf8, tu, mu +# CHECK-NEXT: 1 40 40.00 vredand.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: 1 45 45.00 vredxor.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf4, tu, mu +# CHECK-NEXT: 1 45 45.00 vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf8, tu, mu +# CHECK-NEXT: 1 35 35.00 vwredsum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, mf2, tu, mu +# CHECK-NEXT: 1 40 40.00 vfredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, mf4, tu, mu +# CHECK-NEXT: 1 40 40.00 vfredmax.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, mf8, tu, mu +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: 1 35 35.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: 1 35 35.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: 1 35 35.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: 1 35 35.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu +# CHECK-NEXT: 1 1280 1280.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu +# CHECK-NEXT: 1 40 40.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu +# CHECK-NEXT: 1 1280 1280.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu +# CHECK-NEXT: 1 40 40.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: 1 1280 1280.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf4, tu, mu +# CHECK-NEXT: 1 40 40.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf8, tu, mu +# CHECK-NEXT: 1 35 35.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, mf2, tu, mu +# CHECK-NEXT: 1 1280 1280.00 vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, mf4, tu, mu +# CHECK-NEXT: 1 40 40.00 vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, mf8, tu, mu +# CHECK-NEXT: 1 1280 1280.00 vfwredosum.vs v4, v8, v12 + +# CHECK: Resources: +# CHECK-NEXT: [0] - SiFive7FDiv +# CHECK-NEXT: [1] - SiFive7IDiv +# CHECK-NEXT: [2] - SiFive7PipeA +# CHECK-NEXT: [3] - SiFive7PipeB +# CHECK-NEXT: [4] - SiFive7PipeV +# CHECK-NEXT: [5] - SiFive7VA +# CHECK-NEXT: [6] - SiFive7VL +# CHECK-NEXT: [7] - SiFive7VS + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] +# CHECK-NEXT: - - 42.00 - 8405.00 8405.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu +# CHECK-NEXT: - - - - 45.00 45.00 - - vredsum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu +# CHECK-NEXT: - - - - 45.00 45.00 - - vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu +# CHECK-NEXT: - - - - 45.00 45.00 - - vredmax.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu +# CHECK-NEXT: - - - - 45.00 45.00 - - vredmax.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu +# CHECK-NEXT: - - - - 40.00 40.00 - - vredminu.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu +# CHECK-NEXT: - - - - 40.00 40.00 - - vredmin.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu +# CHECK-NEXT: - - - - 40.00 40.00 - - vredand.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu +# CHECK-NEXT: - - - - 40.00 40.00 - - vredor.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: - - - - 35.00 35.00 - - vredxor.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: - - - - 35.00 35.00 - - vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: - - - - 35.00 35.00 - - vwredsum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: - - - - 640.00 640.00 - - vfredosum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu +# CHECK-NEXT: - - - - 30.00 30.00 - - vfredusum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu +# CHECK-NEXT: - - - - 30.00 30.00 - - vfredmax.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu +# CHECK-NEXT: - - - - 30.00 30.00 - - vfredmin.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu +# CHECK-NEXT: - - - - 30.00 30.00 - - vfredmin.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu +# CHECK-NEXT: - - - - 45.00 45.00 - - vredsum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu +# CHECK-NEXT: - - - - 45.00 45.00 - - vredmaxu.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu +# CHECK-NEXT: - - - - 45.00 45.00 - - vredmax.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu +# CHECK-NEXT: - - - - 45.00 45.00 - - vredminu.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu +# CHECK-NEXT: - - - - 40.00 40.00 - - vredmin.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf8, tu, mu +# CHECK-NEXT: - - - - 40.00 40.00 - - vredand.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: - - - - 45.00 45.00 - - vredxor.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf4, tu, mu +# CHECK-NEXT: - - - - 45.00 45.00 - - vwredsumu.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf8, tu, mu +# CHECK-NEXT: - - - - 35.00 35.00 - - vwredsum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, mf2, tu, mu +# CHECK-NEXT: - - - - 40.00 40.00 - - vfredusum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, mf4, tu, mu +# CHECK-NEXT: - - - - 40.00 40.00 - - vfredmax.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, mf8, tu, mu +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: - - - - 35.00 35.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: - - - - 35.00 35.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: - - - - 35.00 35.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: - - - - 35.00 35.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu +# CHECK-NEXT: - - - - 1280.00 1280.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu +# CHECK-NEXT: - - - - 40.00 40.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu +# CHECK-NEXT: - - - - 1280.00 1280.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu +# CHECK-NEXT: - - - - 40.00 40.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: - - - - 1280.00 1280.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf4, tu, mu +# CHECK-NEXT: - - - - 40.00 40.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf8, tu, mu +# CHECK-NEXT: - - - - 35.00 35.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, mf2, tu, mu +# CHECK-NEXT: - - - - 1280.00 1280.00 - - vfwredosum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, mf4, tu, mu +# CHECK-NEXT: - - - - 40.00 40.00 - - vfwredusum.vs v4, v8, v12 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, mf8, tu, mu +# CHECK-NEXT: - - - - 1280.00 1280.00 - - vfwredosum.vs v4, v8, v12