diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -4227,13 +4227,16 @@ return SDValue(); unsigned ViaEltSize = std::max((uint64_t)8, PowerOf2Ceil(NumElts)); - MVT ViaVT = MVT::getVectorVT(MVT::getIntegerVT(ViaEltSize), 1); - MVT ViaBitVT = MVT::getVectorVT(MVT::i1, ViaVT.getScalarSizeInBits()); + EVT ViaVT = EVT::getVectorVT( + *DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), ViaEltSize), 1); + EVT ViaBitVT = + EVT::getVectorVT(*DAG.getContext(), MVT::i1, ViaVT.getScalarSizeInBits()); // If we don't have zvbb or the larger element type > ELEN, the operation will // be illegal. if (!Subtarget.getTargetLowering()->isOperationLegalOrCustom(ISD::BITREVERSE, - ViaVT)) + ViaVT) || + !Subtarget.getTargetLowering()->isTypeLegal(ViaBitVT)) return SDValue(); // If the bit vector doesn't fit exactly into the larger element type, we need diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse-bitrotate.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse-bitrotate.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse-bitrotate.ll @@ -0,0 +1,22 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc -mtriple=riscv32 -mattr=+v,+zvl1024b -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvl1024b -verify-machineinstrs < %s | FileCheck %s + + +define <256 x i1> @reverse_v256i1(<256 x i1> %a) { +; CHECK-LABEL: reverse_v256i1: +; CHECK: # %bb.0: +; CHECK-NEXT: li a0, 256 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 +; CHECK-NEXT: vid.v v10 +; CHECK-NEXT: vrsub.vi v10, v10, -1 +; CHECK-NEXT: vrgather.vv v12, v8, v10 +; CHECK-NEXT: vmsne.vi v0, v12, 0 +; CHECK-NEXT: ret + %res = call <256 x i1> @llvm.experimental.vector.reverse.v256i1(<256 x i1> %a) + ret <256 x i1> %res +} + +declare <256 x i1> @llvm.experimental.vector.reverse.v256i1(<256 x i1>)