diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp --- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp @@ -46,6 +46,8 @@ bool GetAllRegSet = false) const; bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; + bool selectCmp(MachineInstr &MI, MachineIRBuilder &MIB, + MachineRegisterInfo &MRI) const; bool selectCopy(MachineInstr &MI, MachineRegisterInfo &MRI) const; bool selectConstant(MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) const; @@ -117,6 +119,20 @@ if (!selectConstant(MI, MIB, MRI)) return false; break; + case TargetOpcode::G_IMPLICIT_DEF: { + MI.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF)); + const LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); + const Register DstReg = MI.getOperand(0).getReg(); + const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); + const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB); + RBI.constrainGenericRegister(DstReg, *DstRC, MRI); + return true; + } + case TargetOpcode::G_ICMP: { + if (!selectCmp(MI, MIB, MRI)) + return false; + break; + } default: return false; } @@ -137,6 +153,141 @@ return nullptr; } +bool RISCVInstructionSelector::selectCmp(MachineInstr &MI, + MachineIRBuilder &MIB, + MachineRegisterInfo &MRI) const { + if (MI.getOpcode() != TargetOpcode::G_ICMP) + return false; + + Register DstReg = MI.getOperand(0).getReg(); + const CmpInst::Predicate Pred = + static_cast(MI.getOperand(1).getPredicate()); + Register SrcReg1 = MI.getOperand(2).getReg(); + Register SrcReg2 = MI.getOperand(3).getReg(); + + // Check if there's an immediate + bool HasImm = false; + int64_t Imm; + const MachineInstr *Src2 = MRI.getVRegDef(SrcReg2); + if (Src2->getOpcode() == TargetOpcode::G_CONSTANT) { + Imm = Src2->getOperand(1).getCImm()->getSExtValue(); + HasImm = isInt<12>(Imm); + } + + auto buildLT = [&MIB, this](Register DstReg, Register SrcReg1, + Register SrcReg2, bool IsSigned) { + MachineInstr *Result = MIB.buildInstr(IsSigned ? RISCV::SLT : RISCV::SLTU) + .addDef(DstReg) + .addReg(SrcReg1) + .addReg(SrcReg2); + return constrainSelectedInstRegOperands(*Result, TII, TRI, RBI); + }; + + auto buildLTImm = [&MIB, this](Register DstReg, Register SrcReg, int64_t Imm, + bool IsSigned) { + MachineInstr *Result = MIB.buildInstr(IsSigned ? RISCV::SLTI : RISCV::SLTIU) + .addDef(DstReg) + .addReg(SrcReg) + .addImm(Imm); + return constrainSelectedInstRegOperands(*Result, TII, TRI, RBI); + }; + + auto buildNOT = [&MIB, this](Register DstReg, Register SrcReg) { + MachineInstr *Result = + MIB.buildInstr(RISCV::XORI).addDef(DstReg).addReg(SrcReg).addImm(1); + errs() << "THERE\n"; + return constrainSelectedInstRegOperands(*Result, TII, TRI, RBI); + }; + + auto buildSUBI = [&MIB, this](Register DstReg, Register SrcReg, int64_t Imm) { + MachineInstr *Result = MIB.buildInstr(RISCV::ADDI) + .addDef(DstReg) + .addReg(SrcReg) + .addImm(Imm - 1); + return constrainSelectedInstRegOperands(*Result, TII, TRI, RBI); + }; + + auto buildXOR = [&MIB, this](Register DstReg, Register SrcReg1, + Register SrcReg2) { + MachineInstr *Result = MIB.buildInstr(RISCV::XOR) + .addDef(DstReg) + .addReg(SrcReg1) + .addReg(SrcReg2); + return constrainSelectedInstRegOperands(*Result, TII, TRI, RBI); + }; + + switch (Pred) { + case CmpInst::Predicate::ICMP_UGT: + case CmpInst::Predicate::ICMP_SGT: { + bool IsSigned = Pred == CmpInst::Predicate::ICMP_SGT; + Register TmpReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + + if (!HasImm && !buildLT(DstReg, SrcReg2, SrcReg1, IsSigned)) + return false; + + if (!HasImm) + break; + + if (!buildLTImm(TmpReg, SrcReg1, Imm + 1, IsSigned)) + return false; + + if (!buildNOT(DstReg, TmpReg)) + return false; + + break; + } + case CmpInst::Predicate::ICMP_EQ: + case CmpInst::Predicate::ICMP_NE: { + bool IsEQ = Pred == CmpInst::Predicate::ICMP_EQ; + Register TmpReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + + if (!HasImm && !buildXOR(TmpReg, SrcReg1, SrcReg2)) + return false; + + if (HasImm && !Imm) + TmpReg = SrcReg1; + + if (HasImm && Imm && !buildSUBI(TmpReg, SrcReg1, Imm)) + return false; + + if (IsEQ && !buildLTImm(DstReg, TmpReg, 1, /* IsSigned */ false)) + return false; + + if (!IsEQ && !buildLT(DstReg, RISCV::X0, TmpReg, /* IsSigned */ false)) + return false; + + break; + } + case CmpInst::Predicate::ICMP_ULE: + case CmpInst::Predicate::ICMP_SLE: + case CmpInst::Predicate::ICMP_UGE: + case CmpInst::Predicate::ICMP_SGE: { + bool IsSigned = Pred == CmpInst::Predicate::ICMP_SLE || + Pred == CmpInst::Predicate::ICMP_SGE; + bool IsLE = Pred == CmpInst::Predicate::ICMP_ULE || + Pred == CmpInst::Predicate::ICMP_SLE; + Register TmpReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + + if (!IsLE) + std::swap(SrcReg1, SrcReg2); + + if (!buildLT(TmpReg, SrcReg1, SrcReg2, IsSigned)) + return false; + + if (!buildNOT(DstReg, TmpReg)) + return false; + + errs() << "HERE\n"; + + break; + } + default: + llvm_unreachable("Not handled pred!"); + } + + return true; +} + bool RISCVInstructionSelector::selectCopy(MachineInstr &MI, MachineRegisterInfo &MRI) const { Register DstReg = MI.getOperand(0).getReg(); diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cmp32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cmp32.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cmp32.mir @@ -0,0 +1,537 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32I %s +--- +name: cmp_ult_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ult_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_slt_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SLT]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ugt_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_sgt_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLT]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_eq_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[XOR]], 1 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ne_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[XOR]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ule_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_sle_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_uge_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_sge_i32 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulti_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ulti_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 10 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slti_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_slti_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTI:%[0-9]+]]:gpr = SLTI [[COPY]], 10 + ; RV32I-NEXT: $x10 = COPY [[SLTI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugti_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ugti_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 11 + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTIU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgti_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_sgti_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTI:%[0-9]+]]:gpr = SLTI [[COPY]], 11 + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTI]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eqi_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_eqi_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 9 + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[ADDI]], 1 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_nei_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_nei_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 9 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ADDI]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulei_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ulei_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[ADDI]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_slei_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_slei_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[ADDI]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugei_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ugei_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgei_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_sgei_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[ADDI]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 10 + %2:gprb(s32) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq0_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_eq0_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 1 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 0 + %2:gprb(s32) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne0_i32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ne0_i32 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = G_CONSTANT i32 0 + %2:gprb(s32) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s32) + PseudoRET implicit $x10 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cmp64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cmp64.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/cmp64.mir @@ -0,0 +1,538 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32I %s +--- +name: cmp_ult_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ult_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slt_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_slt_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; RV32I-NEXT: $x10 = COPY [[SLT]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugt_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ugt_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgt_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_sgt_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; RV32I-NEXT: $x10 = COPY [[SLT]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_eq_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[XOR]], 1 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ne_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[XOR]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ule_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_ule_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sle_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_sle_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[COPY1]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_uge_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_uge_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY1]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sge_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; RV32I-LABEL: name: cmp_sge_i64 + ; RV32I: liveins: $x10, $x11 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY1]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulti_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ulti_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 10 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ult), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slti_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_slti_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTI:%[0-9]+]]:gpr = SLTI [[COPY]], 10 + ; RV32I-NEXT: $x10 = COPY [[SLTI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(slt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugti_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ugti_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 11 + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTIU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ugt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgti_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_sgti_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTI:%[0-9]+]]:gpr = SLTI [[COPY]], 11 + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTI]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(sgt), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eqi_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_eqi_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 9 + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[ADDI]], 1 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_nei_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_nei_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 9 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ADDI]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ulei_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ulei_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[ADDI]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ule), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_slei_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_slei_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[COPY]], [[ADDI]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(sle), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ugei_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ugei_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADDI]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLTU]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(uge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_sgei_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_sgei_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 10 + ; RV32I-NEXT: [[SLT:%[0-9]+]]:gpr = SLT [[ADDI]], [[COPY]] + ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[SLT]], 1 + ; RV32I-NEXT: $x10 = COPY [[XORI]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(sge), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_eq0_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_eq0_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[COPY]], 1 + ; RV32I-NEXT: $x10 = COPY [[SLTIU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 0 + %2:gprb(s64) = G_ICMP intpred(eq), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... +--- +name: cmp_ne0_i64 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + + ; RV32I-LABEL: name: cmp_ne0_i64 + ; RV32I: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 9 + ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ADDI]] + ; RV32I-NEXT: $x10 = COPY [[SLTU]] + ; RV32I-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = G_CONSTANT i64 10 + %2:gprb(s64) = G_ICMP intpred(ne), %0, %1 + $x10 = COPY %2(s64) + PseudoRET implicit $x10 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def32.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def32.mir @@ -0,0 +1,23 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \ +# RUN: | FileCheck %s +--- +name: implicit_def +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: implicit_def + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s32) = G_IMPLICIT_DEF + $x10 = COPY %0(s32) + PseudoRET implicit $x10 + +... diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def64.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def64.mir @@ -0,0 +1,23 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \ +# RUN: | FileCheck %s +--- +name: implicit_def +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10 + + ; CHECK-LABEL: name: implicit_def + ; CHECK: liveins: $x10 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF + ; CHECK-NEXT: $x10 = COPY [[DEF]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = G_IMPLICIT_DEF + $x10 = COPY %0(s64) + PseudoRET implicit $x10 + +...