diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -691,10 +691,6 @@ #endif struct BlockData { - // The VSETVLIInfo that represents the net changes to the VL/VTYPE registers - // made by this block. Calculated in Phase 1. - VSETVLIInfo Change; - // The VSETVLIInfo that represents the VL/VTYPE settings on exit from this // block. Calculated in Phase 2. VSETVLIInfo Exit; @@ -742,9 +738,10 @@ MachineBasicBlock::iterator InsertPt, DebugLoc DL, const VSETVLIInfo &Info, const VSETVLIInfo &PrevInfo); - void transferBefore(VSETVLIInfo &Info, const MachineInstr &MI); - void transferAfter(VSETVLIInfo &Info, const MachineInstr &MI); - bool computeVLVTYPEChanges(const MachineBasicBlock &MBB); + void transferBefore(VSETVLIInfo &Info, const MachineInstr &MI) const; + void transferAfter(VSETVLIInfo &Info, const MachineInstr &MI) const; + bool computeVLVTYPEChanges(const MachineBasicBlock &MBB, + VSETVLIInfo &Info) const; void computeIncomingVLVTYPE(const MachineBasicBlock &MBB); void emitVSETVLIs(MachineBasicBlock &MBB); void doLocalPostpass(MachineBasicBlock &MBB); @@ -1006,7 +1003,8 @@ // Given an incoming state reaching MI, modifies that state so that it is minimally // compatible with MI. The resulting state is guaranteed to be semantically legal // for MI, but may not be the state requested by MI. -void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info, const MachineInstr &MI) { +void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info, + const MachineInstr &MI) const { uint64_t TSFlags = MI.getDesc().TSFlags; if (!RISCVII::hasSEWOp(TSFlags)) return; @@ -1063,7 +1061,8 @@ // Given a state with which we evaluated MI (see transferBefore above for why // this might be different that the state MI requested), modify the state to // reflect the changes MI might make. -void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info, const MachineInstr &MI) { +void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info, + const MachineInstr &MI) const { if (isVectorConfigInstr(MI)) { Info = getInfoForVSETVLI(MI); return; @@ -1082,18 +1081,18 @@ Info = VSETVLIInfo::getUnknown(); } -bool RISCVInsertVSETVLI::computeVLVTYPEChanges(const MachineBasicBlock &MBB) { +bool RISCVInsertVSETVLI::computeVLVTYPEChanges(const MachineBasicBlock &MBB, + VSETVLIInfo &Info) const { bool HadVectorOp = false; - BlockData &BBInfo = BlockInfo[MBB.getNumber()]; - BBInfo.Change = BBInfo.Pred; + Info = BlockInfo[MBB.getNumber()].Pred; for (const MachineInstr &MI : MBB) { - transferBefore(BBInfo.Change, MI); + transferBefore(Info, MI); if (isVectorConfigInstr(MI) || RISCVII::hasSEWOp(MI.getDesc().TSFlags)) HadVectorOp = true; - transferAfter(BBInfo.Change, MI); + transferAfter(Info, MI); } return HadVectorOp; @@ -1132,8 +1131,8 @@ // compatibility checks performed a blocks output state can change based on // the input state. To cache, we'd have to add logic for finding // never-compatible state changes. - computeVLVTYPEChanges(MBB); - VSETVLIInfo TmpStatus = BBInfo.Change; + VSETVLIInfo TmpStatus; + computeVLVTYPEChanges(MBB, TmpStatus); // If the new exit value matches the old exit value, we don't need to revisit // any blocks. @@ -1528,10 +1527,11 @@ // Phase 1 - determine how VL/VTYPE are affected by the each block. for (const MachineBasicBlock &MBB : MF) { - HaveVectorOp |= computeVLVTYPEChanges(MBB); + VSETVLIInfo TmpStatus; + HaveVectorOp |= computeVLVTYPEChanges(MBB, TmpStatus); // Initial exit state is whatever change we found in the block. BlockData &BBInfo = BlockInfo[MBB.getNumber()]; - BBInfo.Exit = BBInfo.Change; + BBInfo.Exit = TmpStatus; LLVM_DEBUG(dbgs() << "Initial exit state of " << printMBBReference(MBB) << " is " << BBInfo.Exit << "\n");