Index: lib/Target/PowerPC/PPC.td
===================================================================
--- lib/Target/PowerPC/PPC.td
+++ lib/Target/PowerPC/PPC.td
@@ -124,6 +124,9 @@
 def FeatureP8Vector  : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
                                         "Enable POWER8 vector instructions",
                                         [FeatureVSX, FeatureP8Altivec]>;
+def FeatureP9        : SubtargetFeature<"power9", "IsP9", "true",
+                                        "Enable POWER9 instructions",
+                                        [FeatureP8Crypto, FeatureP8Vector]>;
 def FeatureDirectMove :
   SubtargetFeature<"direct-move", "HasDirectMove", "true",
                    "Enable Power8 direct move instructions",
Index: lib/Target/PowerPC/PPCInstrAltivec.td
===================================================================
--- lib/Target/PowerPC/PPCInstrAltivec.td
+++ lib/Target/PowerPC/PPCInstrAltivec.td
@@ -1213,3 +1213,33 @@
                               int_ppc_altivec_crypto_vncipherlast, v2i64>;
 def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;
 } // HasP8Crypto
+
+// The following altivec instructions were introduced in Power ISA 3.0
+def P9Instrs : Predicate<"PPCSubTarget->isP9()">;
+let Predicates = [P9Instrs] in {
+
+def VBPERMD : VXForm_1<1484, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+                       "vbpermd $vD, $vA, $vB", IIC_VecFP, []>;
+
+class VXEO_GVV<bits<11> xo, bits<5> eo, string opc>
+  : VXForm_EO<xo, eo, (outs g8rc:$rD), (ins vrrc:$vB),
+              !strconcat(opc, " $rD, $vB"), IIC_VecGeneral,
+              []>;
+
+class VXEO_VVV<bits<11> xo, bits<5> eo, string opc>
+  : VXForm_EO<xo, eo, (outs vrrc:$vD), (ins vrrc:$vB),
+              !strconcat(opc, " $vD, $vB"), IIC_VecGeneral,
+              []>;
+
+// Vector Count Leading/Trailing Zero LSB, dest register is gpr
+def VCLZLSBB : VXEO_GVV<1538, 0, "vclzlsbb">;
+def VCTZLSBB : VXEO_GVV<1538, 1, "vctzlsbb">;
+
+// Vector Count Trailing Zeros
+// TODO: map to llvm cttz?
+def VCTZB : VXEO_VVV<1538, 28, "vctzb">;
+def VCTZH : VXEO_VVV<1538, 29, "vctzh">;
+def VCTZW : VXEO_VVV<1538, 30, "vctzw">;
+def VCTZD : VXEO_VVV<1538, 31, "vctzd">;
+} // end P9Instrs
+
Index: lib/Target/PowerPC/PPCInstrFormats.td
===================================================================
--- lib/Target/PowerPC/PPCInstrFormats.td
+++ lib/Target/PowerPC/PPCInstrFormats.td
@@ -1571,6 +1571,21 @@
   let Inst{21-31} = xo;
 }
 
+/// VXForm_EO - [PO, VRT, EO, VRB, XO]
+class VXForm_EO<bits<11> xo, bits<5> eo, dag OOL, dag IOL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OOL, IOL, asmstr, itin> {
+  bits<5> RD;
+  bits<5> VB;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = RD;
+  let Inst{11-15} = eo;
+  let Inst{16-20} = VB;
+  let Inst{21-31} = xo;
+}
+
 /// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX"
 class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
Index: lib/Target/PowerPC/PPCSubtarget.h
===================================================================
--- lib/Target/PowerPC/PPCSubtarget.h
+++ lib/Target/PowerPC/PPCSubtarget.h
@@ -111,6 +111,7 @@
   bool IsE500;
   bool IsPPC4xx;
   bool IsPPC6xx;
+  bool IsP9;
   bool FeatureMFTB;
   bool DeprecatedDST;
   bool HasLazyResolverStubs;
@@ -241,6 +242,7 @@
   bool isPPC4xx() const { return IsPPC4xx; }
   bool isPPC6xx() const { return IsPPC6xx; }
   bool isE500() const { return IsE500; }
+  bool isP9() const { return IsP9; }
   bool isFeatureMFTB() const { return FeatureMFTB; }
   bool isDeprecatedDST() const { return DeprecatedDST; }
   bool hasICBT() const { return HasICBT; }
Index: lib/Target/PowerPC/PPCSubtarget.cpp
===================================================================
--- lib/Target/PowerPC/PPCSubtarget.cpp
+++ lib/Target/PowerPC/PPCSubtarget.cpp
@@ -92,6 +92,7 @@
   IsPPC4xx = false;
   IsPPC6xx = false;
   IsE500 = false;
+  IsP9 = false;
   FeatureMFTB = false;
   DeprecatedDST = false;
   HasLazyResolverStubs = false;
Index: test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
===================================================================
--- test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
+++ test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
@@ -672,3 +672,26 @@
 # CHECK: mfvscr 2                        
 0x10 0x40 0x06 0x04
 
+# Power9 instructions
+
+# CHECK: vbpermd 2, 5, 17
+0x10 0x45 0x8d 0xcc
+
+# CHECK: vclzlsbb 2, 3
+0x10 0x40 0x1e 0x02
+
+# CHECK: vctzlsbb 2, 3
+0x10 0x41 0x1e 0x02
+
+# CHECK: vctzb 2, 3
+0x10 0x5c 0x1e 0x02
+
+# CHECK: vctzh 2, 3
+0x10 0x5d 0x1e 0x02
+
+# CHECK: vctzw 2, 3
+0x10 0x5e 0x1e 0x02
+
+# CHECK: vctzd 2, 3
+0x10 0x5f 0x1e 0x02
+
Index: test/MC/PowerPC/ppc64-encoding-vmx.s
===================================================================
--- test/MC/PowerPC/ppc64-encoding-vmx.s
+++ test/MC/PowerPC/ppc64-encoding-vmx.s
@@ -742,3 +742,31 @@
 # CHECK-LE: mfvscr 2                        # encoding: [0x04,0x06,0x40,0x10]
             mfvscr 2
 
+# Power9 instructions
+
+# CHECK-BE: vbpermd 2, 5, 17                # encoding: [0x10,0x45,0x8d,0xcc]
+# CHECK-LE: vbpermd 2, 5, 17                # encoding: [0xcc,0x8d,0x45,0x10]
+            vbpermd 2, 5, 17
+
+# Vector count trailing zero instructions
+# CHECK-BE: vctzb 2, 3                      # encoding: [0x10,0x5c,0x1e,0x02]
+# CHECK-LE: vctzb 2, 3                      # encoding: [0x02,0x1e,0x5c,0x10]
+            vctzb 2, 3
+# CHECK-BE: vctzh 2, 3                      # encoding: [0x10,0x5d,0x1e,0x02]
+# CHECK-LE: vctzh 2, 3                      # encoding: [0x02,0x1e,0x5d,0x10]
+            vctzh 2, 3
+# CHECK-BE: vctzw 2, 3                      # encoding: [0x10,0x5e,0x1e,0x02]
+# CHECK-LE: vctzw 2, 3                      # encoding: [0x02,0x1e,0x5e,0x10]
+            vctzw 2, 3
+# CHECK-BE: vctzd 2, 3                      # encoding: [0x10,0x5f,0x1e,0x02]
+# CHECK-LE: vctzd 2, 3                      # encoding: [0x02,0x1e,0x5f,0x10]
+            vctzd 2, 3
+
+# LSB version of vector count leading/trailing zero instructions
+# CHECK-BE: vclzlsbb 2, 3                   # encoding: [0x10,0x40,0x1e,0x02]
+# CHECK-LE: vclzlsbb 2, 3                   # encoding: [0x02,0x1e,0x40,0x10]
+            vclzlsbb 2, 3
+# CHECK-BE: vctzlsbb 2, 3                   # encoding: [0x10,0x41,0x1e,0x02]
+# CHECK-LE: vctzlsbb 2, 3                   # encoding: [0x02,0x1e,0x41,0x10]
+            vctzlsbb 2, 3
+